Flash memory rereading method and device, medium and product

Abstract

The invention discloses a flash memory rereading method and device, a medium and a product, and relates to the technical field of storage. According to the scheme, the syndrome weight returned when the low-density parity check code is successfully decoded and the basic characteristics of the NAND flash memory are fully utilized, and when the decoding is failed under the default voltage, the initial syndrome weight in the low-density parity check code decoder is recorded; selecting a target voltage axis meeting a preset requirement in the reread voltage axis table and executing a reread decoding operation; if the decoding fails, the new syndrome weight returned when the decoding fails and the previously reserved initial syndrome weight are utilized to timely correct the direction of the re-reading attempt error, a new target voltage axis is determined in the re-reading voltage axis table, and the decoding operation is repeated until the decoding is successful, so that the re-reading time delay is greatly reduced, and the decoding efficiency is improved. And the voltage axis selection efficiency and the SSD performance are improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a flash memory rereading method, device, medium and product. Background Art

[0002] The physical characteristics of NAND flash memory may cause read errors during use. Solid State Drives (SSDs) usually use Low Density Parity Code (LDPC) for data protection. When the number of read error bits exceeds the LDPC decoding capability, the SSD triggers a reread mechanism to reduce the number of error bits by adjusting the voltage axis. NAND flash memory manufacturers provide a reread voltage axis table that contains multiple offset voltage axes to accommodate different physical scenarios. The current reread execution process has two methods: one is to try the read voltages in the table one by one, and the other is to record the number of successes for each voltage axis and perform the reread operation in order of success rate from large to small.

[0003] However, both methods have disadvantages: trying each voltage axis one by one consumes a lot of time delay, and the method of only recording the number of successes can reduce the number of rereads, but does not fully utilize the additional return information of the decoder. When multiple voltage axes have similar success rates, the efficiency improvement is limited.

[0004] In view of the above, how to solve the problem that the current voltage axis selection method in the SSD re-read process has high latency and low efficiency, which has an adverse effect on SSD performance, is an urgent problem to be solved by technicians in this field. Summary of the invention

[0005] The present invention provides a flash memory rereading method, device, medium and product to at least solve the problem that the voltage axis selection method in the current SSD rereading process has high delay and low efficiency, which has an adverse effect on SSD performance.

[0006] The present invention provides a flash memory rereading method, which is applied to a solid state hard disk; the method comprises:

[0007] When decoding fails under the default voltage axis, obtaining an initial syndrome weight in the current low-density parity-check code decoder;

[0008] Determining a target voltage axis that meets preset requirements among the voltage axes in the re-read voltage axis table;

[0009] Performing a reread decoding operation based on the target voltage axis and determining whether the decoding is successful;

[0010] If not, obtaining a new syndrome weight in the current low-density parity-check code decoder;

[0011] Determine a new target voltage axis in each voltage axis of the reread voltage axis table according to the initial syndrome weight and the new syndrome weight, and use the new syndrome weight as the initial syndrome weight, and return to the step of performing the reread decoding operation based on the target voltage axis;

[0012] If yes, the re-reading process ends.

[0013] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above flash memory rereading methods when executing the computer program.

[0014] The present invention also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned flash memory rereading methods are implemented.

[0015] The present invention also provides a computer program product, comprising a computer program, which implements the steps of any one of the above flash memory rereading methods when executed by a processor.

[0016] The beneficial effect of the present invention lies in that it makes full use of the syndrome weight returned when the low-density parity-check code is successfully decoded and the basic characteristics of the NAND flash memory. When the decoding fails under the default voltage axis, the initial syndrome weight in the low-density parity-check code decoder is recorded, and the target voltage axis that meets the preset requirements is first selected in the reread voltage axis table and the reread decoding operation is performed; if the decoding fails, the new syndrome weight returned when the decoding fails and the previously retained initial syndrome weight are used to promptly correct the wrong direction of the reread attempt, determine the new target voltage axis in the reread voltage axis table, and repeat the decoding operation until the decoding is successful, which greatly reduces the reread delay and improves the voltage axis selection efficiency and SSD performance.

[0017] In addition, the present invention also provides a flash memory re-reading device, medium and product, with the same effects as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A flowchart of a flash memory rereading method provided by an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of threshold voltage distribution provided by an embodiment of the present invention;

[0021] Figure 3 A schematic diagram of the overall process of flash memory rereading provided by an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of a flash memory rereading device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] It should be noted that, in the description of the present invention, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0025] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0026] At present, due to its physical characteristics, NAND flash memory is affected by factors such as erasure, data retention time, and read interference during use, causing the threshold voltage to shift and widen, thereby causing read errors. To address this problem, SSDs usually use error correction codes, such as LDPC codes, to protect data. When the number of read error bits is within the protection range of the LDPC code, the data can be recovered through a regular read operation. However, when the threshold voltage is severely shifted and widened, using the original read reference voltage for reading will result in too many error bits, exceeding the decoding capability of LDPC, resulting in decoding failure.

[0027] After decoding fails, the SSD triggers a read retry mechanism, which adjusts the voltage axis to offset the offset of the threshold voltage to reduce the number of read error bits. However, the reread operation usually involves a large number of read operations, which will increase the read operation delay and reduce the read performance. Therefore, efficiently selecting a suitable read voltage axis to reduce the impact of the reread operation on performance is the main technical problem solved by the present invention; the application scenario of the present invention is a solid-state hard disk.

[0028] Figure 1A flowchart of a flash memory rereading method provided by an embodiment of the present invention. Figure 1 As shown, the method includes:

[0029] S10: When decoding fails under the default voltage axis, an initial syndrome weight in the current low-density parity-check code decoder is obtained.

[0030] Specifically, when the SSD triggers the reread mechanism and the LDPC decoding fails under the default voltage axis, in order to select a suitable voltage axis for rereading again, the initial syndrome weight in the current LDPC decoder needs to be obtained in this embodiment. The following is an explanation of LDPC and its syndrome weight:

[0031] The decoding algorithm of LDPC is implemented by performing information iteration between check nodes and variable nodes on the Tanner graph. The syndrome weight of decoding is defined as the number of check nodes that failed to pass the check after the first iteration. In the SSD read operation, the syndrome weight is positively correlated with the raw bit error rate (RBER) of the initial data input to the decoder, that is, the higher the RBER of the read data, the larger the syndrome weight. Both RBER and syndrome weight can reflect the degree of deviation of the current voltage axis. At present, the LDPC decoder will return the number of error bits in the read when the read is successful (that is, when the LDPC decoding is successful) (the decoder will report the number of "0" errors into "1" and the number of "1" errors into "0", that is, the number of 0 errors into 1 errors and the number of 1 errors into 0 errors). In addition, the LDPC decoder can obtain the syndrome weight regardless of whether the decoding is successful. It can be understood that the initial syndrome weight in the current LDPC decoder is the syndrome weight output by the decoder when decoding fails under the current default voltage axis.

[0032] S11: Determine a target voltage axis that meets preset requirements among the voltage axes in the re-read voltage axis table.

[0033] It should be noted that NAND flash memory manufacturers usually provide a retry read table (RRT), which usually contains dozens of voltage axes, corresponding to different physical scenarios such as program / erase cycle (PE), data retention time (RET) and read disturbance (RDD).

[0034] In this embodiment, after the initial syndrome weight is obtained, a target voltage axis that meets the preset requirements is determined in each voltage axis of the reread voltage axis table. In this embodiment, there is no limitation on the preset requirements, for example, the voltage axis may have the highest reread success rate or the least number of error bits in the previous reread process, depending on the specific implementation situation.

[0035] S12: Execute a reread decoding operation based on the target voltage axis and determine whether the decoding is successful; if not, proceed to step S13; if yes, end the reread process.

[0036] S13: Obtain a new syndrome weight in the current low-density parity-check code decoder.

[0037] S14: According to the initial syndrome weight and the new syndrome weight, a new target voltage axis is determined in each voltage axis of the re-read voltage axis table, and the new syndrome weight is used as the initial syndrome weight, and the process returns to step S12.

[0038] Furthermore, a reread decoding operation is performed based on the target voltage axis, and it is determined whether the decoding is successful. If the decoding is confirmed to be successful, the rereading process is terminated and the read data is returned to the host. If the decoding is confirmed to be unsuccessful, it is considered that the current target voltage axis still cannot meet the requirements and needs to be reselected.

[0039] Specifically, a new syndrome weight in the current LDPC decoder is obtained. It can be understood that the new syndrome weight here is the syndrome weight in the LDPC decoder when the reread decoding fails under the target voltage axis. Finally, according to the initial syndrome weight and the new syndrome weight, a new target voltage axis is determined in each voltage axis of the reread voltage axis table, and the new syndrome weight is used as the initial syndrome weight, and the step of performing the reread decoding operation based on the target voltage axis is returned to, and the reread decoding operation is repeated until the decoding is successful.

[0040] It should be noted that, in this embodiment, there is no limitation on the specific process of determining a new target voltage axis in each voltage axis of the re-read voltage axis table according to the initial syndrome weight and the new syndrome weight.

[0041] In this embodiment, full use is made of the syndrome weight returned when the low-density parity-check code is successfully decoded and the basic characteristics of the NAND flash memory. When the decoding fails under the default voltage axis, the initial syndrome weight in the low-density parity-check code decoder is recorded, and the target voltage axis that meets the preset requirements is first selected in the reread voltage axis table and the reread decoding operation is performed; if the decoding fails, the new syndrome weight returned when the decoding fails and the previously retained initial syndrome weight are used to promptly correct the wrong direction of the reread attempt, determine the new target voltage axis in the reread voltage axis table, and repeat the decoding operation until the decoding is successful, which greatly reduces the reread delay and improves the voltage axis selection efficiency and SSD performance.

[0042] Based on the above embodiments, in some embodiments, determining a target voltage axis that meets preset requirements in each voltage axis of the re-read voltage axis table includes:

[0043] S111: determining, according to a pre-constructed voltage axis weight table, a target voltage axis having a minimum number of corresponding error bits and on which no reread operation is performed, from among the voltage axes in the reread voltage axis table;

[0044] The voltage axis weight table includes the number of error bits of each voltage axis after reading, and the offset direction relative to the ideal voltage axis.

[0045] In order to select a suitable target voltage axis more quickly and accurately, the present invention utilizes the return value of the LDPC decoder and combines the NAND characteristics to provide an additional voltage axis weight table RRT_weight in addition to RRT in the SSD master control.

[0046] The voltage axis weight table contains the number of error bits of each voltage axis in the RRT after reading, and the offset direction relative to the ideal voltage axis. In other words, the size of the voltage axis weight table RRT_weight is the same as the number of voltage axes in the RRT. In this embodiment, in order to select the target voltage axis, the target voltage axis with the smallest number of corresponding error bits and no reread operation is determined among the voltage axes of the reread voltage axis table RRT mainly based on the pre-constructed voltage axis weight table RRT_weight. In this way, the appropriate voltage axis can be selected more quickly and accurately. Since the target voltage axis has a smaller number of error bits than other voltage axes and no reread operation is performed, the target voltage axis has a higher reread success rate than other voltage axes. The construction process of the voltage axis weight table RRT_weight is described in detail below in conjunction with specific embodiments:

[0047] The process of constructing the voltage axis weight table includes:

[0048] S112: Setting the initialization weight value of the voltage axis.

[0049] The size of the initialization weight value is 2 bytes.

[0050] S113: When decoding is successful under the voltage axis, the original number of error bits and the number of 1-to-0 errors output by the low-density parity-check code decoder are correspondingly obtained.

[0051] S114: Determine the number of zero-to-one errors according to the original number of erroneous bits and the number of one-to-zero errors.

[0052] S115: Determine whether the number of 0-to-1 errors is not less than the number of 1-to-0 errors; if so, proceed to step S116; if not, proceed to step S117.

[0053] S116: Record the highest bit of the initialization weight value of the voltage axis as 1, and use the remaining bits to record the original number of error bits to generate the weight value of the voltage axis.

[0054] S117: Record the highest bit of the initialization weight value of the voltage axis as 0, and use the remaining bits to record the original number of error bits to generate the weight value of the voltage axis.

[0055] Specifically, in SSD, the LDPC decoder returns the current read operation only when the read is successful. and It should be noted that is the original number of error bits, is the number of "1" errors reported by the decoder that are converted to "0", that is, the number of "1" errors that are converted to "0". = + , It is the number of "0" errors converted to "1" reported by the decoder, that is, the number of 0-to-1 errors. Therefore, the number of 0-to-1 errors can be directly calculated by the number of 1-to-0 errors and the original number of error bits.

[0056] At the same time, the original number of error bits It can be used as an evaluation criterion to determine whether the current voltage axis is closer to the ideal voltage axis: The smaller it is, the closer the current voltage axis is to the ideal voltage axis. and The difference can reflect the offset direction of the voltage axis. The details are as follows:

[0057] Figure 2 Schematic diagram of threshold voltage distribution provided by an embodiment of the present invention. Figure 2 As shown, in the two peaks of the threshold voltage distribution, the left side is the "1" peak and the right side is the "0" peak, and RL is the ideal voltage axis of the current threshold voltage distribution. If the voltage axis RL on the left side of the ideal voltage axis is used If you read Greater than , as shown by the two shadows in the figure, RL The shaded area on the right indicates , the left shadow indicates Similarly, the voltage axis to the right of the ideal voltage axis is RL , there will be Greater than situation.

[0058] Therefore, based on the above principle, a voltage axis weight table RRT_weight is maintained for each flash memory page in the SSD master control. The weight of each voltage axis includes the number of error bits after reading each voltage axis and the offset direction relative to the ideal voltage axis. First, set the initialization weight value of the voltage axis, specifically set to 0xFFFF, and the size of the initialization weight value is 2 bytes. When the decoding is successful under the voltage axis, the original number of error bits output by the LDPC decoder is obtained. and 1 is mistaken for 0 error number , and according to the original number of error bits and 1 is mistaken for 0 error number , determine the number of errors that are 0 and 1 . Determine whether the number of 0-to-1 errors is not less than the number of 1-to-0 errors, that is, determine whether .

[0059] If it is confirmed that the number of 0-to-1 errors is not less than the number of 1-to-0 errors, the highest bit of the initialization weight value of the voltage axis is recorded as 1, and the remaining bits are used to record the original number of error bits (i.e., representing the weight amplitude) to generate the weight value of the voltage axis. If it is confirmed that the number of 0-to-1 errors is less than the number of 1-to-0 errors, the highest bit of the initialization weight value of the voltage axis is recorded as 0, and the remaining bits are used to record the original number of error bits (i.e., representing the weight amplitude) to generate the weight value of the voltage axis. In summary, the weight of the i-th voltage axis RRT[i] in the RRT is represented by the two-byte RRT_weight[i], with the highest bit used to record the sign bit (1 or 0) and the remaining bits used to represent the weight amplitude.

[0060] It should also be noted that since the read operation is performed in units of flash memory pages, the dimension of the voltage axis weight table is the same as the number of word lines and flash memory pages. In other words, for single-level cell (SLC), there is only one flash memory page in a word line, so a set of voltage axes only needs to maintain one set of voltage axis weight tables. If it is a triple-level cell (TLC) flash memory, there are three flash memory pages in a word line, then a voltage axis weight table needs to be maintained for each set of voltage axes, the lower page, middle page, and upper page.

[0061] In this embodiment, the original number of error bits and the number of 1-to-0 errors of the current read operation returned by LDPC when the SSD read is successful are used to construct the weights of all voltage axes in the RRT table, and the weight amplitude is used to identify the distance from the ideal voltage axis. The sign bit identifies the direction of the current voltage axis from the ideal voltage axis, so as to quickly and accurately select the entry voltage axis of the reread operation when the reread operation is triggered.

[0062] Based on the above embodiments, in some embodiments, according to the initial syndrome weight and the new syndrome weight, determining a new target voltage axis in each voltage axis of the re-read voltage axis table includes:

[0063] S141: Determine a first difference between a new syndrome weight and an initial syndrome weight.

[0064] S142: Determine a weight value of the target voltage axis according to the voltage axis weight table.

[0065] S143: Determine the index of a new target voltage axis corresponding to the target voltage axis according to the first difference and the weight value of the target voltage axis and according to a pre-constructed rereading index table.

[0066] The reread index table includes the index corresponding to each voltage axis in the reread voltage axis table; the index is determined according to the distance value between the corresponding voltage axis and the remaining voltage axes in the reread voltage axis table.

[0067] S144: Determine a new target voltage axis in each voltage axis of the re-read voltage axis table according to the index.

[0068] In order to determine a new target voltage axis in each voltage axis of the RRT, in this embodiment, a first difference between the new syndrome weight and the initial syndrome weight is specifically determined, and the weight value of the target voltage axis is determined according to the voltage axis weight table RRT_weight. Further, according to the first difference and the weight value of the target voltage axis, the index of the new target voltage axis corresponding to the target voltage axis is determined according to the pre-constructed rereading index table.

[0069] It should be noted that the reread index table contains the index corresponding to each voltage axis in the reread voltage axis table; the index is determined based on the distance value between the corresponding voltage axis and the remaining voltage axes in the reread voltage axis table. Specifically, the reread index table actually combines the NAND threshold voltage distribution characteristics to calculate and select the spare new target voltage axes in the two directions of 0 and 1 for subsequent rereads for different flash memory pages of each voltage axis according to the voltage axis distance definition, thereby optimizing the operation of traversing the RRT in the original reread operation and reducing the reread latency. The following is a detailed description of the construction process of the reread index table:

[0070] Reread the index table construction process, including:

[0071] S145: Determine the distance value between each voltage axis and the remaining voltage axes in the re-read voltage axis table.

[0072] S146: Sort the distance values ​​corresponding to each voltage axis respectively to obtain a distance queue corresponding to each voltage axis.

[0073] S147: Determine the index corresponding to each voltage axis according to each distance queue.

[0074] Specifically, the present invention defines the distance between any two sets of voltage axes for each flash memory page. For example, the voltage axis Vth1 is , the voltage axis Vth2 is m represents the number of reference voltages of the current flash memory page. For example, in common TLC NAND, the threshold voltage has 8 states, and there are 7 read reference voltage axes. The number of voltage axes of the three flash memory pages is 2, 3, and 2 respectively. The distance between the voltage axes Vth1 and Vth2 is defined as:

[0075] ;

[0076] in, For Towards The absolute distance moved, For Towards The movement is to the left or to the right; the sign(x) function is a sign function, that is, when x>0, sign=1, and when x<0, sign(x)=0. Indicates that the i-th voltage axis is moving to the right Is it decreasing or increasing? If i is an odd number, moving to the right means moving towards the "0" peak. decreases; if i is an even number, moving to the right means moving towards the "1" peak, Increase.

[0077] Therefore, use To mark the case where the voltage axis moves from Vth1 to Vth2, When is negative, it can be considered that the number of “1” errors decreases when the number moves from Vth1 to Vth2. is positive, it can be considered that the number of "1" errors increases as it moves from Vth1 to Vth2.

[0078] In summary, using the above distance formula, the distance between each voltage axis in the re-read voltage axis table RRT and the remaining voltage axes in the table can be calculated: If the size of the RRT table is N, then the distance between the i-th group of voltage axes RRT[i] and the remaining voltage axes in the table is as follows:

[0079] ;

[0080] Further, the N-1 distance values ​​corresponding to each voltage axis are sorted respectively to obtain the distance queues corresponding to each voltage axis. Finally, the indexes corresponding to each voltage axis are determined respectively according to each distance queue. In this embodiment, there is no limitation on the specific method of determining the indexes corresponding to each voltage axis respectively according to each distance queue. In this embodiment, by constructing a reread index table and combining the NAND threshold voltage distribution characteristics, the new target voltage axes in the two directions of 0 and 1 for subsequent rereading are calculated and selected for different flash memory pages of each voltage axis according to the voltage axis distance definition, thereby optimizing the operation of traversing the RRT in the original reread operation and reducing the reread delay.

[0081] It is worth noting that in the present invention, the index corresponding to the voltage axis and the index of the voltage axis are two different concepts. Taking voltage axis A and voltage axis B as examples, voltage axis A and voltage axis B have indexes respectively. Voltage axis A can be queried through the index of voltage axis A, and voltage axis B can be queried through the index of voltage axis B. In this case, the corresponding voltage axis is found through the index itself. When the index corresponding to voltage axis A is the index of voltage axis B, it means that there is a corresponding relationship between the index of voltage axis B and voltage axis A, that is, voltage axis B can be queried through the index of voltage axis B corresponding to voltage axis A. In this case, the index corresponding to one voltage axis is used to query another voltage axis.

[0082] On the basis of the above embodiments, in some embodiments, the distance values ​​corresponding to each voltage axis are sorted respectively to obtain the distance queues corresponding to each voltage axis, including:

[0083] S151: among the multiple distance values ​​corresponding to the voltage axis, sort the distance values ​​with negative values ​​in ascending order according to the corresponding absolute values ​​to generate a first distance queue corresponding to the voltage axis.

[0084] S152: among the multiple distance values ​​corresponding to the voltage axis, sort the distance values ​​with positive values ​​in ascending order according to the corresponding absolute values ​​to generate a second distance queue corresponding to the voltage axis.

[0085] In order to obtain the distance queues corresponding to each voltage axis, in this embodiment, among the N-1 distance values ​​corresponding to the voltage axis, the distance values ​​with negative values ​​are sorted in the order of corresponding absolute values ​​from small to large to generate the first distance queue corresponding to the voltage axis; among the N-1 distance values ​​corresponding to the voltage axis, the distance values ​​with positive values ​​are sorted in the order of corresponding absolute values ​​from small to large to generate the second distance queue corresponding to the voltage axis. Since the distance values ​​in the first distance queue and the second distance queue are negative and positive values, respectively, representing different moving directions of the voltage axis, the index of the new target voltage axis can be determined more accurately according to the first distance queue and the second distance queue.

[0086] Based on the above embodiments, in some embodiments, the index corresponding to each voltage axis is determined according to each distance queue, including:

[0087] S153: Determine the first two distance values ​​in the first distance queue to obtain a first distance value and a second distance value.

[0088] The absolute value of the first distance value is smaller than the absolute value of the second distance value.

[0089] S154: Determine the first two distance values ​​in the second distance queue to obtain a third distance value and a fourth distance value.

[0090] The absolute value of the third distance value is smaller than the absolute value of the fourth distance value.

[0091] S155: respectively determine a first candidate voltage axis corresponding to the first distance value, a second candidate voltage axis corresponding to the second distance value, a third candidate voltage axis corresponding to the third distance value, and a fourth candidate voltage axis corresponding to the fourth distance value.

[0092] S156: respectively determining the index of the first to-be-selected voltage axis, the index of the second to-be-selected voltage axis, the index of the third to-be-selected voltage axis, and the index of the fourth to-be-selected voltage axis as the indexes corresponding to the voltage axes.

[0093] After obtaining the first distance queue and the second distance queue of the voltage axis, in order to determine the index corresponding to the voltage axis, the first two distance values ​​in the first distance queue are specifically determined to obtain the first distance value and the second distance value, and the absolute value of the first distance value is less than the absolute value of the second distance value. It can be understood that the first distance value and the second distance value are the two distance values ​​with the smallest absolute values ​​in the first distance queue. The first two distance values ​​in the second distance queue are determined to obtain the third distance value and the fourth distance value, and the absolute value of the third distance value is less than the absolute value of the fourth distance value. It can be understood that the third distance value and the fourth distance value are the two distance values ​​with the smallest absolute values ​​in the second distance queue.

[0094] Further, the first to-be-selected voltage axis corresponding to the first distance value, the second to-be-selected voltage axis corresponding to the second distance value, the third to-be-selected voltage axis corresponding to the third distance value, and the fourth to-be-selected voltage axis corresponding to the fourth distance value are determined respectively. For example, the first distance value of the voltage axis A is the distance value between the voltage axis A and the voltage axis 1, the second distance value of the voltage axis A is the distance value between the voltage axis A and the voltage axis 2, the third distance value of the voltage axis A is the distance value between the voltage axis A and the voltage axis 3, and the fourth distance value of the voltage axis A is the distance value between the voltage axis A and the voltage axis 4. Then, the first to-be-selected voltage axis corresponding to the first distance value of the voltage axis A, the second to-be-selected voltage axis corresponding to the second distance value, the third to-be-selected voltage axis corresponding to the third distance value, and the fourth to-be-selected voltage axis corresponding to the fourth distance value are voltage axis 1, voltage axis 2, voltage axis 3, and voltage axis 4, respectively.

[0095] Finally, the index of the first candidate voltage axis is , the index of the second candidate voltage axis , the index of the third candidate voltage axis and the fourth candidate voltage axis The index of the voltage axis is determined as the index corresponding to the voltage axis Taking the above content as an example, the index of voltage axis 1, the index of voltage axis 2, the index of voltage axis 3 and the index of voltage axis 4 are determined as the index corresponding to voltage axis A. The index corresponding to each voltage axis is Together they form the rereading index table.

[0096] In this way, the index corresponding to each voltage axis in the reread index table is determined. Two additional sets of indexes are recorded for each voltage axis in the reread index table, and the offline calculation does not increase the complexity and delay in actual use, thereby improving the search efficiency of the new target voltage axis.

[0097] It should also be noted that since the read operation is performed in units of flash memory pages, the dimension of the reread index table is the same as the number of word lines and flash memory pages. In other words, for SLC, there is only one flash memory page in a word line, so a set of voltage axes only needs to maintain one set of reread index tables. If it is TLC flash memory, there are three flash memory pages in a word line, so a reread index table needs to be maintained for the Lower Page, Middle Page and Upper Page of each set of voltage axes.

[0098] Based on the above embodiments, in some embodiments, determining the index of a new target voltage axis corresponding to the target voltage axis according to the first difference and the weight value of the target voltage axis according to a pre-constructed rereading index table includes:

[0099] S161: Determine a second difference between an initial syndrome weight and a corresponding previous syndrome weight.

[0100] S162: Determine whether the first difference and the second difference are both greater than 0; if not, proceed to step S163; if yes, proceed to step S164.

[0101] S163: Determine an index of a new target voltage axis in the reread index table according to the voltage axis usage status of the reread voltage axis table and the weight value of the target voltage axis.

[0102] S164: Re-determine, according to the voltage axis weight table, a new target voltage axis with the smallest number of corresponding error bits and without performing a reread operation among the voltage axes in the reread voltage axis table, and proceed to step S12.

[0103] In order to determine the index of the new target voltage axis, when the kth reread is performed and the decoding fails even when the target voltage axis is RRk, the new syndrome weight corresponding to the target voltage axis RRk is , the corresponding initial syndrome weight is , then the first difference is ; Initial checksum weight The corresponding weight of the previous syndrome is , then the second difference between the initial syndrome weight and the corresponding previous syndrome weight is It should be noted that, in this embodiment, there is no restriction on the size of k, for example, k can be set to 3.

[0104] Further determine whether the first difference and the second difference are both greater than 0. If it is confirmed that the first difference and the second difference are both greater than 0, it means that the weights of two consecutive check sub-values ​​have increased, and the corresponding RBER has also increased, indicating that the current voltage axis movement direction is incorrect. In the k+1th reread, it is necessary to re-determine the new target voltage axis with the smallest number of corresponding error bits and no reread operation in each voltage axis of the reread voltage axis table according to the voltage axis weight table, and promptly correct the wrong direction of the reread attempt, and try the reread decoding operation again to reduce the number of rereads and delays. If it is confirmed that the first difference and / or the second difference is not greater than 0, the index of the new target voltage axis is determined in the reread index table according to the voltage axis usage of the reread voltage axis table and the weight value of the target voltage axis. The specific explanation is as follows:

[0105] Based on the above embodiments, in some embodiments, according to the voltage axis usage of the reread voltage axis table and the weight value of the target voltage axis, determining the index of the new target voltage axis in the reread index table includes:

[0106] S165: When the highest bit of the weight value of the target voltage axis is 0, determine whether the first candidate voltage axis and the second candidate voltage axis corresponding to the target voltage axis have been used in the previous rereading.

[0107] S166: If it is confirmed that the first candidate voltage axis and the second candidate voltage axis have not been used in the previous rereading, the index of the first candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis.

[0108] S167: If it is confirmed that the first candidate voltage axis has been used in the previous rereading and the second candidate voltage axis has not been used in the previous rereading, the index of the second candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis.

[0109] S168: When the highest bit of the weight value of the target voltage axis is 1, determine whether the third candidate voltage axis and the fourth candidate voltage axis corresponding to the target voltage axis have been used in the previous rereading.

[0110] S169: If it is confirmed that the third candidate voltage axis and the fourth candidate voltage axis have not been used in the previous rereading, the index of the third candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis.

[0111] S170: If it is confirmed that the third candidate voltage axis has been used in the previous rereading and the fourth candidate voltage axis has not been used in the previous rereading, the index of the fourth candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis.

[0112] It can be understood that the index corresponding to the target voltage axis RRk is , are the indices of the first candidate voltage axis corresponding to the target voltage axis RRk , the index of the second candidate voltage axis , the index of the third candidate voltage axis and the index of the fourth candidate voltage axis Therefore, when the highest bit of the weight value of the target voltage axis RRk is 0, it means that the current voltage axis needs to shift toward the "0" peak to approach the ideal voltage axis, and a new target voltage axis needs to be selected from the first candidate voltage axis and the second candidate voltage axis.

[0113] Specifically, it is determined whether the first candidate voltage axis and the second candidate voltage axis corresponding to the target voltage axis have been used in the previous rereading. If it is confirmed that the first candidate voltage axis and the second candidate voltage axis have not been used in the previous rereading, since the first candidate voltage axis is closer to the target voltage axis, the index of the first candidate voltage axis corresponding to the target voltage axis is changed to The index of the new target voltage axis is determined. If it is confirmed that the first candidate voltage axis has been used in the previous rereading, and the second candidate voltage axis has not been used in the previous rereading, the index of the second candidate voltage axis corresponding to the target voltage axis is changed to The index of the new target voltage axis is determined, that is, the second candidate voltage axis is used as the voltage axis for performing the reread operation in the next step. This operation avoids switching back and forth between the two adjacent voltage axes that are closest to each other.

[0114] When the highest bit of the weight value of the target voltage axis RRk is 1, it means that the current voltage axis needs to shift toward the "1" peak to approach the ideal voltage axis, and accordingly a new target voltage axis needs to be selected from the third and fourth candidate voltage axes.

[0115] Specifically, it is determined whether the third and fourth candidate voltage axes corresponding to the target voltage axis have been used in the previous rereading. If it is confirmed that the third and fourth candidate voltage axes have not been used in the previous rereading, since the third candidate voltage axis is closer to the target voltage axis, the index of the third candidate voltage axis corresponding to the target voltage axis is changed to If it is confirmed that the third candidate voltage axis has been used in the previous rereading and the fourth candidate voltage axis has not been used in the previous rereading, the fourth candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis. The index of is determined as the index of the new target voltage axis, that is, the fourth candidate voltage axis is used as the voltage axis to be reread in the next step. This operation avoids switching back and forth between the two adjacent voltage axes that are closest to each other.

[0116] In summary, in this embodiment, by querying the weight sign bit of the current target voltage axis, the next group of voltage axis indexes for performing the reread operation are determined in the reread index table according to the sign bit, and the corresponding voltage axis is selected to perform the reread operation in the next step, thereby achieving fine-tuning correction of the reread direction, reducing the reread delay, and improving the reread efficiency.

[0117] Based on the above embodiment, in some embodiments, if it is confirmed that the first candidate voltage axis and the second candidate voltage axis have been used in the previous rereading, or it is confirmed that the third candidate voltage axis and the fourth candidate voltage axis have been used in the previous rereading, the method further includes:

[0118] S171: Re-determine, according to the voltage axis weight table, a new target voltage axis with the smallest number of corresponding error bits and without performing a reread operation among the voltage axes in the reread voltage axis table, and proceed to step S12.

[0119] In a specific implementation, if the first selected voltage axis and the second selected voltage axis have both been used in the previous reread, or the third selected voltage axis and the fourth selected voltage axis have both been used in the previous reread, it means that the first selected voltage axis and the second selected voltage axis, as well as the third selected voltage axis and the fourth selected voltage axis are no longer suitable as new target voltage axes to participate in the next reread operation. At this time, it is necessary to re-determine the new target voltage axis with the smallest number of corresponding error bits and no reread operation among the voltage axes in the reread voltage axis table according to the voltage axis weight table, so as to correct the reread voltage axis entry in time and try the reread decoding operation again to reduce the number of rereads and delays.

[0120] Based on the above embodiment, in some embodiments, if the decoding is confirmed to be successful, the process further includes:

[0121] S172: Obtain the new original number of error bits and the new number of 1-to-0 errors returned by the low-density parity-check code decoder.

[0122] S173: Determine a new number of 0-to-1 errors according to the new number of original erroneous bits and the new number of 1-to-0 errors.

[0123] S174: When the new original number of error bits is not less than the original number of error bits corresponding to the target voltage axis, the new original number of error bits is used to update the original number of error bits corresponding to the target voltage axis in the voltage axis weight table.

[0124] S175: When the new number of 0-to-1 errors is not less than the new number of 1-to-0 errors, the highest bit of the weight value of the target voltage axis in the voltage axis weight table is recorded as 1.

[0125] S176: When the new number of 0-to-1 errors is less than the new number of 1-to-0 errors, the highest bit of the weight value of the target voltage axis in the voltage axis weight table is recorded as 0.

[0126] In a specific implementation, when the decoding is successful using the target voltage axis, in order to ensure the accuracy of the voltage axis weight table and to facilitate the next re-reading of the voltage axis selection, the voltage axis weight table needs to be updated.

[0127] Specifically, obtain the new original number of error bits and the new number of 1-to-0 errors returned by the LDPC decoder. Determine the new number of 0-to-1 errors based on the new original number of error bits and the new number of 1-to-0 errors. When the new original number of error bits is not less than the original number of error bits corresponding to the target voltage axis, use the new original number of error bits to update the original number of error bits corresponding to the target voltage axis in the voltage axis weight table, that is, update the weight amplitude corresponding to the target voltage axis in the voltage axis weight table to the new original number of error bits, otherwise retain the original weight amplitude corresponding to the target voltage axis in the voltage axis weight table.

[0128] When the new 0-to-1 error number is not less than the new 1-to-0 error number, the highest bit of the weight value of the target voltage axis in the voltage axis weight table is recorded as 1. When the new 0-to-1 error number is less than the new 1-to-0 error number, the highest bit of the weight value of the target voltage axis in the voltage axis weight table is recorded as 0, thereby updating the weight sign bit of the target voltage axis, ensuring the accuracy of the voltage axis weight table, and facilitating the selection of the voltage axis when it is reread next time.

[0129] Based on the above embodiment, in some embodiments, if the decoding fails, the method further includes:

[0130] S177: Determine whether each voltage axis of the reread voltage axis table has been reread; if so, end the reread process and execute the read recovery process; if not, enter step S13.

[0131] In a specific implementation, if it is confirmed that the decoding fails, it can be further determined whether each voltage axis in the reread voltage axis table has been reread. If it is confirmed that each voltage axis in the reread voltage axis table has been reread, it is considered that all voltage axes do not support normal reread decoding, and the reread process is terminated directly, and the read recovery process is executed. If it is confirmed that there is a voltage axis in the reread voltage axis table that has not been reread, then step S13 is entered to execute a new target voltage axis selection and reread process. This avoids meaningless voltage axis selection and rereading that wastes system resources.

[0132] In addition, if data cannot be successfully read after traversing all voltage axes in the RRT, and it is determined that the error is caused by physical layer factors (such as read interference accumulation or temperature drift), physical layer data recovery operations need to be performed. For read interference problems, data can be migrated to new storage blocks and the original blocks can be erased to reset the threshold voltage distribution; for threshold voltage shifts caused by temperature, the voltage parameter deviations caused by environmental changes can be compensated by actively adjusting the NAND chip temperature (such as heating to a stable operating condition) and combining a cross-temperature calibration algorithm to restore readability. These two types of methods work together through hardware intervention and algorithms to mitigate irreversible storage cell characteristic degradation at the physical level.

[0133] Figure 3 The overall process diagram of flash memory rereading provided by the embodiment of the present invention is shown in FIG. Figure 3 As shown, the present invention utilizes the return value of the LDPC decoder and combines the characteristics of NAND to maintain two additional tables for RRT in the master control: the voltage axis weight table is used to select the entry voltage axis for the reread operation, and the reread index table is used to select the index of the voltage axis for the next operation, thereby optimizing the operation of traversing the RRT in the original reread operation and optimizing the reread delay. In the two additionally maintained tables, the reread index table records two additional sets of indexes for each voltage axis, and the offline calculation does not increase the complexity and delay in actual use; the size of the voltage axis weight table is the same as that of the RRT, and only comparison and update are performed after each reading. Compared with the traditional solution, this solution consumes only a small amount of memory and computational complexity, and can reduce the delay of the reread operation.

[0134] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0135] Figure 4 A schematic diagram of a flash memory re-reading device provided by an embodiment of the present invention. The device is applied to a solid state hard disk; Figure 4 As shown, the device comprises:

[0136] The first acquisition module 10 is used to acquire the initial syndrome weight in the current low-density parity-check code decoder when decoding fails under the default voltage axis.

[0137] The first determination module 11 is used to determine a target voltage axis that meets a preset requirement among the voltage axes in the re-read voltage axis table.

[0138] The reread decoding and judging module 12 is used to perform a reread decoding operation based on the target voltage axis and judge whether the decoding is successful; if so, the rereading process is terminated. If not, the second acquisition module 13 is triggered.

[0139] The second acquisition module 13 is used to acquire a new syndrome weight in the current low-density parity-check code decoder.

[0140] The second determination module 14 is used to determine a new target voltage axis in each voltage axis of the reread voltage axis table according to the initial syndrome weight and the new syndrome weight, and use the new syndrome weight as the initial syndrome weight to trigger the reread decoding and judgment module 12.

[0141] In some embodiments, the first determining module 11 includes:

[0142] A first determination submodule is used to determine, according to a pre-constructed voltage axis weight table, a target voltage axis having a minimum number of corresponding error bits and on which no reread operation is performed, among the voltage axes in the reread voltage axis table;

[0143] The voltage axis weight table includes the number of error bits of each voltage axis after reading, and the offset direction relative to the ideal voltage axis.

[0144] In some embodiments, the construction process of the voltage axis weight table includes: setting the initialization weight value of the voltage axis; wherein the size of the initialization weight value is 2 bytes; when decoding is successful under the voltage axis, correspondingly obtaining the original number of error bits and the number of 1-to-0 errors output by the low-density parity-check code decoder; determining the number of 0-to-1 errors based on the original number of error bits and the number of 1-to-0 errors; judging whether the number of 0-to-1 errors is not less than the number of 1-to-0 errors; if so, recording the highest bit of the initialization weight value of the voltage axis as 1, and the remaining bits are used to record the original number of error bits to generate the weight value of the voltage axis; if not, recording the highest bit of the initialization weight value of the voltage axis as 0, and the remaining bits are used to record the original number of error bits to generate the weight value of the voltage axis.

[0145] In some embodiments, the second determining module 14 includes:

[0146] A first determination submodule, configured to determine a first difference between a new syndrome weight and an initial syndrome weight;

[0147] A second determination submodule is used to determine a weight value of a target voltage axis according to a voltage axis weight table;

[0148] A third determination submodule is used to determine the index of a new target voltage axis corresponding to the target voltage axis according to the first difference and the weight value of the target voltage axis and according to a pre-constructed rereading index table; wherein the rereading index table contains the index corresponding to each voltage axis in the rereading voltage axis table; the index is determined according to the distance value between the corresponding voltage axis and the remaining voltage axes in the rereading voltage axis table;

[0149] The fourth determination submodule is used to determine a new target voltage axis in each voltage axis of the re-read voltage axis table according to the index.

[0150] In some embodiments, the construction process of the reread index table includes: determining the distance value between each voltage axis and the remaining voltage axes in the reread voltage axis table; sorting the distance values ​​corresponding to each voltage axis respectively to obtain the distance queue corresponding to each voltage axis; and determining the index corresponding to each voltage axis according to each distance queue.

[0151] In some embodiments, the distance values ​​corresponding to each voltage axis are sorted respectively to obtain a distance queue corresponding to each voltage axis, including: among the multiple distance values ​​corresponding to the voltage axis, the distance values ​​with negative values ​​are sorted in order from small to large according to the corresponding absolute values ​​to generate a first distance queue corresponding to the voltage axis; among the multiple distance values ​​corresponding to the voltage axis, the distance values ​​with positive values ​​are sorted in order from small to large according to the corresponding absolute values ​​to generate a second distance queue corresponding to the voltage axis.

[0152] In some embodiments, the index corresponding to each voltage axis is determined respectively according to each distance queue, including: determining the first two distance values ​​in the first distance queue to obtain a first distance value and a second distance value; wherein the absolute value of the first distance value is smaller than the absolute value of the second distance value; determining the first two distance values ​​in the second distance queue to obtain a third distance value and a fourth distance value; wherein the absolute value of the third distance value is smaller than the absolute value of the fourth distance value; respectively determining the first selected voltage axis corresponding to the first distance value, the second selected voltage axis corresponding to the second distance value, the third selected voltage axis corresponding to the third distance value, and the fourth selected voltage axis corresponding to the fourth distance value; respectively determining the index of the first selected voltage axis, the index of the second selected voltage axis, the index of the third selected voltage axis, and the index of the fourth selected voltage axis as the indexes corresponding to the voltage axes.

[0153] In some embodiments, the third determining submodule includes:

[0154] a fifth determination submodule, configured to determine a second difference between the initial syndrome weight and the corresponding previous syndrome weight;

[0155] The first judgment submodule is used to judge whether the first difference and the second difference are both greater than 0; if not, the sixth determination submodule is triggered; if so, the seventh determination submodule is triggered;

[0156] A sixth determination submodule, configured to determine an index of a new target voltage axis in a reread index table according to a voltage axis usage condition of the reread voltage axis table and a weight value of the target voltage axis;

[0157] The seventh determination submodule is used to re-determine a new target voltage axis with the smallest number of corresponding error bits and no reread operation among the voltage axes in the reread voltage axis table according to the voltage axis weight table, and trigger the reread decoding and judgment module.

[0158] In some embodiments, the sixth determining submodule includes:

[0159] The second judgment submodule is used to judge whether the first to-be-selected voltage axis and the second to-be-selected voltage axis corresponding to the target voltage axis have been used in the previous rereading when the highest bit of the weight value of the target voltage axis is 0; if it is confirmed that the first to-be-selected voltage axis and the second to-be-selected voltage axis have not been used in the previous rereading, the index of the first to-be-selected voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis; if it is confirmed that the first to-be-selected voltage axis has been used in the previous rereading and the second to-be-selected voltage axis has not been used in the previous rereading, the index of the second to-be-selected voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis;

[0160] The third judgment submodule is used to judge whether the third selected voltage axis and the fourth selected voltage axis corresponding to the target voltage axis have been used in the previous rereading when the highest bit of the weight value of the target voltage axis is 1; if it is confirmed that the third selected voltage axis and the fourth selected voltage axis have not been used in the previous rereading, the index of the third selected voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis; if it is confirmed that the third selected voltage axis has been used in the previous rereading and the fourth selected voltage axis has not been used in the previous rereading, the index of the fourth selected voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis.

[0161] In some embodiments, it also includes:

[0162] The selection module is used to re-determine a new target voltage axis with the smallest number of corresponding error bits and no reread operation among the voltage axes in the reread voltage axis table according to the voltage axis weight table, and trigger the reread decoding and judgment module.

[0163] In some embodiments, it also includes:

[0164] The second acquisition submodule is used to obtain a new original number of error bits and a new number of 1-to-0 errors returned by the low-density parity-check code decoder;

[0165] A seventh determination submodule, configured to determine a new number of 0-error-to-1 errors according to a new original number of erroneous bits and a new number of 1-error-to-0 errors;

[0166] A first updating submodule, configured to update the original number of error bits corresponding to the target voltage axis in the voltage axis weight table using the new original number of error bits when the new original number of error bits is not less than the original number of error bits corresponding to the target voltage axis;

[0167] The second updating submodule is used for recording the highest bit of the weight value of the target voltage axis in the voltage axis weight table as 1 when the new number of 0-to-1 errors is not less than the new number of 1-to-0 errors;

[0168] The third updating submodule is used to record the highest bit of the weight value of the target voltage axis in the voltage axis weight table as 0 when the new number of 0-to-1 errors is less than the new number of 1-to-0 errors.

[0169] In some embodiments, it also includes:

[0170] The fourth judgment submodule is used to judge whether each voltage axis of the reread voltage axis table has been reread; if so, the rereading process is terminated and the read recovery process is executed; if not, the second acquisition module 13 is triggered.

[0171] The description of the features in the embodiment corresponding to the flash memory rereading device can refer to the relevant description of the embodiment corresponding to the flash memory rereading method, which will not be repeated here.

[0172] An embodiment of the present invention further provides an electronic device, comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above flash memory rereading method embodiments.

[0173] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned flash memory rereading method embodiments when running.

[0174] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0175] An embodiment of the present invention further provides a computer program product, the computer program product comprising a computer program, and when the computer program is executed by a processor, the steps in any one of the above flash memory rereading method embodiments are implemented.

[0176] An embodiment of the present invention further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned flash memory rereading method embodiments are implemented.

[0177] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0178] The above is a detailed introduction to a flash memory rereading method, device, medium and product provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A flash memory rereading method, characterized in that: Applied to a solid state hard disk; the method comprises: When decoding fails under the default voltage axis, obtaining an initial syndrome weight in the current low-density parity-check code decoder; Determining a target voltage axis that meets preset requirements among the voltage axes in the re-read voltage axis table; Performing a reread decoding operation based on the target voltage axis and determining whether the decoding is successful; If not, obtaining a new syndrome weight in the current low-density parity-check code decoder; Determine a new target voltage axis in each voltage axis of the reread voltage axis table according to the initial syndrome weight and the new syndrome weight, use the new syndrome weight as the initial syndrome weight, and return to the step of performing a reread decoding operation based on the target voltage axis; If yes, the re-reading process ends.

2. The flash memory rereading method according to claim 1, characterized in that: Determine a target voltage axis that meets preset requirements in each voltage axis of the re-read voltage axis table, including: According to a pre-constructed voltage axis weight table, determining the target voltage axis having the smallest corresponding error bit number and not performing a reread operation among the voltage axes in the reread voltage axis table; The voltage axis weight table includes the number of error bits of each voltage axis after reading, and the offset direction relative to the ideal voltage axis.

3. The flash memory rereading method according to claim 2, characterized in that: The process of constructing the voltage axis weight table includes: Setting an initialization weight value of the voltage axis; wherein the size of the initialization weight value is 2 bytes; When decoding is successful under the voltage axis, the original number of error bits and the number of 1-to-0 errors output by the low-density parity check code decoder are obtained accordingly; Determine the number of 0-error-to-1 errors according to the original number of error bits and the number of 1-error-to-0 errors; Determine whether the number of 0-to-1 errors is not less than the number of 1-to-0 errors; If yes, the highest bit of the initialization weight value of the voltage axis is recorded as 1, and the remaining bits are used to record the original number of error bits to generate the weight value of the voltage axis; If not, the highest bit of the initialized weight value of the voltage axis is recorded as 0, and the remaining bits are used to record the original number of error bits to generate the weight value of the voltage axis.

4. The flash memory rereading method according to claim 3, characterized in that: Determining a new target voltage axis in each voltage axis of the re-read voltage axis table according to the initial syndrome weight and the new syndrome weight includes: determining a first difference between the new syndrome weight and the initial syndrome weight; Determining a weight value of the target voltage axis according to the voltage axis weight table; According to the first difference and the weight value of the target voltage axis, the index of the new target voltage axis corresponding to the target voltage axis is determined according to a pre-constructed rereading index table; wherein the rereading index table contains the index corresponding to each voltage axis in the rereading voltage axis table; the index is determined according to the distance value between the corresponding voltage axis and the remaining voltage axes in the rereading voltage axis table; The new target voltage axis is determined in each voltage axis of the re-read voltage axis table according to the index.

5. The flash memory rereading method according to claim 4, characterized in that: The process of constructing the reread index table includes: Determine the distance value between each voltage axis and the remaining voltage axes in the re-read voltage axis table; Sort the distance values ​​corresponding to each voltage axis respectively to obtain the distance queue corresponding to each voltage axis; The index corresponding to each voltage axis is determined respectively according to each of the distance queues.

6. The flash memory rereading method according to claim 5, characterized in that: The distance values ​​corresponding to each voltage axis are sorted respectively to obtain the distance queue corresponding to each voltage axis, including: Among the multiple distance values ​​corresponding to the voltage axis, the distance values ​​with negative values ​​are sorted in ascending order according to the corresponding absolute values, so as to generate a first distance queue corresponding to the voltage axis; Among the multiple distance values ​​corresponding to the voltage axis, the distance values ​​with positive values ​​are sorted in ascending order according to the corresponding absolute values ​​to generate a second distance queue corresponding to the voltage axis.

7. The flash memory rereading method according to claim 6, characterized in that: Determining the index corresponding to each voltage axis according to each of the distance queues respectively includes: Determine the first two distance values ​​in the first distance queue to obtain a first distance value and a second distance value; wherein the absolute value of the first distance value is smaller than the absolute value of the second distance value; Determine the first two distance values ​​in the second distance queue to obtain a third distance value and a fourth distance value; wherein the absolute value of the third distance value is less than the absolute value of the fourth distance value; respectively determining a first to-be-selected voltage axis corresponding to the first distance value, a second to-be-selected voltage axis corresponding to the second distance value, a third to-be-selected voltage axis corresponding to the third distance value, and a fourth to-be-selected voltage axis corresponding to the fourth distance value; The index of the first to-be-selected voltage axis, the index of the second to-be-selected voltage axis, the index of the third to-be-selected voltage axis and the index of the fourth to-be-selected voltage axis are respectively determined as the indexes corresponding to the voltage axes.

8. The flash memory rereading method according to claim 7, characterized in that: Determining the index of the new target voltage axis corresponding to the target voltage axis according to the first difference and the weight value of the target voltage axis and according to a pre-constructed rereading index table includes: Determining a second difference between the initial syndrome weight and a corresponding previous syndrome weight; Determine whether the first difference and the second difference are both greater than 0; If not, determining the index of the new target voltage axis in the reread index table according to the voltage axis usage of the reread voltage axis table and the weight value of the target voltage axis; If so, then the new target voltage axis with the smallest number of corresponding error bits and no reread operation is performed is determined again according to the voltage axis weight table, and the step of performing a reread decoding operation based on the target voltage axis is entered.

9. The flash memory rereading method according to claim 8, characterized in that: Determining the index of the new target voltage axis in the reread index table according to the voltage axis usage of the reread voltage axis table and the weight value of the target voltage axis includes: When the highest bit of the weight value of the target voltage axis is 0, determining whether the first candidate voltage axis and the second candidate voltage axis corresponding to the target voltage axis have been used in a previous rereading; If it is confirmed that the first candidate voltage axis and the second candidate voltage axis have not been used in the previous rereading, the index of the first candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis; If it is confirmed that the first candidate voltage axis has been used in the previous rereading, and the second candidate voltage axis has not been used in the previous rereading, the index of the second candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis; When the highest bit of the weight value of the target voltage axis is 1, determining whether the third candidate voltage axis and the fourth candidate voltage axis corresponding to the target voltage axis have been used in the previous rereading; If it is confirmed that the third candidate voltage axis and the fourth candidate voltage axis have not been used in the previous rereading, the index of the third candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis; If it is confirmed that the third candidate voltage axis has been used in the previous rereading and the fourth candidate voltage axis has not been used in the previous rereading, the index of the fourth candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis.

10. The flash memory rereading method according to claim 9, characterized in that: If it is confirmed that the first candidate voltage axis and the second candidate voltage axis have been used in the previous rereading, or it is confirmed that the third candidate voltage axis and the fourth candidate voltage axis have been used in the previous rereading, the method further includes: According to the voltage axis weight table, a new target voltage axis with the smallest number of corresponding error bits and without performing a reread operation is determined among the voltage axes in the reread voltage axis table, and the step of performing a reread decoding operation based on the target voltage axis is entered.

11. The flash memory rereading method according to any one of claims 3 to 10, characterized in that: If the decoding is confirmed to be successful, it also includes: Obtain the new original error bit number and the new 1-to-0 error number returned by the low-density parity check code decoder; Determine a new number of 0-error-to-1 errors according to the new original number of erroneous bits and the new number of 1-error-to-0 errors; When the new original number of error bits is not less than the original number of error bits corresponding to the target voltage axis, using the new original number of error bits to update the original number of error bits corresponding to the target voltage axis in the voltage axis weight table; When the new number of 0-to-1 errors is not less than the new number of 1-to-0 errors, recording the highest bit of the weight value of the target voltage axis in the voltage axis weight table as 1; When the new number of 0-to-1 errors is less than the new number of 1-to-0 errors, the highest bit of the weight value of the target voltage axis in the voltage axis weight table is recorded as 0.

12. The flash memory rereading method according to claim 11, characterized in that: If the decoding fails, it also includes: Determining whether each voltage axis of the re-read voltage axis table has been re-read; If yes, then the reread process ends and the read recovery process is executed; If not, the process proceeds to the step of obtaining a new syndrome weight in the current low-density parity-check code decoder.

13. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the flash memory rereading method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the flash memory rereading method according to any one of claims 1 to 12.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the flash memory rereading method according to any one of claims 1 to 12 are implemented.

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