Solid memory bad block management processing method based on eNVM (enhanced non-volatile memory) on SOC (system on chip)

Abstract

The invention relates to the technical field of storage, in particular to a solid memory bad block management processing method based on an eNVM on an SOC. The invention discloses a solid memory bad block management processing method based on an eNVM on an SOC. The method comprises the steps that S1, an eNVM bad block cache region is established; s2, performing initialization configuration; s3, marking factory bad blocks of the NAND flash; s4, the eNVM writes in set page number management; s5, the eNVM writes a time sequence; s6, the eNVM reads out set page number management; and S7, the eNVM reads the time sequence. According to the processing method for managing the bad blocks of the solid memory, the bad block management data is stored in the nonvolatile memory (eNVM) on the SOC chip based on an ARM + FPGA architecture of the SOC chip, so that the storage reliability of the NAND flash is improved, and the cache resources of the NAND flash and other hardware cost are correspondingly saved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a method for managing solid storage bad blocks based on eNVM on a SOC chip. Background Art

[0002] As the amount of data that needs to be stored in onboard storage systems continues to increase, there are higher requirements for storage speed and reliability. Today, NAND flash-based memory is mainly used as a large-capacity data storage device. Due to its process and inherent structure, some inherent bad blocks cannot be used when leaving the factory, and bad blocks may randomly appear during use, making it impossible to write or read data. In order to improve the reliability of data storage, it is necessary to manage the factory bad blocks and dynamically generated bad blocks when using NAND flash chips.

[0003] There are currently two main ways to store bad block management data such as the bad block table. One is to reserve several blocks in NAND flash. The advantage of this method is that it does not require additional cache chips, which can save hardware resources, but it will waste NAND flash storage resources, and the characteristics of NAND flash itself may cause errors in cached bad block data. The other is to configure a non-volatile storage chip to store bad block management data. This method can improve the reliability of bad block data cache, but it will increase hardware space and cost.

[0004] Embedded Non-Volatile Memory (eNVM) refers to memory that can retain all data even when the power is off. Unlike traditional volatile memory such as RAM, eNVM provides persistent storage and is ideal for applications that require long-term data retention.

[0005] The NAND FLASH bad block management system and method disclosed in patent number CN104765695A can be applied to bad block management in hardware systems configured with non-volatile memory EEPROM, but it will not be applicable to some hardware platforms that are not configured with non-volatile memory, and this method increases the cost and space of the hardware.

[0006] Patent No. CN105702300A discloses an FPGA-based NAND Flash fault-tolerant system. Although the proposed FLASH bad block management subsystem is composed of an FPGA and a Flash array, the flash is divided into three logical areas, namely, a good block area, a bad block area, and an information storage area, and an address mapping table is established and stored in the information storage area. The FPGA is controlled as a core controller. Although the system does not require additional hardware space and cost to implement bad block management, the address mapping table for bad block management is stored in the flash, which will consume part of the flash storage resources on the one hand, and on the other hand, the flash area storing the mapping table may also become a bad block, resulting in errors in the address mapping table for bad block management. Summary of the invention

[0007] In order to solve the above problems, the present invention provides a method for managing fixed storage bad blocks based on an embedded non-volatile memory on a system-on-chip. A fixed area is set in the eNVM on the system-on-chip (SOC) as a bad block management data storage area, and the main control FPGA manages the NAND flash online. The specific technical solution is as follows:

[0008] A method for processing bad blocks of solid memory based on eNVM on a SOC chip, the method comprising the following steps:

[0009] S1. Establish eNVM bad block cache area

[0010] S2. Initialization configuration

[0011] S3, NAND flash factory bad block mark

[0012] After the first power-on, the NAND flash management module reads and judges the first byte of the redundant area of ​​the first page of each block of the NAND flash, and marks it. After all blocks are marked, a completion mark is given, and a valid enable signal for writing eNVM is given;

[0013] S4, eNVM write setting page number management

[0014] After receiving the valid enable signal for writing eNVM obtained in step S3, the eNVM management module enters the state of writing eNVM from the standby state, determines that the interface FIFO data is readable and the eNVM read-write timing module is in an idle state in the state of writing eNVM, gives a page write enable signal for writing each page of eNVM, and gives the address of the page to be written;

[0015] S5, eNVM write timing

[0016] After receiving the page write enable signal and the address of the page to be written obtained in step S4, the eNVM read / write timing module starts to jump to perform a write operation according to the eNVM write protocol through the AHB interface;

[0017] The eNVM management module waits to receive a write completion signal from the eNVM read / write timing module. After receiving the signal, it determines whether the set write page number condition is met. If not, the address of the page to be written is incremented, and the above steps S4 and S5 are repeated to start the write operation of the next page until the set page number condition is met, and the writing of the bad block management data is terminated;

[0018] S6, eNVM readout setting page number management

[0019] After each subsequent power-on, the processor will initialize and configure the registers through the APB interface. After the initialization configuration is completed, the FPGA can read and write eNVM through the AHB interface;

[0020] After the power-on eNVM management module receives the valid enable signal for reading eNVM, the state machine enters the state of reading eNVM from the standby state, and gives a page read enable signal for reading each page of eNVM when the interface FIFO is writable and the eNVM read-write timing module is idle, and gives the address of the page to be read;

[0021] S7, eNVM read timing

[0022] After receiving the page read enable signal and the address of the page to be read, the eNVM read / write timing module starts to jump. First, the state machine enters the read status register state from the standby state, and reads and writes the eNVM through the AHB interface, performing the read operation according to the eNVM protocol;

[0023] The eNVM management module waits to receive the read completion signal from the eNVM read / write timing module. After receiving this signal, it determines whether the set read page number condition is met. If not, the address of the page to be read is incremented, and the above steps S6 and S7 are repeated to start the read operation of the next page until the set page number condition is met and the reading of the bad block management data is terminated.

[0024] Furthermore, the step S1 of establishing the eNVM bad block cache area specifically includes: establishing the MSSIP core according to the planned cache space, and establishing N / 32-1 pages in the eNVM for storing bad block management data.

[0025] Furthermore, the initialization configuration in step S2 is specifically that after power-on, the processor initializes and configures the IP core through the APB interface.

[0026] Furthermore, the marking method in step S3 is as follows:

[0027] If it is 0xFFH, it means it is a good block, and 0xFFH is written according to the block address in the bad block management data cache module;

[0028] If it is not 0xFFH, it indicates a bad block, and 0x00H is written to the block address in the bad block management data cache module;

[0029] Furthermore, after the writing and erasing operations are completed, the eNVM write timing described in step S5 updates the bad block management data cache module if there is a new bad block, and gives a write eNVM valid enable signal after the NAND flash management module stops operating. The eNVM management module and the eNVM read and write timing module complete the writing and updating of the bad block data according to the above steps S4 and S5.

[0030] Furthermore, the registers described in step S6 include the MSS IP core and the eNVM.

[0031] Furthermore, the specific method of reading the status register status in step S7 is:

[0032] When the busy signal of the AHB interface module is invalid, the state of the read-back 0x60080120 register is determined. If the lowest bit of the data bit is 0, it means that the current eNVM is in a busy state. If it is 1, it means that the current eNVM is in an idle state.

[0033] When the AHB interface module is in an idle state, the state machine jumps to a read state, first gives a read address, then loops 32 times to read out a whole page of data, and then releases the eNVM as described in step S5 above.

[0034] Furthermore, the processor is ARM Cortex-M3.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] The method for managing and processing persistent bad blocks provided by the present invention is based on the ARM+FPGA architecture of the SOC chip, and stores bad block management data in the non-volatile memory (eNVM) on the SOC chip, which not only improves the storage reliability of the NAND flash, but also correspondingly saves NAND flash cache resources and other hardware costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 A schematic diagram of the SOC on-chip eNVM control block provided by the present invention;

[0039] Figure 2 A schematic diagram of the structure of a software module for managing bad solid-state blocks based on eNVM on a SOC chip provided by the present invention;

[0040] Figure 3 A schematic diagram of the bad block management on the SOC chip provided by the present invention, with block marking and cache;

[0041] Figure 4 A flow chart of the eNVM management module provided by the present invention;

[0042] Figure 5 A write flow chart of the eNVM read-write timing module provided by the present invention;

[0043] Figure 6 This is a read flow chart of the eNVM read and write timing module provided by the present invention.

[0044] Specific implementation methods

[0045] The present invention will be further described below in conjunction with the accompanying drawings.

[0046] The present invention proposes a method for managing fixed storage bad blocks based on eNVM on a system-on-chip. By setting a fixed area in the eNVM on the SOC chip as a bad block management data cache area, 128KB of eNVM resources are planned to be occupied, thereby forming a bad block management capability of 256Gb fixed storage capacity.

[0047] Taking the M2S090T chip as an example, the on-chip eNVM resources are 2x256KB, with 4096 pages. The actual available eNVM on the chip is 4000 pages. The space of each eNVM page is 1024 bits. Considering the triple-module redundancy requirement of storage, 32 blocks are managed per page. Each logical unit (Logic Unit Number, LUN) requires 128 pages of eNVM, and a maximum of 1000Gb of solid storage space can be managed.

[0048] Combined with the internal cache requirements of FPGA, a byte parallel marking method is used to mark the solid memory by block. Specifically, the good block is marked as 0xFFH, the factory bad block and the bad block generated by erasure are marked as 0x00H, and the dynamic bad block generated during the recording process is marked as 0XXXXXXXB (the lower seven bits indicate the page address where the recording failed). The specific marking diagram is as follows: Figure 1 shown.

[0049] According to the number of NAND flash blocks N, N / 32-1 pages are created in eNVM to store bad block management data. The main control FPGA manages the NAND flash online, and marks the bad block area at the factory and the newly added bad blocks after write and erase operations in the bad block management data cache module in the FPGA chip. Before the chip is powered off, the FPGA writes the bad block mark in the bad block management data cache module to the eNVM through the AHB interface. When the chip is powered on, the FPGA chip reads the bad block mark from the eNVM through the AHB interface to the bad block management data cache module. In combination with the specific implementation, a method for managing and storing bad blocks based on the eNVM on the SOC chip is clearly and completely described below.

[0050] The specific implementation measures of the present invention are as follows:

[0051] S1. Establish eNVM bad block cache area

[0052] according to Figure 2 The cache schematic diagram shown in the figure plans the cache space, establishes the MSS IP core, and establishes N / 32-1 pages in the eNVM to store the bad block management data.

[0053] S2. Initialization configuration

[0054] After power-on, the ARM Cortex-M3 processor initializes and configures the IP core through the APB interface;

[0055] S3, NAND flash factory bad block mark

[0056] After the first power-on, if Figure 1 As shown in , the NAND flash management module reads and judges the first byte of the redundant area of ​​the first page of each block of the NAND flash. If it is 0xFFH, it indicates a good block, and 0xFFH is written according to the block address in the bad block management data cache module. If it is not 0xFFH, it indicates a bad block, and 0x00H is written according to the block address in the bad block management data cache module. After all blocks are marked, a completion mark is given and a valid enable signal for writing eNVM is given.

[0057] S4, eNVM write setting page number management

[0058] like Figure 3 and Figure 4 As shown, after the eNVM management module receives the valid enable signal for writing eNVM, the state machine enters the state of writing eNVM from the standby state. In the state of writing eNVM, it is determined that the interface FIFO data is readable and the eNVM read-write timing module is in the ready state, and a valid signal for writing each page of eNVM is given, and the page address to be written is given.

[0059] S5, eNVM write timing

[0060] After receiving the page write enable signal and the address of the page to be written, the eNVM read / write timing module starts to jump state machine as follows: Figure 5 The flowchart shown in the figure jumps, and reads and writes eNVM through the AHB interface. First, the state machine enters the read status register state from the standby state. When the busy signal of the AHB interface module is invalid, the state of the read-back 0x60080120 register is judged. If the lowest bit of the data bit is 0, it means that the current eNVM is in a busy state. When it is 1, it means that the current eNVM is in an idle state. When the AHB interface module is in an idle state, 0x1 is written to the REQACCESS register 0x600801FC. When the AHB interface module enters the idle state again, the value of this register is read back, and the data bit is judged. If the lower three bits are 0x110, the register configuration state is entered, and configuration 0x40 is configured. 03800C register, after configuration is completed, after the AHB interface module enters the idle state, the state machine enters the write data state, writes 32 bits of data each time, and completes the data writing after 32 cycles, and then enters the write command state, writes the page address and other data to be written in the register 0x60080148 register, and then enters the waiting programming completion state. The eNVM write time per page is 10ms. During the waiting process, the register 0x60080120 register status is read back for judgment. When the read-back data bit 0 is 0x1, it means that the programming is completed. The state machine enters the write completion and releases the eNVM state, writes 0x0 in the 0x600801FC register to release the eNVM, and completes this page write operation.

[0061] The eNVM management module waits to receive the write completion signal from the eNVM read / write timing module. After receiving this signal, it determines whether the set write page number condition is met. If not, the address of the page to be written is incremented, and the above steps S4 and S5 are repeated to start the write operation of the next page until the set page number condition is met and the writing of the bad block management data is terminated.

[0062] S6, eNVM readout setting page number management

[0063] After each subsequent power-on, the M3 core will initialize and configure the MSS IP core, eNVM and other related registers through the APB interface. After the initialization configuration is completed, the FPGA can read and write eNVM through the AHB interface. Figure 4 As shown, after the power-on eNVM management module receives the valid enable signal for reading eNVM, the state machine enters the state of reading eNVM from the standby state, and gives a valid signal for reading each page of eNVM when the interface FIFO is writable and the eNVM read-write timing module is idle, and gives the page address to be read.

[0064] S7, eNVM read timing

[0065] After receiving the page read enable signal and the address of the page to be read, the eNVM read / write timing module starts to jump state machine as follows: Figure 6 The flowchart shown in the figure jumps, and reads and writes the eNVM through the AHB interface. First, the state machine enters the read status register state from the standby state. When the busy signal of the AHB interface module is invalid, the state of the read-back 0x60080120 register is judged. If the lowest bit of the data bit is 0, it means that the current eNVM is in a busy state. When it is 1, it means that the current eNVM is in an idle state. When the AHB interface module is in an idle state, the state machine jumps to the read state, first gives the read address, and then loops 32 times to read the entire page of data, and then releases the eNVM as described in step S5 above.

[0066] The eNVM management module waits to receive the read completion signal from the eNVM read / write timing module. After receiving this signal, it determines whether the set read page number condition is met. If not, the address of the page to be read is incremented, and the above steps S6 and S7 are repeated to start the read operation of the next page until the set page number condition is met and the reading of the bad block management data is terminated.

[0067] After the write and erase operations, if there are new bad blocks, the bad block management data cache module is updated, and a write eNVM valid enable signal is given after the NAND flash management module stops operating.

[0068] The eNVM management module and the eNVM read / write timing module complete the writing and updating of the bad block data according to the above steps S4 and S5.

[0069] Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the above disclosed methods and technical contents without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention. The contents not described in detail in the specification of the present invention belong to the known technology of professional and technical personnel in this field.

Claims

1. A method for managing solid memory bad blocks based on eNVM on SOC chip, characterized in that: The method comprises the following steps: S1. Establish eNVM bad block cache area S2. Initialization configuration S3, NAND flash factory bad block mark After the first power-on, the NAND flash management module reads and judges the first byte of the redundant area of ​​the first page of each block of the NAND flash, and marks it. After all blocks are marked, a completion mark is given, and a valid enable signal for writing eNVM is given; S4, eNVM write setting page number management After receiving the valid enable signal for writing eNVM obtained in step S3, the eNVM management module enters the state of writing eNVM from the standby state, determines that the interface FIFO data is readable and the eNVM read-write timing module is in an idle state in the state of writing eNVM, gives a page write enable signal for writing each page of eNVM, and gives the address of the page to be written; S5, eNVM write timing After receiving the page write enable signal and the address of the page to be written obtained in step S4, the eNVM read / write timing module starts to jump to perform a write operation according to the eNVM write protocol through the AHB interface; The eNVM management module waits to receive the write completion signal from the eNVM read / write timing module. After receiving this signal, it determines whether the set write page number condition is met. If the condition is not met, the address of the page to be written is incremented, and the above steps S4 and S5 are repeated to start the writing operation of the next page, until the set page number condition is met, and the writing of the bad block management data is terminated; S6, eNVM readout setting page number management After each subsequent power-on, the processor will initialize and configure the registers through the APB interface. After the initialization configuration is completed, the FPGA can read and write eNVM through the AHB interface; After the power-on eNVM management module receives the valid enable signal for reading eNVM, the state machine enters the state of reading eNVM from the standby state, and gives a page read enable signal for reading each page of eNVM when the interface FIFO is writable and the eNVM read-write timing module is idle, and gives the address of the page to be read; S7, eNVM read timing After receiving the page read enable signal and the address of the page to be read, the eNVM read / write timing module starts to jump. First, the state machine enters the read status register state from the standby state, and reads and writes the eNVM through the AHB interface, performing the read operation according to the eNVM protocol; The eNVM management module waits to receive the read completion signal from the eNVM read / write timing module. After receiving this signal, it determines whether the set read page number condition is met. If not, the address of the page to be read is incremented, and the above steps S6 and S7 are repeated to start the read operation of the next page until the set page number condition is met and the reading of the bad block management data is terminated.

2. The method for managing solid memory bad blocks based on SOC on-chip eNVM according to claim 1, characterized in that: The specific method of establishing the eNVM bad block cache area in step S1 is: according to the planned cache space, establish the MSS IP core, and establish N / 32-1 pages in the eNVM for storing bad block management data.

3. The method for managing solid memory bad blocks based on SOC on-chip eNVM according to claim 1, characterized in that: The specific method of initialization configuration in step S2 is: after power-on, the processor initializes and configures the IP core through the APB interface.

4. The method for managing solid memory bad blocks based on SOC on-chip eNVM according to claim 3, characterized in that: The processor is ARM Cortex-M3.

5. The method for managing solid memory bad blocks based on SOC on-chip eNVM according to claim 1, characterized in that: The marking method in step S3 is as follows: If it is 0xFFH, it means it is a good block, and 0xFFH is written according to the block address in the bad block management data cache module; If it is not 0xFFH, it indicates a bad block, and 0x00H is written according to the block address in the bad block management data cache module.

6. The method for managing solid memory bad blocks based on SOC on-chip eNVM according to claim 1, characterized in that: After the writing and erasing operations are completed, the eNVM write timing described in step S5 updates the bad block management data cache module if there is a new bad block, and gives a valid enable signal for writing eNVM after the NAND flash management module stops operating. The eNVM management module and the eNVM read and write timing module complete the writing and updating of the bad block data according to the above steps S4 and S5.

7. The method for managing solid memory bad blocks based on SOC on-chip eNVM according to claim 1, characterized in that: The registers described in step S6 include the MSS IP core and the eNVM.

8. The method for managing solid memory bad blocks based on SOC on-chip eNVM according to claim 1, characterized in that: The specific method of reading the status register status in step S7 is: When the busy signal of the AHB interface module is invalid, the state of the read-back 0x60080120 register is determined. If the lowest bit of the data bit is 0, it indicates that the current eNVM is in a busy state. When it is 1, it indicates that the current eNVM is in an idle state.

9. The method for managing solid memory bad blocks based on SOC on-chip eNVM according to claim 8, characterized in that: When the AHB interface module is in an idle state, the state machine jumps to a read state, first gives a read address, then loops 32 times to read out a whole page of data, and then releases the eNVM as described in step S5 above.

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