DTCO circuit structure optimization method and system based on deep learning and heuristic search

Abstract

The invention discloses a DTCO circuit structure optimization method and system based on deep learning and heuristic search, and the method comprises the steps: obtaining a circuit netlist of a target circuit for analysis, and dividing the target circuit into a plurality of independent function modules based on function demands; predicting the performance of different devices in the target circuit under a plurality of target process conditions based on a pre-trained deep learning model; searching an optimal circuit connection mode of the target circuit based on a heuristic search algorithm so as to carry out circuit structure layout topology; performing parameter optimization on the target circuit based on the optimal circuit connection mode; and based on the parameter optimization, evaluating the topological circuit through an SPICE simulation tool, verifying whether an optimization result meets a design requirement or not, and if the optimization result meets the design requirement, completing the optimization. Through a deep learning model and a heuristic search algorithm, with the guidance of agile design methodology, rapid and efficient optimization of an advanced process node large-scale circuit structure is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design optimization, and in particular relates to a DTCO circuit structure optimization method and system based on deep learning and heuristic search. Background Art

[0002] In the development of the semiconductor industry since Moore's era, the industry has changed from the IDM (Integrated Device Manufacturer) model to the Foundry & Fabless (wafer foundry and design formula) model. This model change separates the physical manufacturing of devices from the logical design of circuits, greatly reducing the complexity of chip design, thereby accelerating the iteration and update speed of the semiconductor industry in the past few decades. Despite the simplification, pure circuit design is still an NP-hard (Non-deterministic Polynomial-time hard) problem, which means that the computational complexity of designing the optimal solution for a circuit design that meets certain functional requirements increases exponentially with the growth of circuit scale and performance requirements.

[0003] Entering the post-Moore era, the DTCO methodology was proposed to solve the coordination problem between device manufacturing and circuit design, and became the key to promoting the industry to achieve more frequent communication between device and circuit design and optimize chip performance under the condition of slowing technology development. DTCO promotes cross-domain collaboration and innovation by comprehensively considering the physical characteristics of devices, manufacturing processes and circuit design requirements. However, with the development of chip process technology, the challenges faced by DTCO are also increasing. This challenge stems from the diversity of circuit design, the continuous advancement of process technology, and the market's drive for higher performance and energy efficiency. When dealing with large-scale integrated circuit design, traditional methods are often limited by the capabilities of computing resources and tools, and it is difficult to find the optimal or near-optimal design solution within a reasonable time. In addition, as the technology node advances to the nanometer level, the non-ideal factors in circuit design and changes in the manufacturing process have an increasingly greater impact on performance, which brings additional complexity to circuit design.

[0004] Existing technologies support the DTCO process to a certain extent, but there are still shortcomings. For example, when dealing with large-scale integrated circuit design, existing methods cannot effectively handle the complex interactions between the device level and the system level, resulting in limited design efficiency and optimization effects. In addition, existing technologies do not fully utilize the latest artificial intelligence and machine learning algorithms, which limits the ability to search for optimal solutions to circuit requirements in the complex design space of advanced process nodes. Summary of the invention

[0005] To solve the above problems, the purpose of the present invention is to provide a DTCO circuit structure optimization method and system based on deep learning and heuristic search, which combines deep learning models and heuristic search algorithms, and takes agile design methodology as a guide to achieve rapid and efficient optimization of large-scale circuit structures at advanced process nodes to meet the performance requirements and process conditions of different application scenarios. It is particularly suitable for rapidly changing process technology environments, and can accelerate the design iteration process while ensuring circuit performance, improve design flexibility and innovation, and reduce design complexity.

[0006] The technical solution provided by the present invention is: a DTCO circuit structure optimization method based on deep learning and heuristic search, comprising the following steps:

[0007] Obtaining a circuit netlist of a target circuit for analysis, and dividing the target circuit into a plurality of mutually independent functional modules based on functional requirements;

[0008] Predicting the performance of different devices in the target circuit under multiple target process conditions based on a pre-trained deep learning model;

[0009] Finding the optimal circuit connection mode of the target circuit based on a heuristic search algorithm to perform circuit structure layout topology;

[0010] Optimizing parameters of the target circuit based on the optimal circuit connection mode;

[0011] Based on the parameter optimization, the topology circuit is evaluated by SPICE simulation tool to verify whether the optimization result meets the design requirements. If so, the optimization is completed.

[0012] Preferably, dividing the target circuit into a plurality of mutually independent functional modules based on functional requirements further comprises:

[0013] The target circuit is quantitatively represented by a graph G(V,E) by using a graph theory method, wherein V is a vertex set representing nodes in the circuit, and E is an edge set representing electrical components or wires connecting these nodes; wherein the target circuit is designed based on an agile design method;

[0014] The target circuit is divided into several subgraphs G1, G2, ..., G n ,Each subgraph represents a functional module to optimize a specific performance indicator;

[0015] In the modular partitioning process, an objective function f is defined to measure the partitioning quality of the target circuit in terms of circuit performance, cost or manufacturability. The optimization problem is expressed as: The union of all subgraphs is equivalent to the target circuit, and the functional modules of the subgraphs do not overlap.

[0016] Preferably, before predicting the performance of different devices in the target circuit under multiple target process conditions based on the pre-trained deep learning model, the method includes:

[0017] Establishing a deep learning model based on a recurrent neural network, training the recurrent neural network based on a large amount of collected process parameters and performance data of the device to establish a mapping relationship between device performance and key parameters;

[0018] Device performance data based on semiconductor devices Where each x i is a vector containing multiple process parameters, and each y i is the corresponding performance output, N is the total number of x, and θ in the recurrent neural network represents its model parameters, with the mapping relationship f from input x to output y θ The goal of the model is to train the recurrent neural network to minimize the prediction error, which is achieved by minimizing the loss function L: Where l is the loss function, which is the mean square error MSE: l(f θ (x i ),y i )=||f θ (x i )-y i || 2 ;

[0019] Use the gradient descent algorithm to update the parameters θ, Among them, α is the learning rate, is the gradient of L with respect to θ;

[0020] During the training process, the model calculates the output results through forward propagation and adjusts the network parameters through back propagation to minimize the prediction error;

[0021] The trained deep learning model can make high-precision predictions on the performance of the device under different process conditions.

[0022] Preferably, searching for the optimal circuit connection mode of the target circuit based on a heuristic search algorithm to perform circuit structure layout topology further includes:

[0023] The circuit netlist is parsed to extract the connection relationship of each component in the circuit. During the parsing process, a unique identifier is assigned to each circuit node. The identifier of each circuit node will be used to represent the connection point of the circuit in the AST. The AST is constructed according to the connection relationship in the circuit netlist to present the structure of the target circuit in the form of a tree structure, in which each node represents an element in the circuit, and the connection relationship between the nodes represents the connection mode between the elements. The connection relationship and component information of the circuit are converted into the form of AST expressions;

[0024] Performing on the ASTA representation a heuristic search algorithm including but not limited to modifying nodes of the tree, adjusting relationships between nodes, and exploring different topological configurations of the circuit to find the circuit structure with the best performance;

[0025] Wherein, the heuristic search algorithm adopts a genetic algorithm.

[0026] Preferably, optimizing parameters of the target circuit based on the optimal circuit connection mode further includes:

[0027] The heuristic search algorithm uses a distributed genetic algorithm to optimize and adjust the device parameters of each circuit after the topology to achieve a predetermined performance index, wherein the distributed genetic algorithm searches by simulating the selection, inheritance and mutation processes in biological evolution;

[0028] Based on the initial circuit structure provided by the netlist, starting from a set of candidate solutions, each candidate solution represents a circuit layout of a topology;

[0029] Based on the existing circuit structure, an initial population P0 is created. Each individual I i ∈P0 represents a circuit topology and its device parameter configuration, and the size of the population is N;

[0030] The distributed genetic algorithm device parameters are adjusted for the topological circuit layout group, and the fitness of each individual F(I i ) evaluating by SPICE simulation calculation to reflect the predetermined performance index of the circuit, wherein the fitness function F needs to be maximized or minimized depending on the specific requirements of the performance index;

[0031] Candidate solutions whose performance meets the preset requirements are selected for crossover and mutation operations to generate a new set of candidate solutions. After multiple generations of iterations, the genetic algorithm tends to find solutions that are closer to or meet the predetermined performance indicators. If there are new circuit module requirements, the circuit topology and circuit parameter adjustment steps are cycled again.

[0032] Preferably, based on the parameter optimization, the topology circuit is evaluated by a SPICE simulation tool to verify whether the optimization result meets the design requirements, and further includes:

[0033] If the verification optimization result does not meet the design requirements, re-optimize and adjust the parameters;

[0034] If the optimization results meet the design requirements, the new circuit structure that meets the performance requirements and the key parameter data of the device after parameter adjustment are recorded in the agile design library. The information in the agile design library includes not only the physical layout and topological structure of the circuit, but also the key parameters of the circuit components, such as resistance, capacitance, and transistor size.

[0035] Each entry in the agile design library can be regarded as a structured data object D, which contains key information of the circuit: D = {T, P, V}, where T represents the topological structure of the circuit, P represents the physical layout of the circuit, and V represents the key parameters of the circuit components;

[0036] Each structured data object D needs to undergo performance verification F(D) to ensure that it meets the predetermined performance requirements: When , the structured data object D is recorded in the design library;

[0037] The agile design library L represents a set of structured data objects, and each newly verified structured data object D will be added to this set: To ensure that only designs that meet performance requirements are recorded and used for future references;

[0038] When a new structured data object D is needed, a design set S that meets specific requirements is retrieved from the agile design library L: S = {D∈L:Criteria(D)}, where Criteria(D) represents the conditions that the new design must meet.

[0039] Preferably, the method further comprises:

[0040] The agile design library is used to train the deep learning model M, and the deep learning model M extracts design rules and patterns: M=Train(L);

[0041] By analyzing the historical data of the agile design library L, the deep learning model M is used to predict the new design D new Provide optimization suggestions: D opt =Optimize(D new ,M).

[0042] Based on the same concept, the present invention also provides a DTCO circuit structure optimization system based on deep learning and heuristic search, including:

[0043] A data acquisition module, used to acquire a circuit netlist of a target circuit for analysis, and divide the target circuit into a plurality of independent functional modules based on functional requirements;

[0044] A performance prediction module, used to predict the performance of different devices in the target circuit under multiple target process conditions based on a pre-trained deep learning model;

[0045] A circuit topology module, used to find the optimal circuit connection mode of the target circuit based on a heuristic search algorithm to perform circuit structure layout topology;

[0046] A parameter optimization module, used for optimizing parameters of the target circuit based on the optimal circuit connection mode;

[0047] The verification module is used to evaluate the topological circuit through the SPICE simulation tool based on the parameter optimization to verify whether the optimization result meets the design requirements. If so, the optimization is completed.

[0048] Based on the same concept, the present invention also provides an electronic device, comprising:

[0049] A memory, the memory being used to store a processing program;

[0050] A processor, wherein when executing the processing program, the processor implements any one of the above-mentioned DTCO circuit structure optimization methods based on deep learning and heuristic search.

[0051] Based on the same concept, the present invention also provides a readable storage medium, on which a processing program is stored. When the processing program is executed by a processor, any one of the above-mentioned DTCO circuit structure optimization methods based on deep learning and heuristic search is implemented.

[0052] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0053] 1. The present invention adopts a modular division method to construct a circuit design process, decomposing complex circuits into manageable small modules. This decomposition not only enables designers to focus on the design of a single module, thereby improving the accuracy and quality of specific circuit functions, but also allows each module to be updated and optimized independently without the need to reconstruct the entire circuit. Such design adaptability and scalability make it more flexible to respond to changing market demands and technological advances. On this basis, by introducing a deep learning model to replace or assist the traditional process library device selection, the present invention can more accurately predict the performance of the device under different design conditions. The deep learning model can learn complex patterns from a large amount of data and provide more accurate predictions than traditional methods. This not only improves the accuracy of the design, but also helps to optimize the selection of devices, ensuring that the design has the best energy efficiency while meeting performance requirements.

[0054] 2. The application of the heuristic search algorithm of the present invention in circuit design can explore innovative solutions that are difficult to achieve with traditional methods. These algorithms can intelligently avoid unnecessary search areas and quickly locate potential design solutions. Therefore, designers can achieve more efficient and innovative circuit structure design while reducing the bias and limitations of human circuit design. And the agile design library records the results of each optimization, ensuring the continuity and iteration of the design process. This means that the design can be continuously iterated and improved based on previous best practices, rather than starting from scratch every time. This iterative approach not only speeds up the design process, but also improves the performance and reliability of the final product. The automated process significantly improves the efficiency of circuit design. Automated tools can quickly perform tedious design tasks, reduce human errors, and free up designers' time to focus on more creative circuit design work. Automation not only shortens the design cycle, but also reduces design costs by reducing repetitive work. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings, wherein:

[0056] Figure 1 It is a flow chart of the DTCO circuit structure optimization method based on deep learning and heuristic search of the present invention;

[0057] Figure 2 A schematic diagram of the process of modularizing the circuit of the present invention;

[0058] Figure 3 Provides a framework for the application of deep learning RNN models in device modeling;

[0059] Figure 4 An example of building a circuit netlist to a circuit structure AST;

[0060] Figure 5 It is a basic flow and operation diagram of the heuristic search algorithm in the circuit topology structure;

[0061] Figure 6 Design the library structure and functionality for Agile. DETAILED DESCRIPTION

[0062] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0063] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0064] Embodiment 1

[0065] like Figure 1 As shown, a DTCO circuit structure optimization method based on deep learning and heuristic search includes the following steps:

[0066] Obtaining a circuit netlist of a target circuit for analysis, and dividing the target circuit into a plurality of mutually independent functional modules based on functional requirements;

[0067] Predicting the performance of different devices in the target circuit under multiple target process conditions based on a pre-trained deep learning model;

[0068] Finding the optimal circuit connection mode of the target circuit based on a heuristic search algorithm to perform circuit structure layout topology;

[0069] Optimizing parameters of the target circuit based on the optimal circuit connection mode;

[0070] Based on the parameter optimization, the topology circuit is evaluated by SPICE simulation tool to verify whether the optimization result meets the design requirements. If so, the optimization is completed.

[0071] The technical solution of this embodiment divides the large-scale target circuit into modules, determines the specific application scenarios and performance requirements of the modules, and the module division process is: decomposing the entire circuit system into smaller, easier to manage and adjust circuit sub-modules. The purpose of modularization is to better adapt to different application scenarios and performance requirements, while simplifying the design process of large-scale circuits. Each module can be individually designed and optimized for its specific functions and performance requirements, making the optimization of the entire system more efficient and targeted. The key parameters of the devices in the module netlist are predicted by a pre-trained deep learning model. This step provides accurate device performance data for circuit design and promotes more reasonable circuit design decisions. Then the structural topology and parameter optimization are performed through a heuristic search algorithm. When the SPICE simulation tool evaluates that the optimization results meet the design requirements, the optimization is completed.

[0072] Preferably, see Figure 2 , dividing the target circuit into a plurality of mutually independent functional modules based on functional requirements further comprises:

[0073] The target circuit is quantitatively represented by a graph G(V,E) by using a graph theory method, wherein V is a vertex set representing nodes in the circuit, and E is an edge set representing electrical components or wires connecting these nodes; wherein the target circuit is designed based on an agile design method;

[0074] The target circuit is divided into several subgraphs G1, G2, ..., G n ,Each subgraph represents a functional module to optimize a specific performance indicator;

[0075] In the modular partitioning process, an objective function f is defined to measure the partitioning quality of the target circuit in terms of circuit performance, cost or manufacturability. The optimization problem is expressed as: The union of all subgraphs is equivalent to the target circuit, and the functional modules of the subgraphs do not overlap.

[0076] In the solution of this embodiment, modularization can be regarded as a graph partitioning problem, where the goal is to partition a large-scale circuit G into several subgraphs G1, G2, ..., G n In this way, the modularization of circuit design can be realized, so that the subsequent optimization steps can be carried out independently for each module, thereby improving the efficiency and effect of overall circuit optimization. The division process includes the definition, delimitation and interaction of different modules. Taking the large-scale circuit SAR ADC as an example, there is a sampling switch module: responsible for signal sampling, converting the analog signal into a charge form that can be stored by the capacitor array. Capacitor array module: as the core part of the SAR ADC, it stores the charge collected by the sampling switch module and participates in the analog-to-digital conversion process. Bias circuit module: provides a stable bias voltage for other circuit modules to ensure the normal operation of the circuit module. Auxiliary logic circuit module: coordinates the work of each module and provides necessary logic control signals. Preamplifier module: enhances the amplitude of the analog signal for subsequent analog-to-digital conversion. Dynamic latch comparator module: compares the voltage of the capacitor array with the reference voltage during the analog-to-digital conversion process to generate a comparison result. SAR logic module: based on the output of the comparator, gradually approximates and determines the digital representation of the analog signal. Signal frequency division circuit module: provides a clock signal for the SAR logic to control the rate of the analog-to-digital conversion process. Through this modular division, agile design methodology not only promotes the flexibility and manageability of the design process, but also improves the efficiency and maintainability of the design process. Each module can be independently designed, tested and optimized, and finally integrated into a high-performance SAR ADC circuit.

[0077] Preferably, before predicting the performance of different devices in the target circuit under multiple target process conditions based on the pre-trained deep learning model, the method includes:

[0078] Establishing a deep learning model based on a recurrent neural network, training the recurrent neural network based on a large amount of collected process parameters and performance data of the device to establish a mapping relationship between device performance and key parameters;

[0079] Device performance data based on semiconductor devices Where each x i is a vector containing multiple process parameters, and each y i is the corresponding performance output, N is the total number of x, and θ in the recurrent neural network represents its model parameters, with the mapping relationship f from input x to output y θ The goal of the model is to train the recurrent neural network to minimize the prediction error, which is achieved by minimizing the loss function L: Where l is the loss function, which is the mean square error MSE: l(f θ (x i ),y i )=||f θ (x i )-y i || 2 ;

[0080] Use the gradient descent algorithm to update the parameters θ, Among them, α is the learning rate, is the gradient of L with respect to θ;

[0081] During the training process, the model calculates the output results through forward propagation and adjusts the network parameters through back propagation to minimize the prediction error;

[0082] The trained deep learning model can make high-precision predictions on the performance of the device under different process conditions.

[0083] The technical solution of this embodiment collects a large amount of device process parameters and performance data, trains a recurrent neural network, and establishes a mapping relationship between device performance and key parameters. The recurrent neural network can capture the dynamic characteristics of parameters changing with the system simulation process, and is very suitable for predicting the electrical characteristics of device models in circuit simulation. The constructed deep learning model can accurately predict the performance output of the device under different process conditions, replacing the traditional manual adjustment of process parameters, thereby reducing the design cycle and improving the accuracy of circuit design. The trained deep learning model will be applied to subsequent circuit simulation iteration steps as a key component in the circuit optimization process, helping designers to quickly evaluate the impact of different design choices on performance, thereby achieving a better circuit design solution.

[0084] like Figure 3As shown in the figure, the application framework of the deep learning RNN model in circuit design is demonstrated, including the process of data preparation, model training and device performance prediction. Collect relevant data for circuit design and testing, such as circuit parameters, working environment, device performance indicators, etc. The data needs to be preprocessed, including cleaning, normalization, labeling, etc., so that the RNN model can better learn and extract features. During the training process, the model calculates the output results through forward propagation and adjusts the network parameters through back propagation to minimize the prediction error. Recurrent neural networks are particularly suitable for processing sequence data, so in circuit design, it can effectively learn the dynamic characteristics of circuit parameters changing over time. The trained RNN model can be used to predict the performance of circuit devices. By inputting new circuit parameters into the model, RNN can predict the working performance of the device under specific conditions, such as frequency response, power consumption, stability, etc.

[0085] like Figure 4 As shown in the figure, an example of constructing from a circuit netlist to a circuit structure AST is presented. Taking the 6-tube SRAM storage circuit module in the SAR ADC circuit as an example, the key content describing the connection relationship in the circuit netlist is extracted and converted into the form of AST expression, which facilitates the subsequent heuristic search algorithm to explore the circuit topology structure.

[0086] Preferably, searching for the optimal circuit connection mode of the target circuit based on a heuristic search algorithm to perform circuit structure layout topology further includes:

[0087] The circuit netlist is parsed to extract the connection relationship of each component in the circuit. During the parsing process, a unique identifier is assigned to each circuit node. The identifier of each circuit node will be used to represent the connection point of the circuit in the AST. The AST is constructed according to the connection relationship in the circuit netlist to present the structure of the target circuit in the form of a tree structure, in which each node represents an element in the circuit, and the connection relationship between the nodes represents the connection mode between the elements. The connection relationship and component information of the circuit are converted into the form of AST expressions;

[0088] Performing on the ASTA representation a heuristic search algorithm including but not limited to modifying nodes of the tree, adjusting relationships between nodes, and exploring different topological configurations of the circuit to find the circuit structure with the best performance;

[0089] Wherein, the heuristic search algorithm adopts a genetic algorithm.

[0090] The technical solution of this embodiment is expressed by converting the circuit structure in the circuit netlist after module division into AST. This representation can show the structure of the circuit in the form of a tree structure, in which each node represents an element in the circuit, such as a gate, a trigger, a connection, etc., and the connection relationship between the nodes represents the connection mode between the circuit elements. The circuit structure converted to AST is easier to be analyzed and processed by a computer program. This provides a clear and structured circuit description for the application of heuristic search algorithms, so that the subsequent structural optimization steps are more efficient. The heuristic search algorithm can be executed on this AST, including but not limited to modifying the nodes of the tree (i.e., circuit elements), adjusting the relationship between nodes (i.e., the connection mode between components), and exploring different topological configurations of the circuit to find a circuit structure with better performance. By converting the circuit netlist into AST, the optimization algorithm can take advantage of the tree structure, such as fast traversal and modification, to perform complex optimization tasks. The method of converting to AST provides a powerful tool for circuit structure optimization, making the circuit design process more automated and intelligent.

[0091] See also Figure 5 , describes the basic process and operation of the genetic algorithm, a heuristic search algorithm, in circuit topology optimization. For a topological circuit that has undergone a round of selection, crossover, and mutation search in the genetic algorithm, its parameter group distribution undergoes several rounds of heuristic search iterations until a new circuit structure that meets the design requirements is established, stored in the database, and put into practical application. Starting from an initial circuit topology, which is the starting point of the design, it may be a known working circuit or a randomly generated structure. In each round of iteration, the algorithm explores changes in the circuit topology, which may include adding, deleting, or modifying components and connections in the circuit. These changes are based on a set of heuristic rules or evaluation functions, aiming to improve circuit performance or meet specific design constraints. For each modified circuit topology, the algorithm evaluates its performance, involving circuit functional behavior and calculating performance indicators based on design requirements. The circuit structures with the best performance are recorded and used as new starting points in subsequent iterations. Through continuous iterations, the topological circuit gradually approaches an optimal circuit structure that meets the design requirements. Once a circuit topology with performance indicators that meet the predetermined standards is found, the genetic algorithm stops iterating. This process involves multiple performance indicators, such as power consumption, speed, area, etc.

[0092] For example, given a large-scale circuit segmented netlist module W with a specific function, the conversion function T converts the netlist into an AST structure, represented by A: A = T(W)

[0093] In this tree structure, each node n i Contains information about the circuit element, such as type t, input in, output out, and other possible properties p:n i={t,in,out,p}

[0094] The heuristic search algorithm H is used to execute on the AST, and the goal is to find a modified AST A' that optimizes the circuit performance P: A' = H(A)

[0095] Performance P is composed of {P1,P2,...,P n}Definitions, such as power consumption, area, speed, etc.

[0096] The way to adjust A includes but is not limited to modifying the node (circuit element) n i property p; adjust the relationship between nodes, that is, modify the position of input in and output out; explore different topological configurations.

[0097] Preferably, optimizing parameters of the target circuit based on the optimal circuit connection mode further includes:

[0098] The heuristic search algorithm uses a distributed genetic algorithm to optimize and adjust the device parameters of each circuit after the topology to achieve a predetermined performance index, wherein the distributed genetic algorithm searches by simulating the selection, inheritance and mutation processes in biological evolution;

[0099] Based on the initial circuit structure provided by the netlist, starting from a set of candidate solutions, each candidate solution represents a circuit layout of a topology;

[0100] Based on the existing circuit structure, an initial population P0 is created. Each individual I i ∈P0 represents a circuit topology and its device parameter configuration, and the size of the population is N;

[0101] The distributed genetic algorithm device parameters are adjusted for the topological circuit layout group, and the fitness of each individual F(I i ) evaluating by SPICE simulation calculation to reflect the predetermined performance index of the circuit, wherein the fitness function F needs to be maximized or minimized depending on the specific requirements of the performance index;

[0102] Candidate solutions whose performance meets the preset requirements are selected for crossover and mutation operations to generate a new set of candidate solutions. Thus, after multiple generations of iterations, the genetic algorithm tends to find solutions that are closer to or meet the predetermined performance indicators. If there are new circuit module requirements, the circuit topology and circuit parameter adjustment steps are cycled again.

[0103] In this embodiment, a group of candidate solutions is called a "population", and each candidate solution represents a circuit layout of a topology. The genetic algorithm can efficiently search the solution space to find the circuit topology and device parameter configuration that meet the design specifications, while reaching or approaching the required performance indicators, and meeting the key indicators of the design such as performance, power consumption, and area.

[0104] Preferably, based on the parameter optimization, the topology circuit is evaluated by a SPICE simulation tool to verify whether the optimization result meets the design requirements, and further includes:

[0105] If the verification optimization result does not meet the design requirements, re-optimize and adjust the parameters;

[0106] If the optimization results meet the design requirements, the new circuit structure that meets the performance requirements and the key parameter data of the device after parameter adjustment are recorded in the agile design library. The information in the agile design library includes not only the physical layout and topological structure of the circuit, but also the key parameters of the circuit components, such as resistance, capacitance, transistor size, etc.

[0107] Each entry in the agile design library can be regarded as a structured data object D, which contains key information of the circuit: D = {T, P, V}, where T represents the topological structure of the circuit, P represents the physical layout of the circuit, and V represents the key parameters of the circuit components;

[0108] Each structured data object D needs to undergo performance verification F(D) to ensure that it meets the predetermined performance requirements: The structured data object D is recorded in the design library;

[0109] The agile design library L represents a set of structured data objects, and each newly verified structured data object D will be added to this set: To ensure that only designs that meet performance requirements are recorded and used for future references;

[0110] When a new structured data object D is needed, a set of designs S that meet specific requirements is retrieved from the agile design library L: S = {D∈L:Criteria(D)}, where Criteria(D) represents the conditions that the new design must meet. Through this quantitative process, the concept of agile design library is clearly defined and can be used in circuit design software and systems. This approach improves the reusability and efficiency of the design while reducing the number of iterations and error rates in the design process.

[0111] In this embodiment, the agile design library acts as an information storage and retrieval system, which saves verified efficient circuit designs and configurations, providing valuable resources for future circuit design work. The development process of subsequent circuit design projects can be accelerated because designers can directly use or iterate based on optimized design solutions in the library without starting from scratch. The agile design library can also support more advanced data analysis and machine learning technologies. By analyzing and learning historical data in the library, design rules and patterns can be further refined, thereby realizing automated decision support and optimization suggestions in future designs.

[0112] Preferably, the method further comprises:

[0113] The agile design library is used to train the deep learning model M, and the deep learning model M extracts design rules and patterns: M=Train(L);

[0114] By analyzing the historical data of the agile design library L, the deep learning model M is used to predict the new design D new Provide optimization suggestions: D opt =Optimize(D new ,M).

[0115] In this embodiment, the agile design library is not only a passive data storage, but also a dynamic resource that actively participates in the design process. In addition, recording this data also helps maintain the continuity of the design and knowledge inheritance, especially when the circuit design team changes, new team members can quickly gain a deep understanding of the previous design. Therefore, the agile design library not only provides an optimization solution for the current design task, but also lays a solid foundation for long-term circuit design and development activities.

[0116] Therefore, the combined application of all the above methods of the present invention not only improves the agility and innovation of circuit design, but also reduces the complexity of circuit design, thereby achieving high efficiency and high performance of circuit design optimization.

[0117] like Figure 6 As shown in the figure, the structure and function of the agile design library are demonstrated, and how to store and manage the optimized circuit structure and parameters is explained. The agile design library is a system for storing and managing optimized circuit structures and parameters, which can support rapid iteration and improvement of circuit design. The design library has a well-organized structure that can store circuit designs in a variety of ways, such as circuit type, performance parameters, and design date. This structure makes it easy for users to quickly retrieve and compare different design solutions. When the heuristic search algorithm generates a new circuit topology, this topology and its related parameters are recorded and stored in the agile design library. This process includes verifying and testing the circuit performance to ensure that the newly entered design meets specific quality standards. The design library provides version control functions to record the historical versions of each design, including all modifications and updates. This allows the circuit design to trace back history, compare the performance of different versions, and restore to an earlier design state when needed. The agile design library supports parametric design, which means that certain features of the circuit can be defined by a set of parameters, which makes it possible to quickly adjust these parameters based on advanced algorithms such as machine learning to generate new circuit variants without having to design from scratch, facilitating the process node migration of the circuit.

[0118] Embodiment 2

[0119] Based on the same concept, the present invention also provides a DTCO circuit structure optimization system based on deep learning and heuristic search, including:

[0120] A data acquisition module, used to acquire a circuit netlist of a target circuit for analysis, and divide the target circuit into a plurality of independent functional modules based on functional requirements;

[0121] A performance prediction module, used to predict the performance of different devices in the target circuit under multiple target process conditions based on a pre-trained deep learning model;

[0122] A circuit topology module, used to find the optimal circuit connection mode of the target circuit based on a heuristic search algorithm to perform circuit structure layout topology;

[0123] A parameter optimization module, used for optimizing parameters of the target circuit based on the optimal circuit connection mode;

[0124] The verification module is used to evaluate the topological circuit through the SPICE simulation tool based on the parameter optimization to verify whether the optimization result meets the design requirements. If so, the optimization is completed.

[0125] The present invention adopts a modular partitioning method to construct a circuit design process, decomposing complex circuits into manageable small modules. This decomposition not only enables designers to focus on the design of a single module, thereby improving the accuracy and quality of specific circuit functions, but also allows each module to be updated and optimized independently without the need to reconstruct the entire circuit. Such design adaptability and scalability make it more flexible to respond to changing market demands and technological advances. On this basis, by introducing a deep learning model to replace or assist traditional process library device selection, the present invention can more accurately predict the performance of devices under different design conditions. The deep learning model can learn complex patterns from a large amount of data and provide more accurate predictions than traditional methods, which not only improves the accuracy of the design, but also helps to optimize the selection of devices, ensuring that the design has the best energy efficiency while meeting performance requirements.

[0126] In addition, the application of heuristic search algorithms in circuit design can explore innovative solutions that are difficult to achieve with traditional methods. These algorithms can intelligently avoid unnecessary search areas and quickly locate potential design solutions. As a result, designers can achieve more efficient and innovative circuit structure design while reducing the bias and limitations of human circuit design. And the agile design library records the results of each optimization, ensuring the continuity and iteration of the design process. This means that the design can be continuously iterated and improved based on previous best practices instead of starting from scratch every time. This iterative approach not only speeds up the design process, but also improves the performance and reliability of the final product. The automated process significantly improves the efficiency of circuit design. Automated tools can quickly perform tedious design tasks, reduce human errors, and free up designers' time to focus on more creative circuit design work. Automation not only shortens the design cycle, but also reduces design costs by reducing repetitive work.

[0127] Based on the same concept, the present invention also provides an electronic device, comprising:

[0128] A memory, the memory being used to store a processing program;

[0129] A processor, wherein when executing the processing program, the processor implements any one of the above-mentioned DTCO circuit structure optimization methods based on deep learning and heuristic search.

[0130] Based on the same concept, the present invention also provides a readable storage medium, on which a processing program is stored. When the processing program is executed by a processor, any one of the above-mentioned DTCO circuit structure optimization methods based on deep learning and heuristic search is implemented.

[0131] If the DTCO circuit structure optimization method based on deep learning and heuristic search is implemented in the form of program instructions and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of software, and the computer software is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc. Various media that can store program codes.

[0132] Those skilled in the art can clearly understand that, for the sake of convenience and brevity in description, the identification content specifically executed by the above-described system and device can refer to the corresponding process in the aforementioned method embodiment.

[0133] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they still fall within the protection scope of the present invention.

Claims

1. A DTCO circuit structure optimization method based on deep learning and heuristic search, characterized in that: The following steps are involved: Obtaining a circuit netlist of a target circuit for analysis, and dividing the target circuit into a plurality of mutually independent functional modules based on functional requirements; Predicting the performance of different devices in the target circuit under multiple target process conditions based on a pre-trained deep learning model; Finding the optimal circuit connection mode of the target circuit based on a heuristic search algorithm to perform circuit structure layout topology; Optimizing parameters of the target circuit based on the optimal circuit connection mode; Based on the parameter optimization, the topology circuit is evaluated by SPICE simulation tool to verify whether the optimization result meets the design requirements. If so, the optimization is completed.

2. The DTCO circuit structure optimization method based on deep learning and heuristic search according to claim 1, characterized in that: Dividing the target circuit into a plurality of mutually independent functional modules based on functional requirements further includes: The target circuit is quantitatively represented by a graph G(V,E) by using a graph theory method, wherein V is a vertex set representing nodes in the circuit, and E is an edge set representing electrical components or wires connecting these nodes; wherein the target circuit is designed based on an agile design method; The target circuit is divided into several subgraphs G1, G2, ..., G n ,Each subgraph represents a functional module to optimize a specific performance indicator; In the modular partitioning process, an objective function f is defined to measure the partitioning quality of the target circuit in terms of circuit performance, cost or manufacturability. The optimization problem is expressed as: The union of all subgraphs is equivalent to the target circuit, and the functional modules of the subgraphs do not overlap.

3. The DTCO circuit structure optimization method based on deep learning and heuristic search according to claim 1, characterized in that: Before predicting the performance of different devices in the target circuit under multiple target process conditions based on the pre-trained deep learning model, the method includes: Establishing a deep learning model based on a recurrent neural network, training the recurrent neural network based on a large amount of collected process parameters and performance data of the device to establish a mapping relationship between device performance and key parameters; Device performance data based on semiconductor devices where each x i is a vector containing multiple process parameters, and each y i is the corresponding performance output, N is the total number of x, and θ in the recurrent neural network represents its model parameters, with the mapping relationship f from input x to output y θ The goal of the model is to train the recurrent neural network to minimize the prediction error, which is achieved by minimizing the loss function L: Where l is the loss function, which is the mean square error MSE: l(f θ (x i ),y i )=||f θ (x i )-y i || 2 ; Use the gradient descent algorithm to update the parameters θ, Among them, α is the learning rate, is the gradient of L with respect to θ; During the training process, the model calculates the output results through forward propagation and adjusts the network parameters through back propagation to minimize the prediction error; The trained deep learning model can make high-precision predictions on the performance of the device under different process conditions.

4. The DTCO circuit structure optimization method based on deep learning and heuristic search according to claim 1, characterized in that: Finding the optimal circuit connection mode of the target circuit based on the heuristic search algorithm to perform circuit structure layout topology further includes: The circuit netlist is parsed to extract the connection relationship of each component in the circuit. During the parsing process, a unique identifier is assigned to each circuit node. The identifier of each circuit node will be used to represent the connection point of the circuit in the AST. The AST is constructed according to the connection relationship in the circuit netlist to present the structure of the target circuit in the form of a tree structure, in which each node represents an element in the circuit, and the connection relationship between the nodes represents the connection mode between the elements. The connection relationship and component information of the circuit are converted into the form of AST expressions; Performing on the ASTA representation a heuristic search algorithm including but not limited to modifying nodes of the tree, adjusting relationships between nodes, and exploring different topological configurations of the circuit to find the circuit structure with the best performance; Wherein, the heuristic search algorithm adopts a genetic algorithm.

5. The DTCO circuit structure optimization method based on deep learning and heuristic search according to claim 1, characterized in that: Optimizing parameters of the target circuit based on the optimal circuit connection mode further includes: The heuristic search algorithm uses a distributed genetic algorithm to optimize and adjust the device parameters of each circuit after the topology to achieve a predetermined performance index, wherein the distributed genetic algorithm searches by simulating the selection, inheritance and mutation processes in biological evolution; Based on the initial circuit structure provided by the netlist, starting from a set of candidate solutions, each candidate solution represents a circuit layout of a topology; Based on the existing circuit structure, an initial population P0 is created. Each individual I i ∈P0 represents a circuit topology and its device parameter configuration, and the size of the population is N; The distributed genetic algorithm device parameters are adjusted for the topological circuit layout group, and the fitness of each individual F(I i ) evaluating by SPICE simulation calculation to reflect the predetermined performance index of the circuit, wherein the fitness function F needs to be maximized or minimized depending on the specific requirements of the performance index; Candidate solutions whose performance meets the preset requirements are selected for crossover and mutation operations to generate a new set of candidate solutions. After multiple generations of iterations, the genetic algorithm tends to find solutions that are closer to or meet the predetermined performance indicators. If there are new circuit module requirements, the circuit topology and circuit parameter adjustment steps are cycled again.

6. The DTCO circuit structure optimization method based on deep learning and heuristic search according to claim 1, characterized in that: Based on the parameter optimization, the circuit after topology is evaluated by SPICE simulation tool to verify whether the optimization result meets the design requirements, and further includes: If the verification optimization result does not meet the design requirements, re-optimize and adjust the parameters; If the optimization results meet the design requirements, the new circuit structure that meets the performance requirements and the key parameter data of the device after parameter adjustment are recorded in the agile design library. The information in the agile design library includes not only the physical layout and topological structure of the circuit, but also the key parameters of the circuit components, such as resistance, capacitance, and transistor size. Each entry in the agile design library can be regarded as a structured data object D, which contains key information of the circuit: D = {T, P, V}, where T represents the topological structure of the circuit, P represents the physical layout of the circuit, and V represents the key parameters of the circuit components; Each structured data object D needs to undergo performance verification F(D) to ensure that it meets the predetermined performance requirements: When F(D)=1, the structured data object D is recorded in the design library; The agile design library L represents a set of structured data objects, and each newly verified structured data object D will be added to this set: To ensure that only designs that meet performance requirements are recorded and used for future references; When a new structured data object D is needed, a design set S that meets specific requirements is retrieved from the agile design library L: S = {D∈L:Criteria(D)}, where Criteria(D) represents the conditions that the new design must meet.

7. The DTCO circuit structure optimization method based on deep learning and heuristic search according to claim 6, characterized in that: The method further comprises: The agile design library is used to train the deep learning model M, and the deep learning model M extracts design rules and patterns: M=Train(L); By analyzing the historical data of the agile design library L, the deep learning model M is used to predict the new design D new Provide optimization suggestions: D opt =Optimize(D new ,M).

8. A DTCO circuit structure optimization system based on deep learning and heuristic search, characterized in that: include: A data acquisition module, used to acquire a circuit netlist of a target circuit for analysis, and divide the target circuit into a plurality of independent functional modules based on functional requirements; A performance prediction module, used to predict the performance of different devices in the target circuit under multiple target process conditions based on a pre-trained deep learning model; A circuit topology module, used to find the optimal circuit connection mode of the target circuit based on a heuristic search algorithm to perform circuit structure layout topology; A parameter optimization module, used for optimizing parameters of the target circuit based on the optimal circuit connection mode; The verification module is used to evaluate the topological circuit through the SPICE simulation tool based on the parameter optimization to verify whether the optimization result meets the design requirements. If so, the optimization is completed.

9. An electronic device, characterized in that: include: A memory, the memory being used to store a processing program; A processor, wherein when executing the processing program, the processor implements the DTCO circuit structure optimization method based on deep learning and heuristic search as described in any one of claims 1 to 7.

10. A readable storage medium, characterized in that: The readable storage medium stores a processing program, and when the processing program is executed by the processor, the DTCO circuit structure optimization method based on deep learning and heuristic search as described in any one of claims 1 to 7 is implemented.

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