Memory, test system and test method

Abstract

The invention provides a memory, a test system and a test method. The memory comprises a memory main control unit and a voltage adjusting unit, wherein the voltage adjusting unit is used for receiving interface power supplies with different voltages and core power supplies with different voltages provided by the outside; the voltage adjusting unit is also used for judging the working state of the memory according to the interface power supply and / or the core power supply; and the voltage adjusting unit and the main control unit adjust the working state of the memory according to the judgment result. According to the memory, the test system and the test method provided by the invention, the stability of the power supply voltage of the memory can be maintained in a power supply fluctuation scene, and the data security can be guaranteed to the greatest extent when an exception occurs.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a memory, a test system and a test method. Background Art

[0002] With the widespread application of memory in consumer electronic devices such as smart TVs, set-top boxes, and mobile terminals, its data reliability and stability have become core requirements. The memory is composed of an ARM architecture main control unit and a NAND Flash flash memory unit. The main control unit implements key functions such as bad block management, garbage collection (GC), performance optimization, and life maintenance of the storage unit by running firmware. At the same time, sensitive data stored in the firmware (such as security keys and digital copyright information) needs to rely on a secure area for protection, which places higher requirements on the stability of the coordinated operation of hardware and firmware.

[0003] In practical applications, the stability of the memory's power supply voltage (core power supply voltage (VCC) and interface power supply voltage (VCCQ)) directly affects the reliability of the firmware's data processing. Due to the complex operating environment of terminal devices, abnormal voltage fluctuations may cause firmware logic errors, data read and write failures, and even hardware damage, thereby threatening the security of sensitive information and storage integrity. Therefore, how to maintain the stability of the memory's power supply voltage in power supply fluctuation scenarios and maximize data security when anomalies occur is an urgent problem to be solved. Summary of the invention

[0004] The purpose of the present invention is to provide a memory, a test system and a test method, which can maintain the stability of the power supply voltage of the memory in a power supply fluctuation scenario and maximize data security when an abnormality occurs.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention provides a memory, comprising a main control unit and a voltage adjustment unit, wherein the voltage adjustment unit is used to receive interface power supplies with different voltages and core power supplies with different voltages provided by the outside world; The voltage adjustment unit is further used to determine the working state of the memory according to the interface power supply and / or the core power supply; the voltage adjustment unit and the main control unit adjust the working state of the memory according to the determination result.

[0006] In one embodiment of the present invention, the voltage adjustment unit includes: A judgment subunit, used for judging the working state of the memory according to the interface power supply and the core power supply, and generating a compensation instruction, an interrupt instruction, and a power-off instruction based on the judgment result; A feedback subunit, used for obtaining an interface compensation power supply and a core compensation power supply according to the compensation instruction; A regulating subunit, used for compensating the interface power supply according to the interface compensation power supply to obtain a compensated interface power supply; the regulating subunit is also used for compensating the core power supply according to the core compensation power supply to obtain a compensated core power supply; The output subunit is used to output the compensated interface power supply to the main control unit, and output the compensated core power supply to the flash memory unit of the memory.

[0007] In one embodiment of the present invention, the determination subunit generates a compensation instruction, an interruption instruction, and a power-off instruction according to the following steps: Determine the working state of the memory according to the interface power supply and / or the core power supply: When the memory is in the undervoltage mode, a compensation instruction is generated and sent; the feedback subunit and the adjustment subunit perform a voltage compensation operation according to the compensation instruction; the voltage compensation operation means compensating the interface power supply and / or the core power supply until the memory exits the undervoltage mode; When the memory is in a low power consumption mode, an interrupt instruction is generated and sent; the main control unit performs a data backup operation according to the interrupt instruction; the data backup operation means backing up the data in the mapping table and the cache unit, and stopping power supply to the idle modules in the memory; When the memory is in the power-off mode, a power-off instruction is generated and sent; and the main control unit performs a shutdown operation according to the power-off instruction.

[0008] In one embodiment of the present invention, the feedback subunit obtains the interface compensation power supply and the core compensation power supply according to the following steps: Acquiring the voltage of the interface power supply and the voltage of the core power supply according to the compensation instruction; Calculating the difference between the voltage of the interface power supply and the voltage of the standard interface power supply to obtain an interface compensation voltage, and generating a corresponding interface compensation power supply according to the interface compensation voltage; The difference between the voltage of the core power supply and the voltage of the standard core power supply is calculated to obtain a core compensation voltage, and a corresponding core compensation power supply is generated according to the core compensation voltage.

[0009] The present invention also provides a memory test system, the test system comprising: A processing module, used for generating and sending voltage regulation instructions, and monitoring the working state of the memory; The power management module is used to output interface power supplies of different voltages and core power supplies of different voltages to the memory according to the voltage control instruction.

[0010] In one embodiment of the present invention, the processing module is further used to monitor the judgment subunit to determine whether the judgment subunit generates a corresponding compensation instruction, interrupt instruction, and power-off instruction after receiving interface power supplies of different voltages and core power supplies of different voltages: When the corresponding compensation instruction, the interruption instruction, and the power-off instruction are not generated, it is determined that the determination subunit is abnormal.

[0011] In one embodiment of the present invention, the processing module is further used to monitor the feedback subunit and the regulating subunit, and determine whether the feedback subunit and the regulating subunit perform a voltage compensation operation after receiving a compensation instruction: When the voltage compensation operation is not performed, it is determined that the feedback subunit and the adjustment subunit are abnormal; the voltage compensation operation means compensating the interface power supply and / or the core power supply until the memory exits the undervoltage mode.

[0012] In one embodiment of the present invention, the processing module is also used to monitor the main control unit and determine whether the main control unit performs a data backup operation after receiving an interrupt instruction: when the data backup operation is not performed, it is determined that there is an abnormality in the firmware of the memory; the data backup operation indicates backing up the data in the mapping table and the cache unit, and stopping power supply to the idle modules in the memory.

[0013] In one embodiment of the present invention, the processing module is also used to monitor the main control unit and determine whether the main control unit performs a shutdown operation after receiving a power-off instruction: when the shutdown operation is not performed, it is determined that there is an abnormality in the firmware of the memory.

[0014] The present invention also provides a memory testing method, the testing method comprising: Generate and send voltage control instructions; Outputting interface power supplies of different voltages and core power supplies of different voltages to the memory according to the voltage control instruction; Monitor the working status of the memory and complete the test of the memory.

[0015] As described above, the present invention provides a memory, a test system and a test method, which significantly improves the test coverage through the testing of the system and firmware in the development stage, combined with a rich VCC / VCCQ type configuration, ensures the stable operation of the firmware in a complex terminal environment, and reduces the risk of logical errors caused by voltage anomalies. The differentiated strategy is flexibly triggered according to the degree of voltage anomaly, including voltage compensation, data backup, emergency shutdown and other operations, which not only avoids system interruption caused by over-protection, but also maximizes data security and hardware integrity.

[0016] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0018] Figure 1 is a schematic diagram of a memory in one embodiment of the present invention; Figure 2 is a schematic diagram of an adjustment unit in one embodiment of the present invention; Figure 3 A schematic diagram of a test system according to an embodiment of the present invention; Figure 4 A schematic diagram of inputting different core power supplies to a memory at different times in one embodiment of the present invention; Figure 5 A schematic diagram of inputting different interface power supplies to a memory at different times in one embodiment of the present invention; Figure 6 Flow chart of a testing method in one embodiment of the present invention.

[0019] In the figure: 100, processing module; 200, memory module; 300, storage module; 400, power module; 500, power management module; 600, interface module; 700, memory; 710, main control unit; 720, interface unit; 730, read-only storage unit; 740, random access storage unit; 750, cache unit; 760, flash memory unit; 770, front-end interface processing unit; 780, adjustment unit; 781, sampling subunit; 782, judgment subunit; 783, protection subunit; 784, output subunit; 785, feedback subunit; 786, regulation subunit. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] See also Figure 1 The present invention provides a memory, and the memory 700 can be an embedded MultiMediaCard (eMMC) or a universal flash storage (UFS). The memory 700 can communicate with the processing module 100 through the CMD line and the DATA0~7 lines, and perform operations such as reading, writing, and erasing by receiving instructions from the processing module 100. The processing module 100 can send instructions through the CMD line and transmit data through the DATA0~7 lines. The communication protocol between the memory 700 and the processing module 100 can follow the JEDEC protocol. The memory may include a main control unit 710, an interface unit 720, a read-only storage unit 730, a random access storage unit 740, a cache unit 750, a flash memory unit 760, a front-end interface processing unit 770, an adjustment unit 780, and the like.

[0022] See also Figure 1 In some embodiments, the main control unit 710 may be a microcontroller unit (MCU). The main control unit 710 may be used to perform specific control tasks, such as reading data, processing instructions from the processing module 100, etc. The processing core of the main control unit 710 may be designed based on the RISC-V architecture to perform various control and computing tasks.

[0023] See also Figure 1In some embodiments, the interface unit 720 (interface) can be a transmission interface and a power supply interface between the main control unit 710 and the processing module 100. The interface unit 720 can receive instructions from the processing module 100 and return data or status information to the processing module 100. The interface unit 720 can receive instructions from the processing module 100 through the CMD line and the DATA line, and return the result data or execution status to the processing module 100 through the DATA line. The interface unit 720 can also be used to receive core power supplies (VCC) of different voltages and interface power supplies (VCCQ) of different voltages provided by the outside world. The interface unit 720 can be connected to the main control unit 710, and the main control unit 710 can be electrically connected to the cache unit 750. The main control unit 710, the cache unit 750, etc. can be used to work according to the interface power supply (VCCQ). The interface unit 720 can be electrically connected to the flash memory unit 760, and the flash memory unit 760 can work according to the interface power supply (VCCQ).

[0024] See also Figure 1 In some embodiments, the read-only storage unit 730 may be a non-volatile memory (ROM) for long-term data storage. The read-only storage unit 730 may store a program, such as firmware. The program may be a set of pre-written instructions that instruct the main control unit 710 on how to start and run. These instructions include device initialization, peripheral configuration, and a possible boot loader. The boot loader may be used to load an updated program or operating system, etc.

[0025] See also Figure 1 In some embodiments, the random access memory unit 740 may be a volatile memory (Random Access Memory, RAM) for temporarily storing data and program codes. The random access memory unit 740 may be used to temporarily store data. When the main control unit 710 executes a program, the program code may be loaded from the read-only memory unit 730 into the random access memory unit 740 for execution.

[0026] See also Figure 1 In some embodiments, the cache unit 750 can be used as a high-speed temporary storage area between the main control unit 710 and the flash memory unit 760 to store data and instructions frequently accessed by the main control unit 710 to achieve the function of accelerating data transmission. The cache unit 750 can be further divided into a read cache unit (Read Buffer) and a write cache unit (Write Buffer). The read cache unit is mainly used to increase the speed of data reading and reduce the access to the main storage device; while the write cache unit is mainly used to improve the efficiency of data writing and optimize the performance of write operations.

[0027] See also Figure 1 In some embodiments, the flash memory unit 760 may be a physical unit (nand) for storing data in the memory 700. The flash memory unit 760 may be composed of a plurality of storage blocks. Each storage block may contain a plurality of pages. Each page is the minimum unit of a read / write operation, and a block is the minimum unit of an erase operation. Data is usually read and written in units of pages, and the entire block needs to be erased when erasing.

[0028] See also Figure 1 In some embodiments, the front-end interface processing unit 770 (FE IP) can receive command data from the processing module 100 through a front-end interface (such as UART, SPI, I2C, Ethernet, etc.). Decode the received command and extract key information (such as operation type, target address, parameters, etc.). Convert the parsed command into the internal operation instruction required by the main control unit 710 to ensure that the main control unit 710 can execute correctly. After processing the command, the main control unit 710 can return the execution result or status information to the processing module 100 through the front-end interface processing unit 770 so that the processing module 100 can understand whether the operation is successful or obtain the required data.

[0029] See also Figure 1 and Figure 2 In some embodiments, the adjustment unit 780 (Voltage Difference Transducer, VDT) can be electrically connected to the interface unit 720, the main control unit 710, and the flash memory unit 760, respectively, and the adjustment unit 780 can be used to determine the working state of the memory 700 according to the core power supply and / or the interface power supply. The adjustment unit 780 and the main control unit 710 can adjust the working state of the memory 700 according to the judgment result. The adjustment unit 780 may include a sampling subunit 781, a judgment subunit 782, a protection subunit 783, an output subunit 784, a feedback subunit 785, and a regulation subunit 786.

[0030] See also Figure 2In some embodiments, the sampling subunit 781 can be used to receive the core power supply and the interface power supply from the interface unit 720, and perform real-time sampling of the voltage of the core power supply (VCC) and the voltage of the interface power supply (VCCQ) to capture their voltage values ​​and change trends. Subsequently, the sampling subunit 781 can transmit the sampled VCC and VCCQ to the downstream unit (such as the judgment subunit 782) for subsequent processing and analysis. The sampling subunit 781 determines the working state of the memory 700 by monitoring the change trend (voltage difference and voltage change rate) of VCC and VCCQ over a period of time.

[0031] See also Figure 2 In some embodiments, the sampling subunit 781 may be a voltage sampling circuit. The voltage sampling circuit may sample VCC and VCCQ using a high-precision ADC (analog-to-digital converter) to ensure data accuracy. The voltage sampling circuit may also calculate the voltage difference between VCC and VCCQ through a differential amplifier or a digital calculation circuit. The voltage sampling circuit may also calculate the voltage change rate of VCC and VCCQ through a differential circuit or a digital algorithm.

[0032] See also Figure 2 In some embodiments, the main function of the judgment subunit 782 is to judge the working state of the memory 700 according to the core power supply and the interface power supply output by the sampling subunit 781, and generate a compensation instruction, an interrupt instruction, and a power-off instruction based on the judgment result. The judgment subunit 782 can judge whether the working state of the memory 700 is normal according to the comparison relationship between the voltage of the core power supply and the preset reference core voltage, and the comparison relationship between the voltage of the interface power supply and the preset reference interface voltage.

[0033] In some embodiments, the reference core voltage may include a normal reference core voltage (VCC1), an undervoltage reference core voltage (VCC2), an interrupt reference core voltage (VCC3), a power-off reference core voltage (VCC4), etc.; the reference interface voltage may include a normal reference interface voltage (VCCQ1), an undervoltage reference interface voltage (VCCQ2), an interrupt reference interface voltage (VCCQ3), and a power-off reference interface voltage (VCCQ4). For different types of memories, the sizes of VCC1~VCC4 may be different, for example, VCC1=3.3V, VCC2=2.7V, VCC3=2.1V, VCC3=0.3V, and for another example, the size relationship of VCC1~VCC3 may be set in proportion, VCC2 / VCC1 may be in the range of 0.75~0.85, and VCC3 / VCC2 may be in the range of 0.75~0.85. The specific size setting rules of VCCQ1~VCCQ4 may be similar to those of VCC1~VCC4, and are not limited here. The power-down reference core voltage (VCC4) and the power-down reference interface voltage (VCCQ4) refer to the reference voltages of the memory when it is completely powered off.

[0034] In some embodiments, the normal reference core voltage (VCC1) and the normal reference interface voltage (VCCQ1) may be the minimum voltage thresholds for normal operation of the memory 700. When the voltage of the core power supply (VCC) is greater than the normal reference core voltage (VCC1), and the voltage of the interface power supply (VCCQ) is greater than the normal reference interface voltage (VCCQ1), the memory 700 may be considered to be in normal operation. The core power supply may power the core logic circuit of the memory 700, such as the flash memory unit 760, etc. The stability of VCC directly affects the data storage and reading performance of the memory 700. The interface power supply may power the main control unit 710, the control logic, etc. of the memory 700. The stability of VCCQ directly affects the communication quality between the memory 700 and the processing module 100, and the stability of the control logic of the memory 700.

[0035] In some embodiments, when the voltage of the core power supply (VCC) and the voltage of the interface power supply (VCCQ) meet specific conditions, for example, when the voltage of the core power supply (VCC) is less than or equal to the normal reference core voltage (VCC1) and greater than the undervoltage reference core voltage (VCC2), the voltage of the interface power supply (VCCQ) is greater than the normal reference interface voltage (VCCQ2), or the voltage of the core power supply (VCC) is greater than the undervoltage reference core voltage (VCC2), the voltage of the interface power supply (VCCQ) is less than or equal to the normal reference interface voltage (VCCQ1) and greater than the undervoltage reference interface voltage (VCCQ2), the memory 700 can be considered to be in the undervoltage mode. In the undervoltage mode, the judgment subunit 782 generates a compensation instruction, and the feedback subunit 785 and the adjustment subunit 786 perform a voltage compensation operation until the memory exits the undervoltage mode.

[0036] In some embodiments, the undervoltage mode refers to a state where the voltage of the core power supply (VCC) or the interface power supply (VCCQ) of the memory 700 is lower than the normal reference voltage (VCC1 or VCCQ1) but higher than the undervoltage reference voltage (VCC2 or VCCQ2). At this time, although the memory 700 can still work, it may not be able to perform at its best performance, and there may even be a risk of data error or communication failure.

[0037] In some embodiments, when the core power supply and the interface power supply meet specific conditions, for example, when the voltage of the core power supply (VCC) is less than or equal to the undervoltage reference core voltage (VCC2) and greater than the interruption reference core voltage (VCC3), the voltage of the interface power supply (VCCQ) is greater than the interruption reference interface voltage (VCCQ3), or the voltage of the core power supply (VCC) is greater than the interruption reference core voltage (VCC3), the voltage of the interface power supply (VCCQ) is less than or equal to the undervoltage reference interface voltage (VCCQ2) and greater than the interruption reference interface voltage (VCCQ3), the memory 700 can be considered to be in low power consumption mode. In the low power consumption mode, the judgment subunit 782 will generate an interrupt instruction, and the main control unit 710 will perform a data backup operation according to the instruction to reduce power consumption and ensure data security.

[0038] In some embodiments, the data backup operation refers to ensuring the safe storage of key data (such as mapping tables and cache data (CacheFlush)) through a series of firmware internal algorithms and hardware operations when the memory 700 enters the low power consumption mode, and shutting down idle modules to reduce power consumption.

[0039] In some embodiments, the mapping table is a key data structure used to record the correspondence between logical addresses and physical addresses in the memory 700. The mapping table ensures the correct storage and reading of data in the memory 700. The main control unit 710 can copy the contents of the mapping table to the flash memory unit 760 by starting the backup algorithm inside the firmware to prevent the loss of the mapping table due to voltage abnormality or power failure, thereby avoiding data reading errors or storage confusion. After the memory 700 returns to normal, the backup data can be quickly restored to ensure the normal operation of the memory 700 and reduce system interruption time.

[0040] In some embodiments, the cache unit 750 is a fast access area in the memory 700 for temporarily storing data, and the cache unit 750 can improve the efficiency of data reading and writing. Cache Flush means forcibly writing the data in the cache unit 750 to the flash memory unit 760 to ensure that the data will not be lost due to power failure, so as to prevent the data in the cache unit 750 from being lost due to voltage abnormality or power failure, and ensure the integrity and consistency of the data. After the memory 700 returns to normal, the backup data can be quickly restored to ensure the normal operation of the memory 700 and reduce the system interruption time.

[0041] In some embodiments, the idle module refers to a part of the memory 700 that is not currently in use, such as an unused storage unit, interface circuit, or cache unit. The main control unit 710 can shut down unnecessary modules according to the current working state. For example, if the memory 700 currently has only a read operation, the write cache unit is shut down; if the memory 700 currently has only a write operation, the read cache unit is shut down. By shutting down the idle module, the power consumption of the memory can be significantly reduced.

[0042] In some embodiments, when the voltage of the core power supply (VCC) is less than or equal to the interrupt reference core voltage (VCC3), or the voltage of the interface power supply (VCCQ) is less than or equal to the interrupt reference interface voltage (VCCQ3), the memory 700 can be considered to be in power-off mode. In the power-off mode, the judgment subunit 782 will generate and send a power-off instruction, and the main control unit 710 will perform a shutdown operation according to the instruction to ensure data security and system stability. The power-off mode refers to the state where the voltage of the core power supply (VCC) or the voltage of the interface power supply (VCCQ) of the memory 700 is lower than or equal to the interrupt reference voltage (VCC3 or VCCQ3). At this time, the power supply of the memory is not enough to maintain normal operation, and the system must immediately take a shutdown operation to prevent data loss or hardware damage.

[0043] In some embodiments, in power-off mode, the main control unit 710 will immediately stop all ongoing read and write operations to prevent data errors or loss due to insufficient voltage. At the same time, the main control unit 710 will also force the data in the cache unit 750 to be written into the flash memory unit 760 to ensure that the cached data will not be lost due to power failure. Finally, the main control unit 710 can copy the contents of the mapping table to the flash memory unit 760 by starting the backup algorithm inside the firmware.

[0044] See also Figure 2 In some embodiments, the protection subunit 783 is used to monitor the core power supply and interface power supply output by the judgment subunit 782, and to monitor the core compensation power supply and interface compensation power supply output by the adjustment subunit 786. The main function of the protection subunit 783 is to monitor the core power supply, interface power supply, interface compensation power supply, and core compensation power supply to prevent damage to the internal circuit of the chip due to abnormal voltage or current. For example, if VCC or VCCQ exceeds the normal range, the protection mechanism (such as shutting down the power supply or limiting the current) is triggered.

[0045] See also Figure 2 In some embodiments, the main function of the output subunit 784 is to transfer the core power supply from the judgment subunit 782 to the flash memory unit 760, and transfer the interface power supply from the judgment subunit 782 to the main control unit 710, so as to ensure that the main control unit 710 and the flash memory unit 760 can obtain a stable power supply. During the transmission process, the output subunit 784 will perform filtering and voltage stabilization to ensure that the fluctuation of VCC and VCCQ will not affect the performance of the main control unit 710 and the flash memory unit 760.

[0046] See also Figure 2 In some embodiments, the feedback subunit 785 can be used to generate a core compensation power supply and an interface compensation power supply. Specifically, the feedback subunit 785 can obtain VCC and VCCQ output by the output subunit 784 according to the compensation instruction. The feedback subunit 785 can generate a core compensation voltage by calculating the difference between VCC and the standard core voltage, and then generate a corresponding core compensation power supply according to the core compensation voltage. The magnitude of the current of the core compensation power supply can be the same as the magnitude of the current of the core power supply. The feedback subunit 785 generates an interface compensation voltage by calculating the difference between VCCQ and the standard interface voltage, and then generates a corresponding interface compensation power supply according to the interface compensation voltage. The magnitude of the current of the interface compensation power supply can be the same as the magnitude of the current of the interface power supply. The standard core voltage can be a normal reference core voltage (VCC1), and the standard interface voltage can be a normal reference interface voltage (VCCQ1). By generating the compensation voltage, the actual VCC and VCCQ are adjusted to be close to the standard value to ensure the stability of the power supply voltage.

[0047] See also Figure 2 In some embodiments, the regulating subunit 786 may be a key unit in the memory 700 for compensating the core power supply and the interface power supply. Its core function is to regulate the core power supply and the interface power supply output by the sampling subunit 781 according to the core compensation power supply and the interface compensation power supply generated by the feedback subunit 785 to ensure the stability and accuracy of the power supply voltage. Through the compensation mechanism, it is ensured that the voltage of the compensated core power supply and the voltage of the compensated interface power supply are always close to the standard value to avoid system instability caused by voltage fluctuations. Among them, the main control unit 710 can set the reference core voltage to the sampling subunit 781 through the regulating subunit 786, and set the standard core voltage and the standard interface voltage to the feedback subunit 785.

[0048] See also Figure 1 and Figure 3 The present invention also provides a memory test system, which can test the memory 700 in the above embodiment, by providing interface power supplies with different voltages and core power supplies with different voltages to the memory 700, so as to determine whether the memory 700 can work normally. The test system may include a processing module 100, a memory module 200, a storage module 300, a power module 400, a power management module 500, an interface module 600, etc.

[0049] See also Figure 3 In some embodiments, the processing module 100 may be a central processing unit. The central processing unit (CPU) may be responsible for interpreting and executing instructions in a program, controlling and processing data. The processing module 100 may be a multi-core processor, each core of which may process different data read and write requests in parallel, thereby increasing the parallelism of tasks. The processing module 100 may be used to generate and send voltage regulation instructions, and monitor the working status of the memory 700. See also Figure 3 In some embodiments, the memory module 200 may be a dynamic random access memory (DRAM). The memory module 200 may be used to store data and program codes so that the processing module 100 can quickly access them.

[0050] See also Figure 3 In some embodiments, the storage module 300 may be a memory card (Secure Digital, SD). The SD card may be used to store an operating system and software programs required for operation.

[0051] See also Figure 3In some embodiments, the power module 400 (POWER) can supply power to the processing module 100, the memory module 200, the storage module 300, the power management module 500, etc. to complete the test.

[0052] See also Figure 3 In some embodiments, the power management module 500 (Power Management Integrated Circuit, PMIC) can be used to output interface power supply and core power supply of different voltages to the memory 700 according to the voltage control instruction to meet the power supply requirements during testing. Specifically, the power management module 500 can be used to parse the voltage control instruction to clarify the size of VCC and VCCQ to be output. Subsequently, the internal voltage regulator (such as a DC-DC converter or LDO) of the power management module 500 generates VCC and VCCQ that meet the requirements.

[0053] See also Figure 3 In some embodiments, the interface module 600 may be a Universal Asynchronous Receiver / Transmitter (UART). The memory 700 may communicate with the peripheral device via serial communication with the interface module 600 to exchange data.

[0054] In some embodiments, after outputting interface power supplies and core power supplies of different voltages to the memory 700, the processing module 100 is also used to determine whether the judgment subunit 782 can generate corresponding compensation instructions, interrupt instructions, and power-off instructions after receiving interface power supplies and core power supplies of different voltages, so as to evaluate the working state of the judgment subunit 782 and provide a basis for the optimization of the adjustment unit 780. When the judgment subunit 782 generates the corresponding instruction, it is determined that the judgment subunit 782 can work normally. When the judgment subunit 782 does not generate the corresponding instruction, it is determined that the judgment subunit 782 is abnormal. When the judgment subunit 782 is abnormal, it means that there may be problems with the voltage abnormality processing design process of the adjustment unit 780, and optimization processing is required, such as improving the voltage judgment logic, adding a fault tolerance mechanism, etc.

[0055] In some embodiments, the processing module 100 can be used to determine whether the feedback subunit 785 and the adjustment subunit 786 perform a voltage compensation operation after receiving a compensation instruction, thereby evaluating the working status of the two subunits. When the feedback subunit 785 and the adjustment subunit 786 perform a voltage compensation operation, it is determined that the two subunits can work normally. When the feedback subunit 785 and the adjustment subunit 786 do not perform a voltage compensation operation, it is determined that the two subunits have an abnormality. The purpose of the voltage compensation operation is to compensate the interface power supply and / or the core power supply until the memory exits the undervoltage mode. When the feedback subunit 785 and the adjustment subunit 786 are abnormal, it means that there may be problems with the voltage abnormality processing design process of the adjustment unit 780, and optimization processing is required, such as improving the voltage compensation logic, adding a fault tolerance mechanism, etc.

[0056] In some embodiments, the processing module 100 is also used to monitor the main control unit 710 and determine whether the main control unit 710 performs a data backup operation after receiving an interrupt instruction: when performing a data backup operation, it is determined that the firmware of the memory 700 can work normally; when not performing a data backup operation, it is determined that there is an abnormality in the firmware of the memory 700. When the firmware does not perform a data backup operation, it means that the processing strategy of the firmware is inconsistent and the error cannot be detected, indicating that there is a defect in the firmware processing flow. For defects in the firmware, the defects in the processing flow can be repaired by updating the firmware.

[0057] In some embodiments, the processing module 100 is also used to determine whether the main control unit 710 performs a shutdown operation after receiving a power-off instruction: when the shutdown operation is performed, it is determined that the firmware of the memory 700 can work normally; when the shutdown operation is not performed, it is determined that there is an abnormality in the firmware of the memory 700. When the firmware does not perform the shutdown operation, it means that the processing strategy of the firmware is inconsistent and the error cannot be detected, indicating that there is a defect in the firmware processing flow. For the defects of the firmware, the defects in the processing flow can be repaired by updating the firmware.

[0058] See also Figure 4 , in some embodiments, Figure 4 It shows that at different times, the core power supply outputs different voltages to the memory 700, where the horizontal axis is time and the vertical axis is voltage. At T1, T3, and T9, the voltage (VCC) of the core power supply is lower than the interrupt reference core voltage (VCC3), and at this time, the memory 700 can be considered to be in power-off mode. Subsequently, the memory 700 can be tested by the processing module 100 to determine whether the memory 700 can perform a shutdown operation.

[0059] See also Figure 4In some embodiments, at time T7, the voltage of the core power supply (VCC) is between the undervoltage reference core voltage (VCC2) and the interrupt reference core voltage (VCC3), and the memory 700 is considered to be in a low power consumption mode. Subsequently, the processing module 100 can test the memory 700 to determine whether the memory 700 can perform a data backup operation.

[0060] See also Figure 4 In some embodiments, at times T2, T5, T8, and T10, the voltage (VCC) of the core power supply is between the normal reference core voltage (VCC1) and the undervoltage reference core voltage (VCC2), and the memory 700 is considered to be in undervoltage mode. Subsequently, the memory 700 can be tested by the processing module 100 to determine whether the memory 700 can perform the voltage compensation operation.

[0061] See also Figure 5 , in some embodiments, Figure 5 The voltage (VCCQ) of the interface power supply with different voltages output to the memory 700 at different times is shown, wherein the horizontal axis is time and the vertical axis is voltage (Voltage). At times T3, T5, and T9, the voltage (VCCQ) of the interface power supply is lower than the interrupt reference interface voltage (VCCQ3), and at this time, the memory 700 can be considered to be in power-off mode. Subsequently, the memory 700 can be tested by the processing module 100 to determine whether the memory 700 can perform a shutdown operation.

[0062] See also Figure 5 In some embodiments, at time T1 and T2, the voltage (VCCQ) of the interface power supply is between the undervoltage reference interface voltage (VCCQ2) and the interruption reference interface voltage (VCCQ3), and the memory 700 can be considered to be in a low power consumption mode. Subsequently, the memory 700 can be tested by the processing module 100 to determine whether the memory 700 can perform a data backup operation.

[0063] See also Figure 5 In some embodiments, at time T4 and T7, the voltage of the interface power supply (VCCQ) is between the normal reference core voltage (VCC1) and the undervoltage reference core voltage (VCC2), and the memory 700 is considered to be in undervoltage mode. Subsequently, the memory 700 can be tested by the processing module 100 to determine whether the memory 700 can perform the voltage compensation operation.

[0064] See also Figure 6The present invention also provides a memory testing method, which can be applied to the above test system to test the memory 700 in the above embodiment, by providing interface power supplies with different voltages and core power supplies with different voltages to the memory 700 to determine whether the memory 700 can work normally. The testing method may include the following steps: Step S10, generating and sending a voltage control instruction; Step S20, outputting interface power supplies of different voltages and core power supplies of different voltages to the memory according to the voltage control instruction; Step S30: monitor the working status of the memory and complete the test of the memory.

[0065] It can be seen that in the above scheme, through the testing of the system and firmware in the development stage, combined with a rich VCC / VCCQ type configuration, the test coverage is significantly improved, ensuring the stable operation of the firmware in a complex terminal environment and reducing the risk of logic errors caused by voltage anomalies. According to the degree of voltage anomaly, the differentiated strategy is flexibly triggered, including voltage compensation, data backup, emergency shutdown and other operations, which not only avoids system interruption caused by over-protection, but also maximizes data security and hardware integrity.

[0066] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory, comprising a main control unit, characterized in that: The memory further comprises an adjustment unit, wherein the adjustment unit is used to receive interface power supplies of different voltages and core power supplies of different voltages provided by the outside world; The adjustment unit is further used to determine the working state of the memory according to the interface power supply and / or the core power supply; the adjustment unit and the main control unit adjust the working state of the memory according to the determination result.

2. The memory according to claim 1, characterized in that: The adjustment unit comprises: A judgment subunit, used for judging the working state of the memory according to the interface power supply and the core power supply, and generating a compensation instruction, an interrupt instruction, and a power-off instruction based on the judgment result; A feedback subunit, used for obtaining an interface compensation power supply and a core compensation power supply according to the compensation instruction; A regulating subunit, used for compensating the interface power supply according to the interface compensation power supply to obtain a compensated interface power supply; the regulating subunit is also used for compensating the core power supply according to the core compensation power supply to obtain a compensated core power supply; The output subunit is used to output the compensated interface power supply to the main control unit, and output the compensated core power supply to the flash memory unit of the memory.

3. The memory according to claim 2, characterized in that: The judgment subunit generates a compensation instruction, an interrupt instruction, and a power-off instruction according to the following steps: Determine the working state of the memory according to the interface power supply and / or the core power supply: When the memory is in the undervoltage mode, a compensation instruction is generated and sent; the feedback subunit and the adjustment subunit perform a voltage compensation operation according to the compensation instruction; the voltage compensation operation means compensating the interface power supply and / or the core power supply until the memory exits the undervoltage mode; When the memory is in a low power consumption mode, an interrupt instruction is generated and sent; the main control unit performs a data backup operation according to the interrupt instruction; the data backup operation means backing up the data in the mapping table and the cache unit, and stopping power supply to the idle modules in the memory; When the memory is in the power-off mode, a power-off instruction is generated and sent; and the main control unit performs a shutdown operation according to the power-off instruction.

4. The memory according to claim 2, characterized in that: The feedback subunit obtains the interface compensation power supply and the core compensation power supply according to the following steps: Acquiring the voltage of the interface power supply and the voltage of the core power supply according to the compensation instruction; Calculating the difference between the voltage of the interface power supply and the voltage of the standard interface power supply to obtain an interface compensation voltage, and generating a corresponding interface compensation power supply according to the interface compensation voltage; The difference between the voltage of the core power supply and the voltage of the standard core power supply is calculated to obtain a core compensation voltage, and a corresponding core compensation power supply is generated according to the core compensation voltage.

5. A memory testing system, characterized in that: The memory is the memory according to any one of claims 1 to 4, and the test system comprises: A processing module, used for generating and sending voltage regulation instructions, and monitoring the working state of the memory; The power management module is used to output interface power supplies of different voltages and core power supplies of different voltages to the memory according to the voltage control instruction.

6. The memory test system according to claim 5, characterized in that: The processing module is also used to monitor the judgment subunit to judge whether the judgment subunit generates corresponding compensation instructions, interrupt instructions, and power-off instructions after receiving interface power supplies of different voltages and core power supplies of different voltages: When the corresponding compensation instruction, the interruption instruction, and the power-off instruction are not generated, it is determined that the determination subunit is abnormal.

7. The memory test system according to claim 6, characterized in that: The processing module is further used to monitor the feedback subunit and the regulating subunit, and determine whether the feedback subunit and the regulating subunit perform a voltage compensation operation after receiving a compensation instruction: When the voltage compensation operation is not performed, determining that the feedback subunit and the regulating subunit are abnormal; The voltage compensation operation means compensating the interface power supply and / or the core power supply until the memory exits the undervoltage mode.

8. The memory test system according to claim 6, characterized in that: The processing module is also used to monitor the main control unit and determine whether the main control unit performs a data backup operation after receiving an interrupt instruction: when the data backup operation is not performed, it is determined that there is an abnormality in the firmware of the memory; the data backup operation indicates backing up the data in the mapping table and the cache unit, and stopping power supply to the idle modules in the memory.

9. The memory test system according to claim 6, characterized in that: The processing module is also used to monitor the main control unit and determine whether the main control unit performs a shutdown operation after receiving a power-off instruction: when the shutdown operation is not performed, it is determined that there is an abnormality in the firmware of the memory.

10. A memory testing method, characterized in that: The memory is the memory according to any one of claims 1 to 4, and the testing method comprises: Generate and send voltage control instructions; Outputting interface power supplies of different voltages and core power supplies of different voltages to the memory according to the voltage control instruction; Monitor the working status of the memory and complete the test of the memory.

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