Test method and test equipment for SPI NAND FLASH memory chip

Abstract

The invention provides a test method and test equipment for an SPI NAND FLASH memory chip, and the test method for the SPI NAND FLASH memory chip comprises the following steps: executing corresponding reading, writing and erasing tests on the SPI NAND FLASH memory chip according to an initial frequency according to a test instruction of reading data, writing data and erasing data input by a user; and adjusting the initial frequency according to a test result and re-executing the test. The performance of reading, writing and erasing of the NAND flash memory under different operation frequencies can be effectively tested, automation can be completely achieved, manual participation is reduced, the testing efficiency is guaranteed while the cost is reduced, and small-batch testing verification of the frequency conversion SPI NAND FLASH memory chip can be well achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of memory chip testing, and in particular to a testing method and testing equipment for a SPI NAND FLASH memory chip. Background Art

[0002] SPI NAND FLASH memory chip is a non-volatile memory widely used in storage devices, with high-speed reading and writing and large storage capacity. In order to ensure its stability and reliability, it is necessary to develop a corresponding automatic testing device to conduct comprehensive performance testing and quality control of SPI NAND FLASH memory chips during the production process to meet the use requirements under different conditions.

[0003] At present, there are some test platforms on the market that can program and read SPI NAND FLASH memory chips, and can integrate test solutions. The test solution adopts modular design, which can easily connect various types of memory and test by setting different parameters. However, the existing test equipment is usually designed for a specific type of memory, lacks compatibility and adaptability to new memories (such as SPI NAND FLASH memory chips of different technology nodes), and its flexibility is insufficient; secondly, most of the current test equipment is controlled by FPGA. Although it is suitable for high-performance application scenarios, the existing test equipment can only test fixed parameters and cannot test more dynamic parameters such as changing frequency, which limits the comprehensiveness and accuracy of the test. Summary of the invention

[0004] The purpose of the present application is to provide a test method and a test device for a SPI NAND FLASH memory chip, which can perform corresponding read and write tests on the SPI NAND FLASH memory chip at different frequencies.

[0005] In order to achieve the above object, the present application provides a test method for a SPI NAND FLASH storage chip, the key of which is to include:

[0006] According to the test instructions of reading data, writing data and erasing data input by the user, the corresponding reading, writing and erasing tests are performed on the SPINAND FLASH storage chip at the initial frequency;

[0007] The initial frequency is adjusted according to the test result and the test is performed again.

[0008] Preferably, performing corresponding read, write and erase tests on the SPI NAND FLASH storage chip at the initial frequency includes:

[0009] According to the automatic test instruction of writing data input by the user, the preset data is written into the SPI NANDFLASH storage chip at the initial frequency;

[0010] Reading the SPI NAND FLASH storage chip to obtain first read data;

[0011] Comparing the first read data with the preset data to obtain a write test result;

[0012] The adjusting the initial frequency according to the test result and re-performing the test comprises:

[0013] According to the test result that the first read data is inconsistent with the preset data, the initial frequency is adjusted and the write test is re-executed.

[0014] Preferably, performing corresponding read, write and erase tests on the SPI NAND FLASH storage chip at the initial frequency also includes:

[0015] According to the automatic test instruction of reading data input by the user, data is read from the SPI NAND FLASH storage chip at the initial frequency to obtain second reading data;

[0016] comparing the second read data with the original data to obtain a read test result;

[0017] The adjusting the initial frequency according to the test result and re-performing the test comprises:

[0018] According to the test result that the second read data is inconsistent with the original data, the initial frequency is adjusted and the read test is re-executed.

[0019] Preferably, performing corresponding read, write and erase tests on the SPI NAND FLASH storage chip at the initial frequency also includes:

[0020] According to the automatic data erasing test instruction input by the user, the SPI NAND FLASH storage chip is erased at the initial frequency;

[0021] Detecting whether there is residual data in the SPI NAND FLASH storage chip to obtain an erase test result;

[0022] The adjusting the initial frequency according to the test result and re-performing the test comprises:

[0023] According to the test result of residual data existing in the SPI NAND FLASH storage chip, the initial frequency is adjusted, and the initial frequency is adjusted and the erase test is performed again.

[0024] Preferably, before executing all the steps, it also includes:

[0025] Establish communication with multi-channel SPI NAND FLASH storage chip.

[0026] Preferably, the multi-channel includes a first channel, a second channel, and a third channel, each channel is correspondingly provided with a plurality of SPI NAND FLASH storage chips, and the performing corresponding read, write and erase tests on the SPI NAND FLASH storage chips at the initial frequency includes:

[0027] The multiple flash memories of the first channel are tested at a first initial frequency; the multiple flash memories of the second channel are tested at a second initial frequency; and the multiple flash memories of the third channel are tested at a third initial frequency.

[0028] Preferably, the aforementioned method may further include:

[0029] When the ambient temperature changes, the initial frequency is adjusted according to a preset linear relationship between temperature and frequency; and

[0030] When the voltage at the communication interface changes, the initial frequency is adjusted according to a preset linear relationship between voltage and frequency.

[0031] Preferably, it also includes:

[0032] Analyzing the write test results, the read test results and / or the erase test results to obtain a performance evaluation result;

[0033] Generate a test report based on the performance evaluation results;

[0034] The test report is uploaded to the cloud server.

[0035] Preferably, performing corresponding read, write and erase tests on the SPI NAND FLASH storage chip at the initial frequency includes:

[0036] Obtaining read, write and erase frequency thresholds of the SPI NAND FLASH memory chip according to the model information of the SPI NAND FLASH memory chip;

[0037] The initial frequency is set according to the threshold.

[0038] The embodiment of the present application also provides a SPI NAND FLASH memory chip testing device, the key of which is that it includes:

[0039] One or more MCU control units and memory;

[0040] The memory is coupled to the one or more MCU control units, and the memory is used to store computer program codes, wherein the computer program codes include computer instructions, and the one or more MCU control units call the computer instructions to enable the test device to execute the aforementioned method.

[0041] This application tests the SPI NAND FLASH memory chip by setting the initial frequency, and then adjusts the test frequency according to the test results until the SPI NAND FLASH memory chip works normally at a certain frequency. It can effectively test the performance of NAND flash memory in terms of reading, writing, erasing, etc. at different frequencies, and can also be fully automated, reducing manual participation, ensuring test efficiency while reducing costs, and can well realize small-batch test verification of variable-frequency SPI NAND FLASH memory chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a flow chart of a method for testing a SPI NAND FLASH memory chip in one embodiment of the present application;

[0043] Figure 2 This is a flow chart of testing the data writing frequency of a SPI NAND FLASH storage chip in one embodiment of the present application;

[0044] Figure 3 This is a flow chart of testing the data reading frequency of the SPI NAND FLASH storage chip in one embodiment of the present application;

[0045] Figure 4 This is a flow chart of testing the data erasing frequency of a SPI NAND FLASH storage chip in one embodiment of the present application;

[0046] Figure 5 This is a flow chart of a method for processing test results in one embodiment of the present application;

[0047] Figure 6 Schematic diagram of the structure of a SPI NAND FLASH memory chip testing device in one embodiment of the present application. DETAILED DESCRIPTION

[0048] It is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0050] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0051] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0052] The principle of the present application is that a test instruction is input through an automatic test device, and the SPI NAND FLASH memory chip is first tested for reading, writing and erasing at an initial frequency. When the SPI NAND FLASH memory chip cannot work at the current frequency, the software program in the automatic test device automatically adjusts the frequency test until the SPI NAND FLASH memory chip works normally at a certain frequency. This frequency is used as the standard for application frequency in some special scenarios, thereby realizing automatic frequency testing of the SPINAND FLASH memory chip.

[0053] The present application provides a method for testing a SPI NAND FLASH memory chip. Figure 1 In one embodiment, the testing method comprises:

[0054] Step S10, according to the test instructions for reading data, writing data and erasing data input by the user, corresponding read, write and erase tests are performed on the SPI NAND FLASH storage chip at the initial frequency; in the embodiment of the present application, the initial frequency can be set to the highest frequency (for example, 133MHz), or the test frequency range of the SPI NAND FLASH storage chip can be obtained according to the model of the SPI NAND FLASH storage chip to determine the initial frequency. After the user inputs the test instructions for reading data, writing data and erasing data, the corresponding read, write and erase tests are performed on the SPI NAND FLASH storage chip according to the initial frequency.

[0055] Step S20, adjusting the initial frequency according to the test result and re-performing the test. In this embodiment, the initial frequency can be lowered or increased according to the test result of the failed test until the SPI NAND FLASH storage chip works normally at a certain frequency. For example, if during the test process of reading data, the test result is that the SPI NAND FLASH storage chip fails the test, the initial frequency is lowered and the reading test is performed again until the chip passes the test. At this time, the lowered frequency can be used as a standard for the application frequency of some special scenarios.

[0056] In a preferred embodiment, in the aforementioned step S20, the initial frequency may be adjusted according to a preset frequency interval, for example, the initial frequency may be gradually reduced or adjusted at intervals of 1 MHz or lower.

[0057] In the embodiment of the present application, the SPI NAND FLASH memory chip is tested by setting the initial frequency, and then the test frequency is adjusted according to the test results. The performance of the NAND flash memory in terms of reading, writing, erasing, etc. at different frequencies can be effectively tested. It can also be fully automated, reducing manual participation, ensuring test efficiency while reducing costs, and can well realize small-batch test verification of variable-frequency SPI NAND FLASH memory chips.

[0058] As mentioned above, the embodiment of the present application can automatically perform corresponding read, write and erase tests on the SPI NAND FLASH storage chip. Figure 2 As shown, in a preferred embodiment, the process of testing the frequency of writing data includes:

[0059] Step S11, according to the automatic data writing test instruction input by the user, the preset data is written into the SPINAND FLASH storage chip at the initial frequency;

[0060] Step S12, reading the SPI NAND FLASH storage chip to obtain first read data;

[0061] Step S13, compare the first read data with the preset data to obtain a write test result. In the embodiment of the present application, after the test device receives the write data automatic test instruction, it can automatically test the write function of the SPI NAND FLASH. According to the write data automatic test instruction, the test device extracts the pre-stored preset data from the local, and then writes the preset data into the SPI NAND FLASH. After the writing is completed, the test device will read the SPI NAND FLASH to obtain the first read data.

[0062] After the test device obtains the first read data, it will judge the first read data. The test device judges whether the first read data is consistent with the preset data. Since the first read data is obtained based on the preset data written into the SPI NAND FLASH; if there is no problem in the process of writing the preset data into the SPI NAND FLASH, then the first read data should be consistent with the preset data.

[0063] If the test device determines that the first read data is consistent with the preset data, it can be said that there is no problem in writing the preset data into the SPI NAND FLASH, indicating that there is no problem with the write function of the SPI NAND FLASH; the test device can determine that the write function of the SPI NAND FLASH passes the write test.

[0064] If the test device determines that the first read data is inconsistent with the preset data, it can be explained that there is a problem in the process of writing the preset data into the SPI NAND FLASH, indicating that there is a problem with the write function of the SPI NAND FLASH; the test device can determine that the write function of the SPI NAND FLASH has failed the write test.

[0065] If the test equipment determines that the write function of the SPI NAND FLASH fails the write test, the write test result can be determined based on the write function of the SPI NAND FLASH failing the write test. The test result at this time can indicate that there is a problem with the write function of the SPI NAND FLASH. If the test equipment determines that the write function of the SPI NAND FLASH passes the write test, the write test result can be determined based on the write function of the SPI NAND FLASH passing the write test. The test result at this time can indicate that there is no problem with the write function of the SPI NAND FLASH.

[0066] In the embodiment of the present application, the aforementioned step S20 includes:

[0067] According to the test result that the first read data is inconsistent with the preset data, the initial frequency is adjusted and the write test is performed again. When the test result shows that there is a problem with the write function of the SPI NAND FLASH, the initial frequency can be reduced and the write data operation can be performed again until the SPI NAND FLASH storage chip works normally at a certain frequency.

[0068] The above steps are merely exemplary and the process may be reversed. For example, an initial frequency at which the test can pass is preset, and the frequency is continuously increased based on this frequency until the write function fails the test. At this time, the frequency is used as the application frequency standard.

[0069] Figure 3 The flow chart of testing the frequency of reading data of the SPI NAND FLASH storage chip in one embodiment of the present application is shown. Figure 3 As shown, in a preferred embodiment, the process of testing the data reading frequency of the SPI NAND FLASH storage chip may include:

[0070] Step S101, according to the automatic data reading test instruction input by the user, reading data from the SPI NAND FLASH storage chip at an initial frequency to obtain second read data;

[0071] Step S102: Compare the second read data with the original data to obtain a read test result.

[0072] In this embodiment, the aforementioned step S20 may include:

[0073] If the test result of the second read data is inconsistent with the original data, the initial frequency is adjusted and the read test is performed again.

[0074] This embodiment discloses a process of reading data and testing the reading frequency, which is substantially the same as the process and principle of the data writing test and will not be described in detail herein.

[0075] Figure 4 The figure shows the process of testing the data erasing frequency of the SPI NAND FLASH storage chip in one embodiment of the present application. Figure 4 As shown, in a preferred embodiment, the process of testing the data reading frequency of the SPI NAND FLASH storage chip may include:

[0076] Step S110, erasing the SPI NANDFLASH storage chip at an initial frequency according to the automatic data erasing test instruction input by the user;

[0077] Step S120, detecting whether there is residual data in the SPI NAND FLASH storage chip to obtain an erase test result;

[0078] In this embodiment, the aforementioned S20 may include:

[0079] According to the test result of residual data existing in the SPI NAND FLASH storage chip, the initial frequency is adjusted, and the initial frequency is adjusted and the erase test is performed again.

[0080] This embodiment discloses a process of erasing data and testing the erasure frequency, which is substantially the same as the process and principle of the aforementioned data writing and reading test, and is not described in detail herein.

[0081] In the embodiment of the present application, a multi-channel test can be designed to implement parallel testing of multiple SPI NAND flash memories, and the test channel can be dynamically selected according to the demand to reduce the test time. For example, in a preferred embodiment, before executing all steps, it can also include:

[0082] Establish communication with a multi-channel SPI NAND FLASH memory chip. In an embodiment of the present application, the multi-channel includes a first channel, a second channel, and a third channel, and each channel is provided with a plurality of SPI NAND FLASH memory chips. The aforementioned step S20 may further include: performing a test on the plurality of flash memories of the first channel at a first initial frequency; performing a test on the plurality of flash memories of the second channel at a second initial frequency; performing a test on the plurality of flash memories of the third channel at a third initial frequency. The present invention establishes SPI protocol communication with a multi-channel SPI NAND FLASH memory chip, and through the automatic test instructions input by the user, the SPI NAND FLASH memory chip can be automatically tested to obtain the test results, so that during the test of the SPI NAND FLASH memory chip, the user only needs to input the automatic test instructions, and the test equipment can automatically complete the test and obtain the test results, thereby reducing manual operations and improving the degree of automation of the test. In particular, since communication with multi-channel SPI NAND FLASH storage chips is established, different customer demand tests can be achieved when executing multiple parallel tests. For example, n flash memories of channel A are tested at frequency A, n flash memories of channel B are tested at frequency B, n flash memories of channel C are tested at frequency C, and so on, thereby meeting different user needs.

[0083] Furthermore, in the aforementioned method steps, an adaptive algorithm can be introduced to ensure the accuracy of the test. For example, the test frequency can be adjusted in real time according to the performance of the SPI NAND FLASH storage chip being tested to optimize the test process. For example, in a preferred embodiment, the aforementioned method can also include:

[0084] When the ambient temperature changes, the initial frequency is adjusted according to a preset linear relationship between temperature and frequency; and,

[0085] When the voltage at the communication interface changes, the initial frequency is adjusted according to a preset linear relationship between voltage and frequency.

[0086] Those skilled in the art know that frequent reading, writing or erasing may change the temperature or interface voltage of the memory chip. In this embodiment, the linear relationship between the temperature and frequency of the SPI NAND FLASH memory chip can be preset in the software, and then the initial frequency can be adjusted according to the measured ambient temperature. For example, when the chip temperature rises and the ambient temperature is also at a high value, a frequency change compensation value can be set to reduce the original frequency interval (for example, from 1MHz to 0.8 or 0.5MHz), thereby optimizing the test process. The linear relationship between the interface voltage and frequency of the SPI NAND FLASH memory chip can also be preset in the software, and then the initial frequency can be adjusted according to the measured interface voltage, thereby optimizing the test process.

[0087] In the embodiment of the present application, since an independent MCU is provided, the test results can be further processed. Figure 5 As shown, in a preferred embodiment, the method flow for processing the test results may include:

[0088] Step S30, analyzing the write test result, the read test result and / or the erase test result to obtain a performance evaluation result;

[0089] Step S40, generating a test report according to the performance evaluation result;

[0090] Step S50, uploading the test report to the cloud server. In the embodiment of the present application, the test equipment can use an independent MCU to connect to SPI, and the MCU can transmit data to the host computer and computer via USB at high speed to process the test results of the current frequency and quickly switch the frequency. After obtaining the test results, the test equipment can also analyze the test results through the MCU to obtain the performance test report of the chip at different frequencies, and the MCU uploads the test report to the cloud server for data storage, sharing and analysis.

[0091] In the embodiment of the present application, the initial frequency can be preset by the user, and the user preset can refer to the factory setting frequency of the SPI NAND FLASH memory chip, or it can be automatically obtained by the device. For example, in a preferred embodiment, the factory setting frequency of the SPI NAND FLASH memory chip can be obtained according to the following steps:

[0092] Obtain the read, write and erase frequency thresholds of the SPI NAND FLASH storage chip according to the model information of the SPI NAND FLASH storage chip;

[0093] The initial frequency is set according to a threshold.

[0094] The present application also provides a SPI NAND FLASH memory chip test device for implementing the above method flow, referring to Figure 6 In a preferred embodiment, the test equipment of the SPI NAND FLASH storage chip may include:

[0095] MCU control unit 10: responsible for the control and data processing of the entire test process. Specifically, the MCU model STM32H750VBT6 can be used. This application uses MCU to control the frequency conversion operation of SPI NAND FLASH reading and writing, etc., which is easy to implement, highly integrated, and occupies a small space, which is convenient for small batch verification.

[0096] SPI test interface 20: SPI and QSPI interfaces can be set to establish communication with the SPI NAND FLASH memory chip. The embodiment of the present application is compatible with two transmission interface bandwidths and supports x1, x2, x4 bit widths and frequency tests above 100 MHz.

[0097] Data acquisition and analysis module 30: collects real-time test data and sends the results to the MCU control unit for the MCU to control frequency adjustment; in the embodiment of the present application, a high-speed data acquisition and analysis module can be used to capture data in real time during the test, and analyze it in real time through a high-performance processor to reduce data processing delays.

[0098] Frequency adjustment module 40: realizes the frequency conversion function, which is realized by adjusting the clock frequency inside the MCU. In the embodiment of the present application, the frequency adjustment module can support the testing of different frequencies of the SPI NAND FLASH storage chip through a programmable clock generation circuit. Due to the use of a programmable clock generation circuit, the frequency can be adjusted in real time according to specific needs to meet the requirements of NAND with different specifications.

[0099] In the embodiment of the present application, the frequency adjustment module is controlled by the MCU control unit 10. For example, after the MCU control unit 10 receives the test results sent by the data acquisition and analysis module 30, it sends instructions to the frequency adjustment module 40 according to the test results. The frequency adjustment module 40 adjusts the initial frequency. The MCU control unit 10 sends a test instruction to notify the relevant test unit to perform the test again according to the adjusted frequency.

[0100] In the embodiment of the present application, the MCU control unit 10 may include a user interface 11 and a data processing module 12, the user interface 11 is used to set the input test instructions and display the test results, and the data processing module 12 is used to process all data.

[0101] From the above, it can be seen that this application uses automated testing software, combined with hardware circuits, to achieve comprehensive reading, writing, erasing and other operations at different frequencies. It can be compatible with SPI NAND FLASH memory chips of different specifications, and can realize frequency change testing of SPI NAND FLASH memory chips. It also reduces manual intervention and improves test efficiency.

[0102] The embodiment of the present application also provides a SPI NAND FLASH memory chip test system, which includes the above-mentioned SPI NAND FLASH memory chip test device. In addition to the above-mentioned test equipment, the test system may also include: a network interface, a user interface, a memory and a communication bus. Among them, the communication bus is used to realize the connection and communication between these components. The user interface may include a display (Display), an input unit, such as a keyboard (Keyboard), and the optional user interface may also include a standard wired interface and a wireless interface. The network interface may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory may be a high-speed RAM memory, or a stable memory (non-volatile memory), such as a disk memory.

[0103] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A method for testing a SPI NAND FLASH memory chip, characterized in that: include: According to the test instructions of reading data, writing data and erasing data input by the user, the corresponding reading, writing and erasing tests are performed on the SPI NANDFLASH storage chip at the initial frequency; The initial frequency is adjusted according to the test result and the test is performed again.

2. The method for testing the SPI NAND FLASH memory chip according to claim 1, wherein: The performing of corresponding read, write and erase tests on the SPI NAND FLASH storage chip according to the initial frequency includes: According to the automatic test instruction of writing data input by the user, the preset data is written into the SPI NAND FLASH storage chip at the initial frequency; Reading the SPI NAND FLASH storage chip to obtain first read data; Comparing the first read data with the preset data to obtain a write test result; The adjusting the initial frequency according to the test result and re-performing the test comprises: According to the test result that the first read data is inconsistent with the preset data, the initial frequency is adjusted and the write test is re-executed.

3. The method for testing the SPI NAND FLASH memory chip according to claim 2, wherein: The performing corresponding read, write and erase tests on the SPI NAND FLASH storage chip at the initial frequency also includes: According to the automatic test instruction of reading data input by the user, data is read from the SPI NAND FLASH storage chip at the initial frequency to obtain second reading data; comparing the second read data with the original data to obtain a read test result; According to the test result that the second read data is inconsistent with the original data, the initial frequency is adjusted and the read test is re-executed.

4. The method for testing the SPI NAND FLASH memory chip according to claim 3, wherein: The performing corresponding read, write and erase tests on the SPI NAND FLASH storage chip at the initial frequency also includes: According to the automatic data erasing test instruction input by the user, the SPI NAND FLASH storage chip is erased at the initial frequency; Detecting whether there is residual data in the SPI NAND FLASH storage chip to obtain an erase test result; According to the test result of residual data existing in the SPI NAND FLASH storage chip, the initial frequency is adjusted, and the initial frequency is adjusted and the erase test is performed again.

5. The method for testing the SPI NAND FLASH memory chip according to any one of claims 1 to 4, characterized in that: Also before executing all steps: Establish communication with multi-channel SPI NAND FLASH storage chip.

6. The method for testing the SPI NAND FLASH memory chip according to claim 5, characterized in that: The multi-channel includes a first channel, a second channel, and a third channel, each channel is correspondingly provided with a plurality of SPI NAND FLASH storage chips, and the corresponding reading, writing and erasing tests are performed on the SPI NAND FLASH storage chips according to the initial frequency, including: The multiple flash memories of the first channel are tested at a first initial frequency; the multiple flash memories of the second channel are tested at a second initial frequency; and the multiple flash memories of the third channel are tested at a third initial frequency.

7. The method for testing the SPI NAND FLASH memory chip according to claim 6, wherein: Also includes: When the ambient temperature changes, the initial frequency is adjusted according to the preset linear relationship between temperature and frequency; as well as When the communication interface voltage changes, the initial frequency is adjusted according to a preset linear relationship between voltage and frequency.

8. The method for testing the SPI NAND FLASH memory chip according to claim 7, characterized in that: Also includes: Analyzing the write test results, the read test results and / or the erase test results to obtain a performance evaluation result; Generate a test report based on the performance evaluation results; The test report is uploaded to the cloud server.

9. The method for testing the SPI NAND FLASH memory chip according to claim 5, characterized in that: The performing of corresponding read, write and erase tests on the SPI NAND FLASH storage chip according to the initial frequency includes: Obtaining read, write and erase frequency thresholds of the SPI NAND FLASH memory chip according to the model information of the SPI NAND FLASH memory chip; The initial frequency is set according to the threshold.

10. A test device for SPI NAND FLASH storage chip, characterized in that: include: One or more MCU control units and memory; The memory is coupled to the one or more MCU control units, and the memory is used to store computer program code, wherein the computer program code includes computer instructions, and the one or more MCU control units call the computer instructions to enable the test device to perform the method as described in any one of claims 1 to 9.

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