Testability design test method and circuit based on delay line

Abstract

The invention discloses a testability design test method and circuit based on a delay line. The method comprises the following steps: acquiring a test point arranged at the input end of the delay line and an observation point arranged at the output end of the delay line; inserting a first control logic designed based on the test point and a second control logic designed based on the observation point into a preset testability design test so as to obtain a test vector according to the testability design test; and testing the delay line based on the test vector to obtain a test result which is used for representing the damage condition of the delay line. According to the technical scheme, the operation process of the delay line test can be simplified through the automatic control logic, so that the test of the delay line is more convenient and easier to operate, and the labor cost is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of chip circuit design, and in particular to a delay line-based design for testability test method and circuit. Background Art

[0002] DDR (Double Data Rate) PHY (physical interface) adjusts the delay line at the transmitting end so that DRAM (dynamic random-access memory) particles can smoothly sample control signals and data signals at the receiving end. Correspondingly, at the DDR PHY end, by adjusting the delay line at the internal receiving end, the DDR PHY can smoothly sample the output signal of the DRAM particles.

[0003] DFT (Design for Testability) is used to test chip quality to see if there are any chip damage problems during the production process due to the physical manufacturing process.

[0004] Generally, a DFT test is performed on the delay line to determine whether the chip is damaged based on the test results. However, the conventional delay line testing process is cumbersome and has high labor costs. Summary of the invention

[0005] In order to solve the above technical problems, an embodiment of the present application provides a delay line-based design for testability test method and circuit.

[0006] According to one aspect of an embodiment of the present application, a delay line-based design for testability test method is provided, the method comprising: obtaining a test point arranged at an input end and an observation point arranged at an output end of the delay line; inserting a first control logic designed based on the test point and a second control logic designed based on the observation point into a preset design for testability test to obtain a test vector according to the design for testability test; testing the delay line based on the test vector to obtain a test result, and the test result is used to characterize the damage of the delay line.

[0007] In some embodiments of the present application, based on the above technical solution, the test vector includes a test stimulus and an expected result, and the delay line is tested based on the test vector to obtain a test result, including: inputting the test stimulus into the delay line so that the delay line outputs a stimulus result according to the test stimulus; comparing the stimulus result with the expected result to obtain a damage condition of the delay line according to the comparison result.

[0008] In some embodiments of the present application, based on the above technical solution, the test stimulus is input into the delay line so that the delay line outputs a stimulus result according to the test stimulus, including: matching the test stimulus with the clock signal of the test point to obtain a test clock for characterizing the test stimulus; and inputting the test clock corresponding to the test stimulus into the delay line so that the delay line outputs a stimulus result according to the test clock.

[0009] In some embodiments of the present application, based on the above technical solution, there are multiple test points, and the excitation result is compared with the expected result to obtain the damage condition of the delay line according to the comparison result, including: obtaining the comparison results of the excitation results corresponding to all test points on the delay line with the expected results; if the comparison results of the excitation results corresponding to all test points with the expected results are all normal, then the test result that the delay line is not damaged is obtained; if at least one of the comparison results of the excitation results corresponding to all test points with the expected results is abnormal, then the test result that the delay line is damaged is obtained.

[0010] In some embodiments of the present application, based on the above technical solution, the method further includes: When the test vector is obtained according to the DFT test, the coverage of the test points on the delay line is generated according to the test content of the DFT test, and the number of the test points is increased when the coverage is less than a preset threshold.

[0011] In some embodiments of the present application, based on the above technical solution, there are multiple test points, and the method includes: judging whether the first control logic of all test points and the second control logic of all observation points are inserted successfully according to the coverage rate; if not, reinserting the first control logic of the test points and the second control logic of the observation points until the first control logic of all test points and the second control logic of all observation points are inserted successfully.

[0012] In some embodiments of the present application, based on the above technical solution, the method further includes: obtaining a selection signal on the test point; when the selection signal is a design for testability test mode, performing a design for testability test on the corresponding test point.

[0013] According to one aspect of an embodiment of the present application, a delay line-based testability design test circuit is provided, including: a delay line, used to delay the transmission time of an electrical signal; a test point, provided at the input end of the delay line, used to test whether the delay line is damaged; and an observation point, provided at the output end of the delay line, used to obtain a test result of whether the delay line is damaged.

[0014] In some embodiments of the present application, based on the above technical solution, the test point includes: a test data selector, the output of the test data selector is connected to the input of the delay line; a first trigger, the output of the first trigger is connected to the input of the test data selector; wherein the input of the test data selector is respectively used to obtain the selection signal on the test point, the preset input clock signal and the output signal of the first trigger; the input of the first trigger is respectively used to obtain the ground signal and the test clock signal of the test point.

[0015] In some embodiments of the present application, based on the above technical solution, the observation point includes: a second trigger, the input end of the second trigger is connected to the output end of the delay line; wherein the input end of the second trigger is used to obtain the test clock signal of the test point and the output signal of the delay line respectively.

[0016] In the technical solution of the embodiment of the present application, the above invention content can at least bring the following beneficial effects: The technical solution of the present application inserts the test vector generation process into the logic program of the testability design test to improve the consistency of test vector generation and use through an automated control process. Based on the automated control logic of the delay line damage test, the operational process of the delay line damage test is simplified, making the delay line damage test more convenient and easy to operate, thereby reducing labor costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 The block diagram of the overall circuit of a level converter is shown in an exemplary embodiment of the present application.

[0018] Figure 2 The schematic diagram of the structure of the testability design test circuit of the delay line is shown for the exemplary embodiment of the present application.

[0019] Figure 3 The flowchart of the delay line-based design for testability test method is shown for an exemplary embodiment of the present application.

[0020] Figure 4 The flowchart is a flow chart showing a method for detecting a delay line damage condition according to an exemplary embodiment of the present application.

[0021] Figure 5A flowchart of the process of obtaining incentive results is shown for an exemplary embodiment of the present application.

[0022] Figure 6 The following is a flowchart showing a method for detecting a delay line damage according to another exemplary embodiment of the present application.

[0023] Figure 7 A flowchart of inserting a first control logic and a second control logic into a design for testability test is shown for an exemplary embodiment of the present application.

[0024] Figure 8 A flow chart showing a delay line detection process according to an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] In order to make the purpose and implementation method of the present application clearer, the exemplary implementation method of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0026] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0027] The terms "first", "second", "third", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances.

[0028] The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to all the components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0029] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0030] In the chip production process of the prior art, due to the physical manufacturing process, some physical damage may be caused to the chip. In order to test whether the chip has similar damage during the production process, the prior art tests the produced chips through the DFT test method. The main purpose of the DFT test is to provide an effective method to detect and diagnose faults in integrated circuits to ensure the normal operation and reliability of the circuit. By considering the test needs in the design stage and taking corresponding measures, it is possible to ensure that the circuit is tested with high quality during the manufacturing process, thereby improving the quality and competitiveness of the product and reducing some unnecessary cost losses in the chip production process.

[0031] For example, the DFT test principle can mainly include the following aspects: Insertion of test points: A certain number of test points are reasonably placed in the circuit design so that the circuit can be fully covered during the test process. The insertion of test points needs to be determined according to the circuit structure and design requirements to maximize the coverage and efficiency of the test. This process often requires some experienced staff to set it based on experience.

[0032] Test vector generation: Based on the location of the test points and the functional requirements of the circuit, a series of test data that can effectively detect circuit faults is generated. These test vectors are used to simulate various situations in the actual working environment in order to detect the response and performance of the circuit under various conditions.

[0033] Application of test sequence: The generated test vectors are applied to the circuit in a certain order and timing to trigger possible faults and detect and diagnose the location and type of faults. The application of test sequence needs to take into account the clock frequency and data transmission speed of the circuit to ensure the correctness and stability of the test.

[0034] Design of fault models: Design corresponding fault models for various possible fault modes. These models are used to simulate fault conditions so that faults can be accurately detected and located during testing.

[0035] Based on the above content, the present application designs a delay line-based testability design test circuit, which may include: Delay lines, used to delay the transmission time of electrical signals; A test point is set at the input end of the delay line to test whether the delay line is damaged; The observation point is set at the output end of the delay line and is used to obtain the test result of whether the delay line is damaged.

[0036] The delay line may be an electronic component or device, the main function of which is to delay an electrical signal or an optical signal for a period of time.

[0037] Specifically, the delay line plays a vital role in the DDR memory interface. The delay line of DDR PHY is a physical structure used to adjust the signal transmission delay, which is usually located inside the DDR PHY (physical layer). The main function of the delay line is to ensure that the clock signal and the data signal can maintain the correct timing relationship during the transmission process, so as to achieve accurate data sampling and transmission.

[0038] Figure 1 The structural relationship diagram of the delay line on the DDR PHY shown in the exemplary embodiment of the present application is as follows: Figure 1 As shown, delay lines are respectively arranged on the interface between the dynamic random access memory (DRAM) and the DDR PHY to ensure that the clock signal and the data signal can maintain a correct timing relationship during the transmission process.

[0039] In the DDR memory interface, data is sampled and transmitted by the clock edge. DDR PHY ensures accurate data transmission by providing alignment of the clock signal and the data signal. To achieve this goal, DDR PHY synchronizes according to the edges of the clock signal and the data signal sent by the controller. When the clock edge arrives, DDR PHY uses the delay line to adjust the transmission delay of the data signal so that it maintains the correct phase relationship with the clock signal, and then samples the data signal and transmits it to the memory.

[0040] Figure 2 The schematic diagram of the structure of the testability design test circuit of the delay line is shown in the exemplary embodiment of the present application. Figure 2 As shown, in the testability design test circuit of the delay line of the present application, the delay line may include multiple delay units and multiple data selectors, the multiple delay units are arranged in series, and each data selector is connected to the input end of the delay unit, so that the multiple delay units are arranged in a one-to-one correspondence with the multiple data selectors, so that the working state of the delay unit can be determined by the data selector. For example, the delay control is performed by the number of selections of the data selector.

[0041] The present application sets a test point at the input end of the delay line to test whether the delay line is damaged during the physical manufacturing process, and obtains the test result of whether the delay line is damaged through the observation point at the output end of the delay line.

[0042] In some embodiments of the present application, based on the above embodiments, the above test points may at least include: A test data selector, wherein an output end of the test data selector is connected to an input end of the delay line; A first trigger, an output terminal of the first trigger being connected to an input terminal of the test data selector; Wherein, the input end of the test data selector is used to obtain the selection signal on the test point, the preset input clock signal and the output signal of the first trigger respectively; The input end of the first trigger is used to obtain a ground signal and a test clock signal of a test point respectively.

[0043] Among them, the test data selector includes three input interfaces and one output interface. The first input interface of the test data selector is used to obtain the input clock signal, the second input interface of the test data selector is used to obtain the output signal of the first trigger, and the third input interface of the test data selector is used to obtain the selection signal on the test point.

[0044] Based on this, the test data selector determines whether the output end of the test data selector outputs the input clock signal or the output signal of the first trigger according to the selection signal input from the third input interface.

[0045] A test clock signal is input into the first trigger, wherein the test clock signal can be used as a test clock signal of a test point, so that the first trigger inputs an output signal of the first trigger into a second input interface of the test data selector according to the test stimulus.

[0046] The first trigger of the present application may select a DFF (bistable trigger), so that the first trigger can store the level state of the test clock signal and maintain the state at the output end until the next trigger signal is received.

[0047] In some embodiments of the present application, based on the above embodiments, the above observation points may at least include: a second flip-flop, wherein an input terminal of the second flip-flop is connected to an output terminal of the delay line; The input end of the second trigger is used to obtain the test clock signal of the test point and the output signal of the delay line respectively.

[0048] Specifically, the second trigger of the present application may also select DFF (bistable trigger), so that the second trigger can change the trigger state according to the output signal of the delay line, thereby realizing the signal detection function according to the rising edge or falling edge state of the second trigger.

[0049] This application also designs a testability design test method based on delay line. Figure 3 The flowchart of the testability design test method based on the delay line is shown as an exemplary embodiment of the present application. Figure 3 As shown, the test method includes at least the following execution steps: S300, obtaining a test point at an input end and an observation point at an output end of the delay line; S310, inserting the first control logic designed based on the test point and the second control logic designed based on the observation point into a preset design for testability test to obtain a test vector according to the design for testability test; S320 , testing the delay line based on the test vector to obtain a test result, where the test result is used to characterize damage of the delay line.

[0050] The specific content of the first control logic is to control the input signals of different inputs of the electronic components in the test point in the preset program of the testability design test so as to perform the test of the test point according to the corresponding input signals. For example, if the third input port of the control test data selector is input with an input signal used to represent the execution of the delay line test, the output end of the control test data selector outputs the signal of the output end of the first trigger.

[0051] The specific content of the second control logic is similar to that of the first control logic. In the preset program of the testability design test, the input signals of different inputs of the electronic components in the observation point are controlled to perform the test of the test point according to the corresponding input signals. As an example, the output signal of the delay line is used as an input signal of the observation point. The second control logic can be characterized as obtaining the output signal of the observation point, that is, the output signal of the second trigger, and obtaining the judgment result of whether the delay line is damaged according to the output signal of the second trigger.

[0052] After the first control logic and the second control logic are inserted into the preset testability design test, the test vector is obtained according to the specific test content, and the test content includes the setting position of the test point and the observation point, and the input and output of the electronic components, etc. For example, a DFT netlist is automatically generated according to the test content, and the back-end layout is performed, and a communication connection with the DFT tool is established in the program, and the layout content is input into the preset DFT tool, for example: the DFT tool can be mentor (Mentor Graphics), and the coverage report of the test vector and the test point is calculated according to the DFT tool, and the coverage report of the test vector and the test point is returned to the program through the communication connection.

[0053] Further, the delay line is tested according to the test vector returned to the program. Specifically, the test of the delay line can be performed on an ATE machine (automatic integrated circuit tester). Similar to the DFT tool, a communication connection with the ATE machine is established in the program. The delay line of the present application can obtain a test result according to the test vector, and then transmit the test result and the test vector to the ATE machine to obtain a judgment result on whether the delay line is damaged, and the judgment result is returned to the program through the communication connection.

[0054] In the above-mentioned embodiment, the technical solution of the present application inserts the test vector generation process into the logic program of the testability design test to improve the consistency of the test vector generation and use through an automated control process. Based on the automated control logic of the delay line damage test, the operation process of the delay line damage test is simplified, making the delay line damage test more convenient and easy to operate, thereby reducing labor costs.

[0055] In some embodiments of the present application, based on the above embodiments, the test vector of the present application may include test stimuli and expected results.

[0056] Figure 4 The flowchart of the exemplary embodiment of the present application shows the detection method of the delay line damage situation, such as Figure 4 As shown, testing the delay line based on the test vector to obtain a test result may at least include the following execution steps: S400, inputting a test stimulus into a delay line, so that the delay line outputs a stimulus result according to the test stimulus; S410: Compare the excitation result with the expected result to obtain the damage condition of the delay line according to the comparison result.

[0057] Specifically, the test stimulus in the test vector is input to the delay line through the ATE machine in the above embodiment, so that the stimulus signal acts on the delay line to obtain a stimulus result, and then the stimulus result is compared with the expected result in the test vector based on the ATE machine, and whether the delay line is damaged is determined according to the comparison result. Explanation is given by way of example, after the stimulus signal acts on the delay line, if the delay line is normal, the value represented by the obtained stimulus result should be equal to the expected result, and if the value represented by the obtained stimulus result is not equal to the expected result, it indicates that the delay line may be damaged.

[0058] In some embodiments of the present application, based on the above embodiments, Figure 5 The flowchart of the process of obtaining the incentive result is shown in the exemplary embodiment of the present application, as shown in FIG. Figure 5 As shown, inputting a test stimulus into a delay line so that the delay line outputs a stimulus result according to the test stimulus may at least include the following steps: S500, matching the test stimulus with the clock signal of the test point to obtain a test clock for characterizing the test stimulus; S510, inputting a test clock corresponding to the test stimulus into a delay line, so that the delay line outputs a stimulus result according to the test clock.

[0059] Specifically, Figure 2As shown in the figure, test_clk is represented as a test clock. In order to more fully disclose the test process of whether the delay line is damaged, the present application makes the following description on the representation of the test stimulus. The test stimulus of the present application can be represented by a clock signal. For example, the test stimulus itself is a voltage signal or a current signal, which is converted into a clock signal through a preset conversion module. For example, when adjusting the test stimulus signal, the corresponding clock signal is adjusted to convert the clock signal into a voltage signal or a current signal through a conversion module. Of course, this is only an exemplary description and no specific limitation is made.

[0060] In the above implementation, the purpose is to enable the test stimulus of the present application to be represented by a clock signal, so that the test clock represented by the clock signal can be more easily adjusted and controlled, thereby improving the convenience of testing whether the delay line is damaged.

[0061] In some embodiments of the present application, based on the above embodiments, Figure 6 Another exemplary embodiment of the present application is a flowchart showing a method for detecting a delay line damage condition. Figure 6 As shown, there may be multiple test points, and comparing the stimulus result with the expected result to obtain the damage of the delay line according to the comparison result may include at least the following steps: S600, obtaining comparison results between the stimulus results corresponding to all test points on the delay line and the expected results; S610, if the comparison results of the stimulus results corresponding to all the test points with the expected results are all normal, then a test result indicating that the delay line is not damaged is obtained; S620: If at least one of the comparison results between the stimulus results corresponding to all the test points and the expected results is abnormal, a test result indicating that the delay line is damaged is obtained.

[0062] Specifically, when there are multiple test points, only when the test results of all the test points are normal can it be considered that the delay line has no physical damage. If only one test point has an abnormal test result, it is considered that the delay line may have physical damage.

[0063] It should be noted that, the multiple test points may correspond to multiple different delay lines respectively, or the multiple test points may correspond to the same delay line.

[0064] In the above implementation, when there are multiple test points, by satisfying that the test results of all test points are normal, the test result of the delay line is reflected as no physical damage to the delay line, thereby improving the test accuracy of the delay line test result and reducing test errors.

[0065] In some embodiments of the present application, based on the above embodiments, the delay line-based testability design test method of the present application may at least further include the following steps: When the test vector is obtained according to the testability design test, the coverage of the test points on the delay line is generated according to the test content of the testability design test, and the number of test points is increased when the coverage is less than a preset threshold.

[0066] Specifically, the coverage of test points can be used to characterize the comprehensiveness of the delay line test. The more test points are distributed, the more detailed the test positions corresponding to the delay line are, and the higher the accuracy of the test results is. However, in order to improve production efficiency to a certain extent, this application controls the coverage of test points by setting a threshold.

[0067] In some embodiments of the present application, based on the above embodiments, Figure 7 The flowchart of inserting the first control logic and the second control logic into the design for testability test is shown in the exemplary embodiment of the present application. Figure 7 As shown, when there are multiple test points, the delay line-based testability design test method of the present application may at least include the following steps: S700, judging whether the first control logic of all test points and the second control logic of all observation points are inserted successfully according to the coverage rate; S710: If no, reinsert the first control logic of the test point and the second control logic of the observation point until the first control logic of all test points and the second control logic of all observation points are successfully inserted.

[0068] Specifically, after determining multiple test points, the ratio of the set test points to the points of all test points that can be set can be calculated. When the ratio is different from the coverage of the test points on the delay line generated according to the test content of the testability design test, it means that the first control logic of all test points and the second control logic of all observation points have not been successfully inserted. The first control logic of all test points and the second control logic of all observation points can be reinserted through the program preset in this application, thereby improving the reliability of the test results.

[0069] In some embodiments of the present application, based on the above embodiments, Figure 8 A flowchart of a delay line detection process is shown for an exemplary embodiment of the present application, such as Figure 8 As shown, the delay line-based testability design test method of the present application may at least include the following steps: S800, obtaining a selection signal on a test point; S810: When the selection signal is in the design for testability test mode, a design for testability test is performed on the corresponding test point.

[0070] Specifically, Figure 2 As shown in the figure, test_mode is represented as a selection signal corresponding to the mode. The present application improves the fluency of the delay line damage test by inserting the first control logic of the test point on the delay line and the second control logic of the observation point into the preset testability design test.

[0071] By way of example, when the delay line is in normal use, a selection signal for selecting a mode set on a test point is adjusted so that the test point exits the test mode to ensure normal use of the delay line.

[0072] For another example, during the production process of the delay line corresponding module, it is necessary to detect whether the delay line is normal. At this time, the selection signal for selecting the mode set on the test point is adjusted so that the test point enters the test mode to detect the delay line.

[0073] For another example, after the corresponding module of the delay line has been used for a period of time, certain faults occur in the corresponding module, and it is necessary to detect whether the delay line is normal in order to troubleshoot the fault. At this time, the selection signal for selecting the mode set on the test point is adjusted so that the test point enters the test mode to detect the delay line.

[0074] Based on this, in the above implementation, the setting of the selection signal at the test point can improve the convenience of detecting whether the delay line is damaged.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0076] For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A test method for design for testability based on a delay line, characterized in that: The method comprises: Acquiring a test point at an input end and an observation point at an output end of the delay line; Inserting the first control logic designed based on the test point and the second control logic designed based on the observation point into a preset design for testability test to obtain a test vector according to the design for testability test; The delay line is tested based on the test vector to obtain a test result, where the test result is used to characterize a damage condition of the delay line.

2. The delay line-based design for testability test method according to claim 1, characterized in that: The test vector includes a test stimulus and an expected result, and the delay line is tested based on the test vector to obtain a test result, including: Inputting the test stimulus into the delay line so that the delay line outputs a stimulus result according to the test stimulus; The excitation result is compared with the expected result to obtain the damage condition of the delay line according to the comparison result.

3. The delay line-based design for testability test method according to claim 2, characterized in that: The step of inputting the test stimulus into the delay line so that the delay line outputs a stimulus result according to the test stimulus comprises: Matching the test stimulus with a clock signal of the test point to obtain a test clock for characterizing the test stimulus; A test clock corresponding to the test stimulus is input into the delay line, so that the delay line outputs a stimulus result according to the test clock.

4. The delay line-based design for testability test method according to claim 2, characterized in that: There are multiple test points, and comparing the excitation result with the expected result to obtain the damage condition of the delay line according to the comparison result includes: Obtaining comparison results between the stimulus results corresponding to all test points on the delay line and the expected results; If the comparison results of the stimulus results corresponding to all the test points with the expected results are all normal, then a test result indicating that the delay line is not damaged is obtained; If at least one of the comparison results of the stimulus results corresponding to all the test points with the expected results is abnormal, then the test result indicating that the delay line is damaged is obtained.

5. The delay line-based design for testability test method according to claim 1, characterized in that: The method further comprises: When the test vector is obtained according to the DFT test, the coverage of the test points on the delay line is generated according to the test content of the DFT test, and the number of the test points is increased when the coverage is less than a preset threshold.

6. The delay line-based design for testability test method according to claim 5, characterized in that: There are multiple test points, and the method includes: Determine whether the first control logic of all test points and the second control logic of all observation points are inserted successfully according to the coverage rate; If not, the first control logic of the test point and the second control logic of the observation point are reinserted until the first control logic of all the test points and the second control logic of all the observation points are successfully inserted.

7. The delay line-based design for testability test method according to claim 1, characterized in that: The method further comprises: Acquiring a selection signal on the test point; When the selection signal is in the design for testability test mode, a design for testability test is performed on the corresponding test point.

8. A delay line-based design for testability test circuit, used to implement the delay line-based design for testability test method according to any one of claims 1 to 5, characterized in that: include: Delay lines, used to delay the transmission time of electrical signals; A test point, provided at the input end of the delay line, for testing whether the delay line is damaged; An observation point is provided at the output end of the delay line and is used to obtain a test result of whether the delay line is damaged.

9. The delay line-based design for testability test circuit according to claim 8, characterized in that: The test points include: a test data selector, wherein an output end of the test data selector is connected to an input end of the delay line; a first trigger, wherein an output terminal of the first trigger is connected to an input terminal of the test data selector; Wherein, the input end of the test data selector is used to obtain the selection signal on the test point, the preset input clock signal and the output signal of the first trigger respectively; The input end of the first trigger is used to obtain a ground signal and a test clock signal of the test point respectively.

10. The delay line-based design for testability test circuit according to claim 8, characterized in that: The observation points include: a second trigger, wherein an input terminal of the second trigger is connected to an output terminal of the delay line; The input end of the second trigger is used to obtain the test clock signal of the test point and the output signal of the delay line respectively.

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