Chip packaging system and electronic equipment

Abstract

The embodiment of the invention discloses a chip packaging system and electronic equipment. The chip packaging system comprises a PCB, a local interconnection component and a plurality of core particles, the local interconnection component is arranged on a board of the PCB, and each core particle is electrically interconnected with the PCB; the local interconnection component comprises a dielectric layer and a high-density interconnection circuit layer which are arranged in a stacked mode, and at least two core particles are electrically interconnected through the local high-density interconnection circuit. Thus, the core particles and the local interconnection parts are installed on the PCB to form a chip board-level system, and the installability, reliability and supptability of the system are effectively improved while the high-density layout requirement is met. Meanwhile, on the basis of the structural characteristic that the core particles are installed on the surface of the PCB through the local interconnection components, link loss caused by conventional packaging can be reduced, and system cost can be reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip packaging technology, and in particular to a chip packaging system and electronic equipment. Background Art

[0002] As the difficulty of transistor process miniaturization increases and the demand for high-performance chips continues to rise, the industry has begun to explore solutions in the field of packaging. In traditional chip-level systems, the die is packaged on a substrate to form a chip package, which is then installed on a PCB (Printed Circuit Board). Among them, FCBGA (Flip chip BGA) technology has been widely used for its high integration, high performance, and low power consumption.

[0003] In order to meet the requirements of high-density layout, a typical FCBGA packaging architecture arranges a silicon interposer based on RDL (Re-distributed layer) between the die and the substrate to achieve small-pitch placement of the die, effectively improving bandwidth performance. With the integration of more chips, the size of FCBGA is getting larger and larger, and there are development bottlenecks in terms of installability, reliability and supplyability. Summary of the invention

[0004] The embodiments of the present application provide a locally high-density chip packaging system and electronic equipment, which effectively improve the installability, reliability and supplyability of the system while meeting the high-density layout requirements.

[0005] A first aspect of an embodiment of the present application provides a chip packaging system, which includes a PCB, a local interconnection component and a plurality of core particles, wherein the local interconnection component and the plurality of core particles are arranged on the PCB, and the plurality of core particles are electrically interconnected with the PCB respectively; the local interconnection component includes a stacked dielectric layer and a high-density interconnection circuit layer, and at least two core particles are electrically interconnected through the local interconnection component.

[0006] In this way, the core particles are mounted on the PCB, and the electrical interconnection between the core particles is achieved through the local interconnection component, forming a chip board-level system. In a specific implementation, the local interconnection component monomer can be tested and integrated with the PCB while ensuring that its function is intact; at the same time, the local interconnection component monomer is small in size and has good installability, so that the manufacturing yield of the chip system is guaranteed, thereby reducing the manufacturing cost.

[0007] In addition, the size of the electrical interconnection between the core particles and local interconnection components and the PCB is small. Under the same power consumption, the application of this solution can effectively reduce the possibility of thermal deformation of the interconnection area, and the system service time can be reasonably improved, with higher reliability.

[0008] In addition, a high-density layout of more cores can be achieved according to functional requirements. The construction of the chip packaging system is not affected by the difficulty of implementing large-size substrates and has good supplyability.

[0009] Exemplarily, the local interconnection component may be provided as one or more. In practical applications, in the case where multiple local interconnection components are provided on one side of the PCB, the multiple local interconnection components may be arranged at intervals on the PCB.

[0010] Based on the first aspect, the embodiment of the present application also provides a first implementation of the first aspect: the PCB also includes a build-up layer, which is arranged at the periphery of the local interconnection component, and the surface of the build-up layer is provided with an interface pad electrically interconnected with the core particle. In practical applications, the build-up layer material can be provided with a window capable of accommodating the local interconnection component, and a blind hole for external interconnection, etc., and an interface pad between the core particle and the local interconnection component is provided on the surface of the build-up layer, so that the core particle maintains a stable posture during the assembly process.

[0011] Exemplarily, the material of the build-up layer may be an organic material, such as ABF.

[0012] Based on the first implementation of the first aspect, the embodiment of the present application also provides a second implementation of the first aspect: the local interconnection component includes a first surface and a second surface, wherein the first surface of the local interconnection component is arranged relative to the PCB, and the second surface of the local interconnection component is arranged relative to the core particle; the interface pad located on the surface of the build-up layer includes a first pad and a second pad, the first pad is electrically connected to the pin on the first surface of the local interconnection component, and the second pad is electrically connected to the core particle interface pad on the surface of the PCB. Such a configuration effectively improves the operability of the core particle upper board assembly while having the characteristics of simple structure and good processability.

[0013] In practical applications, the structural form and board layout of the first pad and the second pad can be determined according to the local interconnection component and the external interface form of the core particle.

[0014] Based on the first implementation of the first aspect, or the second implementation of the first aspect, the embodiment of the present application also provides a third implementation of the first aspect: the interface pad on the surface of the build-up layer includes a first pad and a second pad, which can be electrically connected to the local interconnection component and the PCB through the stacked through holes on the build-up layer. Based on the structural characteristics that the local interconnection component is directly set on the PCB board surface, the determination of the build-up layer thickness only needs to meet the forming conditions corresponding to the first pad of the local interconnection component. In this way, by reasonably controlling the thickness of the build-up layer, a layer of stacked through holes is set thereon to achieve electrical connection between the core particle and the local interconnection component, which has better processability.

[0015] Based on the first aspect, the embodiment of the present application further provides a fourth implementation of the first aspect: the PCB further includes a column, which is disposed on the PCB beside the local interconnection component, and the column extends toward the core connected to the local interconnection component, and the end face of the column is connected to the core. Thus, mechanical support and external electrical interconnection are provided by arranging the column, thereby improving the reliability of core assembly.

[0016] Based on the fourth implementation of the first aspect, the embodiment of the present application further provides a fifth implementation of the first aspect: the local interconnection component includes a first surface and a second surface, wherein the first surface of the local interconnection component is arranged relative to the PCB, and the second surface of the local interconnection component is arranged relative to the core particle; the end surface of the column connected to the core particle is flush with the interconnection pad on the first surface of the local interconnection component. In this way, based on the fact that the column can level the height difference of the pads of the core particle pins, the installation area of ​​the core particle is roughly a plane, which can further improve the reliability of the core particle assembly.

[0017] Based on the fourth implementation of the first aspect, or the fifth implementation of the first aspect, the embodiment of the present application also provides a sixth implementation of the first aspect: the column is a conductive column, and the column is electrically connected to the core particle interface pad on the PCB to construct an electrical interconnection between the core particle connected to the local interconnection component and the PCB. In other words, the column can be a conductive column configured on the pad on the surface of the PCB. In this way, on the basis of providing auxiliary mechanical support, it also has an electrical connection function.

[0018] In practical applications, the conductive column can be made of metal material; for example, the column can be a copper column electrically connected to the core particle interface pad on the PCB, which has good electrical conductivity and can quickly conduct heat from the board side based on the good thermal conductivity of the copper column, and has a heat dissipation function. In this way, when the core particles are assembled on the board, the two core particles to be connected are welded to the interconnection pads on the first side of the local interconnection component, and electrical interconnection is achieved through the high-density interconnection circuit layer of the local interconnection component; the core particles are also welded to the conductive column to achieve electrical interconnection between the core particles and. Overall, the system integration can be further improved.

[0019] In other exemplary embodiments, the conductive column is made of non-metallic material and copper is plated on the surface of the column, which can also have the functions of support and electrical connection.

[0020] Based on the sixth implementation of the first aspect, the embodiment of the present application also provides a seventh implementation of the first aspect: the local interconnection component and the column are plastic-encapsulated to form a plastic-encapsulated body located on the PCB board surface, and the end face of the column and the interconnection pads on the first face of the local interconnection component are exposed on the surface of the plastic-encapsulated body. In this way, the plastic-encapsulated body is formed in a local position area of ​​the PCB board surface, which can further improve the reliability of the core particle assembly, and the process implementation cost is low.

[0021] For example, EMC materials can be used for plastic encapsulation. In practical applications, the plastic encapsulation material covering the local interconnection components and the top of the pillars can be removed, for example, a grinding process can be used to expose the conductive pillars and the interconnection pads of the local interconnection components to the plastic encapsulation body to establish a reliable electrical connection.

[0022] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, or the fifth implementation of the first aspect, or the sixth implementation of the first aspect, or the seventh implementation of the first aspect, the embodiment of the present application also provides an eighth implementation of the first aspect: the local interconnection component is a double-sided interconnection structure, and the pins on the second side of the local interconnection component are electrically connected to the interconnection component interface pads on the board surface of the PCB. In practical applications, the double-sided interconnection local interconnection component can be flexibly configured according to the system function design.

[0023] Exemplarily, after performing the flux cleaning operation, the bottom filling process can be used to protect the solder joints between the local interconnection component and the PCB, and then the core particles can be assembled. In addition, exemplarily, in the case of setting a conductive column, the flux cleaning can be performed as a whole after all the core particles are assembled, and the bottom filling process can be used to protect the solder joints between the local interconnection component and the PCB, as well as the solder joints between the core particles and the PCB. Based on the structural characteristics of the local interconnection component being directly arranged on the PCB board surface, it is convenient to perform cleaning and bottom filling operations, which can effectively ensure the installability and reliability of the downward interconnection of the local interconnection component.

[0024] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, or the fifth implementation of the first aspect, or the sixth implementation of the first aspect, or the seventh implementation of the first aspect, or the eighth implementation of the first aspect, the embodiment of the present application also provides a ninth implementation of the first aspect: the local interconnection component is a single-sided interconnection structure, and the second side of the local interconnection component is glued and fixed to the board surface of the PCB. The local interconnection component with single-sided interconnection can be flexibly configured according to the system function design, and is easy to implement in process.

[0025] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, or the eighth embodiment of the first aspect, or the ninth embodiment of the first aspect, the embodiments of the present application also provide a tenth embodiment of the first aspect: the dielectric layer can be made of organic material or inorganic material.

[0026] In practical applications, for local interconnect components whose dielectric layer is made of organic materials, the dielectric layer material of the local interconnect component has a similar thermal expansion capacity as the substrate of the PCB, which can prevent the deformation of the two after being heated and generate mechanical stress at the joint. Accordingly, the substrate of the PCB can be a BT board, and the dielectric layer 21 can be made of PI, PP or ABF.

[0027] In other practical applications, for the local interconnection components using inorganic materials for the dielectric layer, accordingly, the substrate of the PCB can be a ceramic plate, a glass plate or a metal plate, and the dielectric layer can be made of SiO2.

[0028] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, or the fifth implementation of the first aspect, or the sixth implementation of the first aspect, or the seventh implementation of the first aspect, or the eighth implementation of the first aspect, or the ninth implementation of the first aspect, or the tenth implementation of the first aspect, the embodiment of the present application also provides an eleventh implementation of the first aspect: the chip packaging system also includes other functional devices arranged on the PCB. In practical applications, the other functional devices arranged on the PCB may include at least one of a power supply module, a connector, and a capacitor.

[0029] Based on the eleventh implementation of the first aspect, the embodiment of the present application also provides a twelfth implementation of the first aspect: the other functional devices and the core particle are located on the same side of the PCB, or the other functional devices are located on the PCB on the opposite side of the core particle.

[0030] Exemplarily, for the power supply module, the core particle is located on one side of the PCB, and the power supply module is located on the other side of the PCB, and is located on the PCB opposite to the core particle, thereby forming a vertical power supply board-level architecture with low power loss and high integration. In other exemplary embodiments, the power supply module and the core particle can also be located on the same side of the PCB to form a horizontal power supply board-level architecture.

[0031] In another exemplary embodiment, for the connector, the connector and the core particle can be located on the same side panel, the link length can be reasonably controlled, and the link loss between the connector and the core particle can be reduced.

[0032] The second aspect of the embodiment of the present application provides an electronic device, which includes a mainboard and a chip packaging system as described above, and the chip packaging system is arranged on the mainboard. Exemplarily, the chip packaging system can be a functional component such as a CPU, GPU, ASIC, SOC, etc. configured in the electronic device.

[0033] In practical applications, the electronic device may be a server, a computer or a high-performance computing cluster. In addition, the electronic device may also be a switch, a router, an indoor baseband processing unit or an edge device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the architecture of a chip board-level system provided in an embodiment of the present application;

[0035] Figure 2 for Figure 1 Schematic diagram of the assembly relationship between the local interconnect components and the PCB shown in;

[0036] Figure 3 A schematic diagram of the structure of a local interconnection component provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of the structure of another local interconnection component provided in an embodiment of the present application;

[0038] Figure 5 for Figure 1 A schematic diagram of the assembly process of the local interconnect components and shown in FIG;

[0039] Figure 6 A schematic diagram of the assembly relationship between another local interconnect component and a PCB provided in an embodiment of the present application;

[0040] Figure 7 for Figure 6 A schematic diagram of the assembly process of the local interconnect components and shown in FIG;

[0041] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The embodiment of the present application provides an implementation scheme for a chip board-level system architecture, which effectively takes into account high-density layout requirements while improving installability, reliability, and supplyability.

[0043] In scenarios with high-density layout and high integration, flip chips are used in medium and high-performance products. Taking the typical FCBGA packaging architecture as an example, the line width capability of the substrate is usually around 15um. In order to improve the architectural layout density, the architecture is arranged with a silicon interposer between the core particles and the substrate. The RDL line width capability formed on the silicon wafer can reach 1um, which is much smaller than the line width made on the resin substrate, and can achieve small-pitch placement of core particles. The FCBGA package body is mounted on the PCB board to form a chip-level system that can meet the established functions. With the improvement of product performance, the number of core particles integrated on the FCBGA packaging architecture has increased accordingly, resulting in an increase in the size of the FCBGA, and a development bottleneck has emerged in terms of installability, reliability, and supplyability.

[0044] Based on this, the embodiment of the present application provides a chip board-level system, including a PCB, a local interconnection component and a plurality of core particles, the local interconnection component and the plurality of core particles are arranged on the PCB, and the plurality of core particles are electrically interconnected with the PCB respectively. Among them, the local interconnection component includes a dielectric layer arranged in a stacked manner and a high-density interconnection circuit layer arranged in the dielectric layer, and the at least two core particles are electrically interconnected through the high-density interconnection circuit layer of the local interconnection component. In this way, the core particles are directly installed on the PCB, and the electrical interconnection between the core particles is realized through the local interconnection component to form a chip board-level system, and the core particles and the local interconnection component are both installed with the PCB, and the size of the single body is relatively small. Compared with the FCBGA packaging architecture and the way of realizing chip assembly with PCB, this solution can effectively reduce the installation difficulty caused by the warping of large-size FCBGA, has good installability, so that the manufacturing yield of the chip system is guaranteed, thereby reducing the manufacturing cost. At the same time, the size of the electrical interconnection between the core particles and the local interconnection component and the PCB is small. Under the same power consumption, the application of this solution can effectively reduce the possibility of heat deformation of the interconnection area, and has high reliability.

[0045] In addition, based on the structural characteristics of the core particles being directly installed on the PCB surface through local interconnect components, it is possible to avoid link loss and cost caused by reducing packaging. In practical applications, a high-density layout of more core particles can be achieved according to functional needs, which is not affected by the difficulty of implementing large-size substrates and has good supplyability. In addition, the installation of local interconnect components on the PCB surface facilitates the coupling process between the local interconnect components and the PCB, which can further improve installability.

[0046] In order to better understand the technical solution and technical effects of the present application, without losing generality, the specific embodiments will be described in detail below in conjunction with the accompanying drawings. Figure 1 , which is a schematic diagram of the architecture of a chip board-level system provided in an embodiment of the present application.

[0047] like Figure 1 As shown, the PCB 1 of the chip board-level system 100 is provided with a local interconnect component 2, a plurality of core particles 3, a connector 4 and a power supply module 5. Each core particle 3 can be electrically interconnected with the PCB 1, for example but not limited to, and can be used to realize power supply, communication (data signal and / or control signal) transmission, etc. In this embodiment, the core particle 3 is located on one side of the PCB 1, and the power supply module 5 is located on the other side of the PCB 1, forming a vertical power supply board-level architecture with low power loss and high integration. In other possible implementation schemes, the power supply module 5 can also be located on the same side of the PCB 1 as the core particle 3, forming a horizontal power supply board-level architecture.

[0048] Exemplarily, in this embodiment, at least four local interconnect components 2 are arranged on one side of the PCB 1, and two adjacent core particles 3 can be coupled to the PCB 1 through the local interconnect components 2, and the electrical interconnection between the two adjacent core particles 3 is realized based on the local interconnect components 2, for example, but not limited to, for high-performance data transmission between core particles. It should be understood that in other possible implementation schemes, the number of local interconnect components 2 can be determined according to the functional requirements of the system, for example, one or a plurality of other local interconnect components can be set; for the case where multiple local interconnect components are arranged on one side of the PCB 1, each local interconnect component can be arranged at intervals. In addition, for multiple core particles on the upper board, some of the core particles can be electrically interconnected based on the local interconnect components 2, and the other part of the core particles can be directly electrically connected to the PCB 1. It can be determined specifically according to the overall design of the product, and the embodiment of the present application is not limited.

[0049] The local interconnection component 2 is arranged on the board surface of the PCB 1, and its structure can be a mixed structure of a dielectric and a redistribution layer, that is, a high-density interconnection circuit layer is constructed by a redistribution layer. For example, but not limited to, the local interconnection component 2 can be a structure formed by alternating a layer of dielectric and a layer of metal (such as copper). The local interconnection component 2 can realize electrical interconnection between two adjacent core particles 3, and can also realize electrical interconnection between two adjacent core particles 3 in a group of core particles.

[0050] The connector 4, the local interconnection component 2, and the plurality of core particles 3 are located on the same side of the PCB 1, and are used to connect to other external devices (not shown in the figure). The connector 4 and the core particles 3 are located on the same side, and the link length can be reasonably controlled, which can reduce the link loss between the connector and the core particles. For the connector 4 installed on the PCB 1, its structural form and number of settings can be configured according to the board-level system function to achieve electrical interconnection between the external device and the PCB 1 side to meet the needs of electrical interaction.

[0051] In addition, as an optional configuration structure, the connector 4 can also be located on the other side of the PCB 1 away from the local interconnection component 2 and the core particle 3, rather than being limited to being located on the same side of the PCB 1 as the local interconnection component 2 and the core particle 3. This embodiment of the application is not limited.

[0052] In addition to the power supply module 5 and the connector 4, other functional components may be provided on the PCB 1 of the chip-board-level system 100. Optionally, a passive device 6 may be provided on the other side of the PCB 1. The passive device 6 is also the passive device of the chip-board-level system, which may be a capacitor, a resistor or an inductor, for example but not limited to Figure 1 In a specific implementation, the configuration of the passive device 6 can be determined according to the circuit design of the chip board level system.

[0053] For the chip board-level system architecture, each core particle 3 can be the same type of core particles or different types of core particles to achieve different functional configurations. In a specific implementation, at least part of the multiple core particles 3 are memory core particles, which can be determined according to the overall design requirements of the specific application scenario to implement data read and write operations; for example, but not limited to, CPU (Central Processing Unit), GPU (Graphic Processing Unit), ASIC (Application Specific Integrated Circuit), SOC (System onChip) and other integrated circuit components. This application embodiment is not limited.

[0054] In order to improve the reliability of chip assembly, further, for the local interconnection components 2 arranged on the board surface of the PCB 1, the chip board-level system 100 provided in this embodiment provides basic support and external electrical interconnection through a buildup layer (buildup) 7. Please refer to Figure 1 and Figure 2 ,in, Figure 2 for Figure 1 Schematic diagram of the assembly relationship between local interconnect components and PCB shown in.

[0055] like Figure 2 As shown, a build-up layer 7 is provided on the PCB 1 substrate at the periphery of the local interconnection component 2, and the core particle 3 can be assembled and fixed through the build-up layer 7. The build-up layer 7 material is provided with a window capable of accommodating the local interconnection component 2, and a blind hole for external interconnection, etc., and an interface pad between the core particle and the local interconnection component 2 and the PCB 1 is provided on the surface of the build-up layer 7, so that the core particle 3 maintains a stable posture during the assembly process.

[0056] Among them, for the electrical connection between the local interconnection component 2 and the core grain 3, a first pad 71 electrically connected to the pin of the local interconnection component 2 can be provided on the surface of the build-up layer 7, and the first pad 71 can be interconnected with the PCB1 side through the corresponding first blind hole 73; for the electrical connection between the PCB 1 and the core grain 3, a second pad 72 electrically connected to the core grain interface pad 12 on the surface of the PCB 1 can be provided on the surface of the build-up layer 7, and the second pad 72 can be interconnected with the PCB1 side through the corresponding second blind hole 74. In this way, when the core grain 3 is assembled on the board, the two core grains 3 to be connected are welded to the corresponding first pads 71 ​​on the surface of the build-up layer 7, and the electrical interconnection is achieved through the high-density interconnection circuit layer of the local interconnection component 2; the core grain 3 is also welded to the corresponding second pads 72 on the surface of the build-up layer 7 to achieve the electrical interconnection between the core grain and the PCB.

[0057] Based on the structural characteristics that the local interconnection component 2 is directly arranged on the PCB 1, the thickness of the build-up layer 7 only needs to meet the forming conditions corresponding to the first pad 71 of the local interconnection component 2. In this way, by reasonably controlling the thickness of the build-up layer 7, a layer of stacked through holes is arranged thereon to achieve electrical connection between the core particle and the local interconnection component 2. Compared with the implementation method of making a groove on the PCB and placing the local interconnection component in the groove, and then providing an electrical interface through the build-up layer (not shown in the figure), in which at least two layers of stacked holes are required to establish an electrical connection between the core particle and the PCB, the application of this solution only requires processing one layer of stacked through holes on the build-up layer 7, which has better processability.

[0058] In a possible implementation, the structural form and board layout of the first pad 71 and the second pad 72 can be determined according to the local interconnect component 2 and the external interface form of the core particle. This embodiment of the application is not limited.

[0059] Alternatively, Figure 2 As shown, the local interconnect component 2 can be a double-sided interconnect structure, the pins for electrically connecting with the core particle 3 are located on the first side (top side) of the local interconnect component 2, and the pins for electrically connecting with the PCB 1 are located on the second side (bottom side) of the local interconnect component 2. The surface layer of the PCB 1 also includes an interconnect component interface pad 11, and the pins on the second side of the local interconnect component 2 are welded to the interconnect component interface pad 11 to meet system requirements.

[0060] For the local interconnection component 2 interconnected on both sides, an underfill process can be used to protect the solder joints between the pins on the second side of the local interconnection component 2 and the interconnection component interface pad 11. Specifically, the liquid underfill material is injected or sprayed around the local interconnection component 2, and penetrates between the local interconnection component 2 and the PCB 1 using the capillary flow principle, and is heated and cured. Based on the structural feature that the local interconnection component 2 is directly set on the board surface of the PCB 1, the underfill process is easy to implement, providing technical guarantee for the welding reliability of the local interconnection component 2.

[0061] In other possible implementations, the liquid underfill may also be replaced by NCF (Non-Conductive Adhesive Film), which can also achieve the function of reliably fixing the local interconnection component 2 .

[0062] See also Figure 3 , which is a structural schematic diagram of a local interconnection component provided in an embodiment of the present application. Figure 3 The local interconnect component 2 shown is a double-sided interconnect structure, and the local interconnect component 2 includes a dielectric layer 21 and a high-density interconnect circuit layer 22 disposed in the dielectric layer 21. In a specific implementation, the high-density interconnect circuit layer 22 may be an RDL redistribution layer.

[0063] An interconnect pad 221 is provided on the first surface 211 of the local interconnect component 2, which serves as a pin for electrically connecting the local interconnect component 2 to the core particle 3. For a scenario where a layer is required to be added, the interconnect pad 221 is connected by Figure 2 The first blind hole 73 and the surface interface pad 71 shown in the figure are connected to the core pin. For the implementation method of connecting with PCB 1 by welding process, a metal bump (BUMP) 222 can be made on the second surface 212 of the local interconnection component 2 to serve as a pin for electrically connecting the local interconnection component 2 with PCB 1. Of course, for other interconnection methods, the pin electrically connected to PCB 1 can be formed by making a pad pattern.

[0064] In other possible implementations, according to system requirements, the local interconnect component 2 may be configured to be interconnected with the chip only upward, that is, a single-sided interconnect structure.

[0065] See also Figure 4 , which is a schematic diagram of the structure of another local interconnection component provided in an embodiment of the present application. Figure 4The local interconnection component 2 shown in the figure is a single-sided interconnection structure, and an interconnection pad 221 is provided on the first side 211 of the local interconnection component 2, which serves as a pin for electrically connecting the local interconnection component 2 with the core particle 3, and is fixed to the board surface of the PCB 1 through the second side 212 of the local interconnection component 2. In a specific implementation, the local interconnection component 2 of the single-sided interconnection structure can be fixed on the board surface of the PCB 1 by using a conventional bonding process.

[0066] For the dielectric layer 21 of the local interconnection component 2, in a possible implementation, the dielectric layer 21 can be made of organic material. In this way, for the PCB 1 using an organic matrix, the dielectric layer material of the local interconnection component 2 and the substrate of the PCB 1 have similar thermal expansion capabilities, which can prevent the two from deforming after being heated and generating mechanical stress at the joint. For example but not limited to, the substrate of the PCB 1 can be a BT (Bismaleimide Triazine, BT resin) board; the dielectric layer 21 can be made of PI (polyimide, polyimide), PP (polypropylene, polypropylene) or ABF (Ajinomoto Build-up Film, Ajinomoto Build-up Film dielectric material).

[0067] In other possible implementations, the dielectric layer 21 may also be made of inorganic materials, such as but not limited to SiO2, etc. Of course, in other possible implementations, the PCB 1 may be an inorganic circuit board, and the substrate of the PCB 1 may be a ceramic board, a glass board, a metal board, etc. This is not limited in the embodiments of the present application.

[0068] Combine the following Figure 5 , a brief description Figure 1 The assembly process of the local interconnect component 2 is shown in FIG.

[0069] Step S301 , mounting the local interconnect component 2 on the board surface of the PCB 1 .

[0070] Taking the local interconnection component 2 of the double-sided interconnection structure shown in the figure as an example, the local interconnection component 2 can be bonded to the interconnection component interface pad 11 on the PCB 1 board surface by a welding process, and the local interconnection component 2 is configured in the buried bridge area of ​​the PCB 1 board surface to realize the downward interconnection of the local interconnection component 2.

[0071] In a specific implementation, after performing the flux cleaning operation, an underfill process is used to protect the solder joints between the local interconnect component 2 and the PCB 1. Based on the structural feature that the local interconnect component 2 is directly disposed on the PCB 1, it is convenient to perform cleaning and underfill operations. Thus, the installability and reliability of the downward interconnection of the local interconnect component 2 are effectively guaranteed.

[0072] Here, the local interconnection component 2 may carry a carrier, and after being welded or glued, the carrier 3a of the local interconnection component 2 may be removed, which improves operability. Of course, in other process steps, the local interconnection component 2 may not carry a carrier.

[0073] Step S302: Cover the first build-up layer 7a on the board surface of the PCB 1. The first build-up layer 7a material is provided with a window 7a1 at a position corresponding to the local interconnection component 2, and the local interconnection component 2 is placed in the window 7a1.

[0074] For example but not limited to, the material of the first build-up layer 7a may be ABF.

[0075] Step S303 , covering the second build-up layer 7 b on the first build-up layer 7 a , and forming the build-up layer 7 after hot pressing and flattening.

[0076] For example, but not limited to, the material of the second build-up layer 7b may be ABF. It is understandable that for build-up layers that require thermal compression bonding, the second build-up layer 7b is preferably made of the same material as the first build-up layer 7a to obtain better bonding strength.

[0077] During the thermal pressing process, the material of the second build-up layer 7b can completely fill the gap between the local interconnection component 2 and the opening 7a1 after being thermally melted, thereby further enhancing the assembly reliability of the local interconnection component 2.

[0078] It should be noted that a build-up layer 7 may also be provided on the other side of the PCB 1 away from the local interconnection component 2, for example but not limited to Figure 5 The process shown in step S302 and step S303 is performed to interconnect with corresponding functional devices.

[0079] Step S304, a hole is opened on the build-up layer 7 and electroplated to form a stacked through hole, and a first pad 71 and a second pad 72 are formed at corresponding positions to realize the upward interconnection and extraction of the local interconnection component 2. In this way, the first pad 71 and the second pad 72 can be roughly located in the same plane, in other words, the installation area of ​​the core particle is a plane, so that the core particle can maintain a stable posture during the assembly process.

[0080] In a specific implementation, the process of opening holes, electroplating and surface pads can be realized using existing technologies, and the embodiments of the present application are not limited thereto.

[0081] In the above-mentioned embodiment, the reliability of the core particle assembly is improved by adding layers to the PCB. In other specific implementations, the interconnection and mechanical support between the core particle and the PCB can also be provided by setting a pillar. Figure 6 , this figure is a schematic diagram of the assembly relationship between another local interconnect component and PCB provided in an embodiment of the present application.

[0082] like Figure 6 As shown, the local interconnection component 2 is arranged on the board surface of the PCB 1, and a column 8 is arranged on the PCB 1 beside the local interconnection component 2, and the end surface of the column 8 is flush with the interconnection pad 221 on the top surface of the local interconnection component 2. The "flush" here includes the situation that the end surface of the column 8 is flush with the interconnection pad 221 of the local interconnection component 2 in an ideal state, and also includes the situation that it is roughly flush due to the tolerance accumulation due to the limitation of process accuracy, as long as it can meet the needs of reliable assembly of the core particles. In other words, based on the fact that the column 8 can level the height difference of the pad of the bump of the core particle, the installation area of ​​the core particle is roughly a plane.

[0083] As shown in the figure, at least two pillars 8 are respectively arranged on both sides of the local interconnection component 2 and are respectively connected to the corresponding core particles 3. In a possible implementation scheme, the number of pillars 8 can be determined as needed, and can be arranged on the periphery of the local interconnection component 2 according to the overall design requirements of the product, rather than being limited to Figure 6 The arrangement shown in .

[0084] In order to improve the system integration, the column 8 can be a conductive column configured on the pad on the surface of the PCB 1, which can provide auxiliary mechanical support and also have an electrical connection function. The conductive column 8 can be made of a metal material, such as but not limited to a copper column; or the conductive column 8 can be made of a non-metallic material, and the surface of the column is copper-plated, which can also have both support and electrical connection functions.

[0085] Exemplarily, the pillar 8 can be a copper pillar electrically connected to the core particle interface pad 12 on the PCB 1, with good electrical conductivity, and can also have a heat dissipation function based on the good thermal conductivity of the copper pillar, and can quickly conduct heat from the board side. In this way, when the core particles 3 are assembled on the board, the two core particles 3 to be connected are welded to the interconnection pads 221 on the first side of the local interconnection component 2, and electrical interconnection is achieved through the high-density interconnection circuit layer of the local interconnection component 2; the core particles 3 are also welded to the conductive pillar 8 to achieve electrical interconnection between the core particles 3 and the PCB.

[0086] Combine the following Figure 7 , a brief description Figure 6 The assembly process of the local interconnect component 2 is shown in FIG.

[0087] Step 701 , manufacturing a copper pillar (pillar 8 ) on the chip interface pad 12 on the surface of the PCB 1 .

[0088] In a specific implementation, based on the incoming PCB material, the copper column can be formed by planting or electroplating using an existing process, which will not be described in detail here.

[0089] Step 702 , mounting the local interconnect component 2 on the board surface of the PCB 1 .

[0090] Taking the local interconnection component 2 of the double-sided interconnection structure shown in the figure as an example, the local interconnection component 2 can be configured in the buried bridge area of ​​the PCB 1 by using a welding process to achieve downward interconnection of the local interconnection component 2.

[0091] In a specific implementation, the interface pads of the interconnection components in the buried bridge area can be locally tinned, and the local interconnection components 2 are bonded to the interface pads of the interconnection components on the PCB 1 board surface by welding or other processes. After performing the flux cleaning operation, the bottom filling process can be used to protect the solder joints between the local interconnection components 2 and the PCB 1. Similarly, based on the structural characteristics that the local interconnection components 2 are directly arranged on the board surface of the PCB 1, it is convenient to perform the flux cleaning and underfill operations, thereby effectively ensuring the reliability of the downward interconnection of the local interconnection components 2.

[0092] In other possible implementation schemes, in the case of providing a conductive column 8 (for example but not limited to a copper column), all the core particles 3 can be assembled and then the flux cleaning can be performed as a whole, and then the bottom filling process can be used to protect the solder joints between the local interconnect component 2 and the PCB1, as well as the solder joints between the core particles 3 and the PCB1 (not shown in the figure).

[0093] Step 703 , plastic-encapsulate the local interconnection components 2 and the pillars 8 on the PCB 1 to form a local plastic-encapsulated body 9 .

[0094] For example but not limited to, EMC (Epoxy Molding Compound) may be used for plastic packaging.

[0095] Step 704, remove the plastic packaging material on the top of the local interconnection component 2 and the pillar 8, that is, the conductive pillar 8 and the interconnection pad 221 of the local interconnection component 2 are exposed. For example, but not limited to, a grinding process is used. This is not limited in the present embodiment.

[0096] Step 705 , forming a solder resist layer 10 on the surface of the plastic package body 9 .

[0097] Step 706 , performing pad surface treatment on the end surface of the pillar 8 and the interconnection pad 221 of the local interconnection component 2 to obtain good electrical conductivity.

[0098] For example, but not limited to, the pad surface may be processed using an ENIG (Electroless Nickel / Immersion Gold) process, which may be selected based on actual process conditions. This is not limited in the present application.

[0099] In addition to the aforementioned chip packaging system, this embodiment also provides an electronic device, see Figure 8 , which is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0100] like Figure 8 As shown, the electronic device 1000 includes a housing 300 and a mainboard 200 disposed in the housing 300, and the mainboard 200 is provided with a chip board-level system 100 as described in the above embodiment. Here, the chip board-level system 100 can be a functional component such as a CPU, a GPU, an ASIC, or a SOC.

[0101] In a specific implementation, the electronic device may be a server, a computer or a high-performance computing cluster, for example, a high-power, highly integrated, ultra-large-scale data center server; in addition, the electronic device may also be a switch, a router, an indoor baseband processing unit or an edge device, etc., which is not limited in the embodiments of the present application.

[0102] It should be understood that other functions of the electronic device are not the core invention of the present application, and those skilled in the art can implement them according to the prior art, so they will not be described in detail herein.

[0103] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A chip packaging system, characterized in that: The chip packaging system comprises a PCB, a local interconnection component and a plurality of core particles, wherein the plurality of core particles are electrically interconnected with the PCB respectively; The local interconnection component is arranged on the board surface of the PCB, and the local interconnection component includes a dielectric layer and a high-density interconnection circuit layer arranged in a stacked manner, and at least two of the core particles are electrically interconnected through the local interconnection component.

2. The chip packaging system according to claim 1, characterized in that: The PCB further comprises a build-up layer, which is arranged at the periphery of the local interconnection component, and the surface of the build-up layer is provided with an interface pad electrically interconnected with the core particle.

3. The chip packaging system according to claim 2, characterized in that: The local interconnect component comprises a first surface and a second surface, the first surface is arranged opposite to the PCB, and the second surface is arranged opposite to the core particle; The interface pad includes a first pad and a second pad, the first pad is electrically connected to the pin on the first surface of the local interconnect component, and the second pad is electrically connected to the core particle interface pad on the surface layer of the PCB.

4. The chip packaging system according to claim 2 or 3, characterized in that: The interface pads on the surface of the build-up layer are electrically connected to the local interconnect component and the PCB through stacking through holes on the build-up layer.

5. The chip packaging system according to claim 1, characterized in that: The PCB further comprises a column, which is arranged on the PCB beside the local interconnection component, and the column extends toward the core particle connected to the local interconnection component, and the end surface of the column is connected to the core particle.

6. The chip packaging system according to claim 5, characterized in that: The local interconnect component comprises a first surface and a second surface, wherein the first surface is arranged opposite to the PCB, and the second surface is arranged opposite to the core particle; the end surface of the column is flush with the interconnection pad on the first surface of the local interconnect component.

7. The chip packaging system according to claim 5 or 6, characterized in that: The column is a conductive column, and the column is electrically connected to the core particle interface pad on the PCB to establish an electrical interconnection between the core particle connected to the local interconnect component and the PCB.

8. The chip packaging system according to claim 7, characterized in that: The column is a copper column.

9. The chip packaging system according to claim 7 or 8, characterized in that: The solder joints between the core particle and the PCB and the solder joints between the local interconnection component and the PCB are both coated with bottom filling.

10. The chip packaging system according to any one of claims 7 to 9, characterized in that: The local interconnection component and the column are plastic-encapsulated to form a plastic-encapsulated body located on the PCB board surface, and the end surface of the column and the interconnection pad on the first surface of the local interconnection component are exposed on the surface of the plastic-encapsulated body.

11. The chip packaging system according to any one of claims 1 to 10, characterized in that: The local interconnection component is a double-sided interconnection structure, and the pins on the second side of the local interconnection component are electrically connected to the interconnection component interface pads on the board surface of the PCB.

12. The chip packaging system according to any one of claims 1 to 11, characterized in that: The local interconnection component is a single-sided interconnection structure, and the second side of the local interconnection component is glued and fixed to the board surface of the PCB.

13. The chip packaging system according to any one of claims 1 to 12, characterized in that: The local interconnection components are provided in plurality, and the plurality of local interconnection components are arranged on the board surface of the PCB at intervals.

14. The chip packaging system according to any one of claims 1 to 13, characterized in that: The dielectric layer is made of organic material or inorganic material.

15. The chip packaging system according to any one of claims 1 to 14, characterized in that: The substrate of the PCB may be a BT board, a ceramic board, a glass board or a metal board.

16. The chip packaging system according to any one of claims 1 to 15, characterized in that: The chip packaging system also includes other functional devices arranged on the PCB.

17. The chip packaging system according to claim 16, characterized in that: The other functional components include at least one of a power supply module, a connector and a capacitor.

18. The chip packaging system according to claim 16 or 17, characterized in that: The other functional devices and the core particle are located on the same side of the PCB, or the other functional devices are located on the side of the PCB opposite to the core particle.

19. An electronic device, characterized in that: The invention comprises a mainboard and the chip packaging system according to any one of claims 1 to 18, wherein the chip packaging system is arranged on the mainboard.

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