Measurement Structure, Monitoring Method and Semiconductor Structure for Contact / Via Etching Process

Abstract

The present invention discloses a measurement structure, a monitoring method and a semiconductor structure for a contact / via etching process, belonging to the field of semiconductors. The measurement structure includes: a first test pad, including an etch stop layer and a contact hole / via dielectric layer, wherein the first test pad is provided with a first contact / via array; and a second test pad, including a monitoring dielectric layer, an etch stop layer and a contact hole / via dielectric layer, wherein the second test pad is provided with a second contact / via array; wherein, the first test pad is disposed on an insulating dielectric layer, and the depth of the first contact / via array extends into the insulating dielectric layer; the second test pad is disposed on a wafer silicon substrate layer, and the depth of the second contact / via array extends into the monitoring dielectric layer. Through the measurement structure and the semiconductor structure for a contact / via etching process disclosed by the present invention, over-etching of contacts / vias can be monitored without damaging the semiconductor structure.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a measurement structure, a monitoring method, and a semiconductor structure for a contact / via etching process. Background Art

[0002] The etching of contact holes and vias is a key process step in the wafer manufacturing process. After forming multiple semiconductor devices on a wafer silicon substrate, multiple stacked thin films are formed on the semiconductor devices, and then a metal interconnection layer is formed on the stacked thin films to connect multiple semiconductor devices to each other to form a functional circuit. Among them, the first metal interconnection layer is connected to the semiconductor device through a contact hole, and other metal interconnection layers are connected through vias.

[0003] When etching contact holes and vias, it is necessary to monitor the over-etching depth of the contact holes and vias. However, since the depth of the contact holes and vias is relatively deep, while the over-etching depth of the contact holes and vias is relatively small, it is impossible to accurately measure the over-etching depth of the contact holes and vias through optical detection. Summary of the Invention

[0004] The purpose of the present invention is to provide a measurement structure, a monitoring method, and a semiconductor structure for a contact / via etching process, which can solve the problem that the over-etching depth of contact holes and vias cannot be accurately measured by optical detection methods.

[0005] To solve the above technical problems, the present invention is realized through the following technical solutions:

[0006] The present invention provides a measurement structure for a contact / via etching process. The measurement structure is disposed in a scribe line of a wafer, and the measurement structure includes:

[0007] A first test pad, including an etch stop layer and a contact hole / via dielectric layer, and the first test pad is provided with a first contact / via array; and

[0008] A second test pad, including a monitoring dielectric layer, an etch stop layer, and a contact hole / via dielectric layer, and the second test pad is provided with a second contact / via array;

[0009] Wherein, the first test pad is disposed on an insulating dielectric layer, and the depth of the first contact / via array extends into the insulating dielectric layer; the second test pad is disposed on a wafer silicon substrate layer, and the depth of the second contact / via array extends into the monitoring dielectric layer; the first test pad and the second test pad are adjacent to each other.

[0010] In an embodiment of the present invention, the monitoring dielectric layer is a conductive metal material, and the etch selectivity between the insulating dielectric layer and the monitoring dielectric layer is greater than 10.

[0011] In an embodiment of the present invention, when the measurement structure is used to measure a contact hole, the insulating dielectric layer is a silicon oxide layer in a shallow trench within a wafer silicon substrate.

[0012] In an embodiment of the present invention, when the measurement structure is used to measure a contact hole, the monitoring dielectric layer is a metal silicide layer.

[0013] In an embodiment of the present invention, when the measurement structure is used to measure a via hole, the monitoring dielectric layer is a metal wire layer.

[0014] In an embodiment of the present invention, when the measurement structure is used to measure a via hole, the insulating dielectric layer is a low-k silicon oxide layer deposited on the surface of a wafer silicon substrate.

[0015] In an embodiment of the present invention, the distance range between the centers of the first test pad and the second test pad is 50 um to 1 mm.

[0016] In an embodiment of the present invention, the sizes of the first test pad and the second test pad are equal to or greater than 50 um × 50 um.

[0017] The present invention also provides a monitoring method for the measurement structure as described above, where the measurement structure is used to monitor the over-etched thickness of the monitoring dielectric layer of the contact hole / via hole, and the monitoring method includes:

[0018] Optically measuring the depth of the contacts / via holes in the first contact / via hole array in the first test pad;

[0019] Optically measuring the depth of the contacts / via holes in the second contact / via hole array in the second test pad;

[0020] Obtaining the difference between the depth of the contacts / via holes in the first contact / via hole array and the depth of the contacts / via holes in the second contact / via hole array, and obtaining the over-etched thickness of the monitoring dielectric layer based on this depth difference and the etching rate difference between the monitoring dielectric layer and the insulating dielectric layer.

[0021] The present invention also provides a semiconductor structure including the measurement structure of any one of the above-described contact / via hole etching processes.

[0022] In summary, the present invention provides a measurement structure, a monitoring method, and a semiconductor structure for a contact / through-hole etching process. The measurement structure for the contact / through-hole etching process includes a first test pad and a second test pad. The first test pad includes an etch stop layer and a contact hole / through-hole dielectric layer, and the first test pad is provided with a first contact / through-hole array. The second test pad includes a monitoring dielectric layer, an etch stop layer, and a contact hole / through-hole dielectric layer, and the second test pad is provided with a second contact / through-hole array. Among them, the first test pad is disposed on the insulating dielectric layer, and the depth of the first contact / through-hole array extends into the insulating dielectric layer. The second test pad is disposed on the wafer silicon substrate layer, and the depth of the second contact / through-hole array extends into the monitoring dielectric layer. The first test pad and the second test pad are adjacent to each other. When using the measurement structure for the contact / through-hole etching process provided by the present application to monitor the over-etching thickness of the monitoring dielectric layer of the contact hole / through-hole, first optically measure the depth of the contact / through-hole in the first contact / through-hole array in the first test pad, and then optically measure the depth of the contact / through-hole in the second contact / through-hole array in the second test pad. And obtain the difference between the depth of the contact / through-hole in the first contact / through-hole array and the depth of the contact / through-hole in the second contact / through-hole array. Based on this depth difference and the etching rate difference between the monitoring dielectric layer and the insulating dielectric layer, the over-etching thickness of the monitoring dielectric layer is obtained. It is possible to avoid damage to semiconductor devices caused by measurement, and it is also possible to avoid that the over-etching depth is too small to be measured, thereby efficiently and nondestructively obtaining the degree of over-etching of the contact / through-hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 It is a schematic structural diagram of a semiconductor structure in an embodiment of the present application.

[0025] Figure 2 It is a schematic structural diagram of forming a contact hole in an embodiment of the present application.

[0026] Figure 3 It is a schematic structural diagram of forming a contact in an embodiment of the present application.

[0027] Figure 4 It is a schematic structural diagram of forming a through-hole in an embodiment of the present application.

[0028] Figure 5 It is a schematic structural diagram of forming a conductive structure in an embodiment of the present application.

[0029] Figure 6This is a top view of the measurement structure of the contact / through-hole etching process when measuring contact holes in an embodiment of the present application.

[0030] Figure 7 This is a cross-sectional view of the measurement structure of the contact / through-hole etching process when measuring contact holes in an embodiment of the present application.

[0031] Figure 8 This is a top view of the measurement structure of the contact / through-hole etching process when measuring through-holes in an embodiment of the present application.

[0032] Figure 9 This is a cross-sectional view of the measurement structure of the contact / through-hole etching process when measuring through-holes in an embodiment of the present application.

[0033] Reference numeral description:

[0034] 101, wafer silicon substrate; 102, shallow trench isolation structure; 103, active region; 104, gate; 105, metal silicide layer; 106, first etching barrier layer; 107, contact hole dielectric layer; 108, contact; 1081, contact hole; 109, metal interconnect layer; 110, first photoresist layer; 111, second etching barrier layer; 112, through-hole dielectric layer; 113, conductive structure; 1131, through-hole; 114, metal layer; 1141, wire layer; 1142, intermetal dielectric layer; 115, second photoresist layer; 201, first test pad; 2011, first contact / through-hole; 202, second test pad; 2021, second contact / through-hole. Detailed implementation manners

[0035] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0037] In the present invention, it should be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes, and cannot be construed as indicating or implying relative importance.

[0038] Please refer to Figures 1 to 5 As shown, when forming an integrated circuit semiconductor structure, first form a shallow trench isolation structure 102 and an active region 103 on the wafer silicon substrate 101, then form structures such as a gate 104 on the wafer silicon substrate 101, and further form multiple semiconductor devices on the wafer silicon substrate 101. After that, form a multi-layer stacked film on the wafer silicon substrate 101 and the semiconductor devices, form a contact hole 1081 in the multi-layer stacked film, and fill the contact hole 1081 with a conductive material to form a contact 108. Finally, form a metal interconnect layer 109 on the multi-layer stacked film to form a complete functional circuit. Among them, the metal interconnect layer 109 is connected to the gate 104 or the active region 103 of the semiconductor device through the contact 108, and the other metal interconnect layers 109 are connected through the conductive structure 113 in the via 1131.

[0039] Please refer to Figure 1 As shown, it should be noted that on a wafer silicon substrate 101, usually several hundred to several thousand chips are connected together, and a scribe line (not shown in the figure) is provided between each chip. After the manufacturing process and testing of the semiconductor devices on the wafer silicon substrate 101 are completed, the semiconductor devices on a wafer silicon substrate 101 are divided into multiple chips through the scribe line.

[0040] Please refer to Figures 1 to 3As shown, in an embodiment of the present invention, the multi-layer stacked film formed on the wafer silicon substrate 101 and the semiconductor device includes a metal silicide layer 105. The metal silicide layer 105 is disposed on the active region 103 and the gate 104, and the material of the metal silicide layer 105 is, for example, nickel silicide (NiSi). Specifically, an alloy layer, such as a nickel-platinum alloy layer, can be first formed on the wafer silicon substrate 101 or the active region 103. After annealing, the nickel in the nickel-platinum alloy layer reacts with the silicon in the polysilicon in the active region 103 and the gate 104 to form the metal silicide layer 105. When connecting the metal interconnect layer 109 and the active region 103 or the gate 104, the high conductivity of the silicide material in the active region 103 and the gate 104 is utilized to form a low-resistance connection between the metal interconnect layer 109 and the semiconductor device in the wafer silicon substrate 101.

[0041] Please refer to Figures 1 to 3 As shown, in an embodiment of the present invention, forming a multi-layer stacked film on the wafer silicon substrate 101 and the semiconductor device includes an etch contact hole stacked film. Among them, the etch contact hole stacked film includes a first etch stop layer (Etch Stop Layer, ESL) 106 and an etch contact hole dielectric layer 107. Among them, the first etch stop layer 106 is disposed on the metal silicide layer 105 and the wafer silicon substrate 101, and the material of the first etch stop layer 106 can be a material such as silicon nitride with high stress. The etch contact hole dielectric layer 107 is disposed on the first etch stop layer 106, and the material of the etch contact hole dielectric layer 107 is, for example, a material such as silicon oxide. On the etch contact hole stacked film, a first photoresist layer 110 is further disposed, and the first photoresist layer 110 is used to define the position of the contact hole 1081. When etching the etch contact hole stacked film to form the contact hole 1081, the first etching is first performed. The first etching uses reactive ion etching (reaction ion etching, RIE) to etch the etch contact hole dielectric layer 107 and stops on the first etch stop layer 106. Then, the second etching is performed, and the second etching uses a gas different from the first etching to etch the first etch stop layer 106. Among them, the etching rate of the gas for the first etching on the etch contact hole dielectric layer 107 is much greater than the etching rate on the first etch stop layer 106, and the etching rate of the gas for the second etching on the first etch stop layer 106 is much greater than the etching rate on the metal silicide layer 105.

[0042] Please refer to Figures 1 to 3As shown, in an embodiment of the present invention, after the etching of the first etch stop layer 106 is completed, the gas for the second etching is used to continue etching the surface of the metal silicide layer 105, and a part of the metal silicide layer 105 is etched away, that is, the metal silicide layer 105 is over-etched, that is, the over-etching of the contact hole 1081. Since there are differences in the thickness of the first etch stop layer 106 on different wafer silicon substrates 101, if the metal silicide layer 105 is not over-etched, not all of the contact holes 1081 can precisely stop on the upper surface of the first etch stop layer 106. Therefore, it is necessary to over-etch the metal silicide layer 105 to ensure that the contact hole 1081 is in contact with the metal silicide layer 105. When over-etching the metal silicide layer 105, if the over-etching is insufficient, residues of the first etch stop layer 106 will remain on the top of the metal silicide layer 105, causing an open circuit failure. If the over-etching is excessive, since the metal silicide layer 105 is relatively thin, the metal silicide layer 105 will be excessively consumed, resulting in a high contact resistance failure. Therefore, during the over-etching of the contact hole 1081, it is necessary to monitor the depth of the over-etching of the contact hole 1081.

[0043] Please refer to Figures 1 to 5 As shown, in an embodiment of the present invention, the metal interconnect layer 109 includes a stacked metal layer 114 and a via etch stack film. Among them, the metal layer 114 includes a metal wire layer 1141 and an inter-metal dielectric layer 1142. The metal wire layer 1141 can be a patterned metal wire layer 1141 formed of a metal such as copper, and the inter-metal dielectric layer 1142 is disposed between the metal wire layers 1141 to isolate the metal wire layers 1141 of the same layer. The inter-metal dielectric layer 1142 disposed between the metal wire layers 1141 can prevent the contact between the patterned metal wire layers 1141 of the same layer, causing a short circuit. The inter-metal dielectric layer 1142 can be formed of an oxide material such as silicon oxide or other low dielectric constant materials.

[0044] Please refer to Figures 1 to 5As shown, in an embodiment of the present invention, the via etch stack film is located between two adjacent metal layers 114 or between the metal layer 114 and the semiconductor device on the wafer silicon substrate 101, which can isolate two adjacent metal layers 114 or isolate the metal layer 114 and the semiconductor device. The via etch stack film generally includes a second etch stop layer 111 and a via dielectric layer 112. The material of the second etch stop layer 111 can be a material such as silicon nitride with high stress, and the via dielectric layer 112 is silicon oxide. A second photoresist layer 115 is further provided on the via etch stack film, and the second photoresist layer 115 is used to define the position of the via 1131. A via 1131 is formed between adjacent metal interconnect layers 109. The via 1131 also needs to pass through the via etch stack film, connect to the metal wire layer 1141, and perform over-etching on the metal wire layer 1141, that is, the over-etching of the via 1131, to ensure effective electrical connection between adjacent metal interconnect layers 109.

[0045] Please refer to Figures 1 to 5 As shown, since the thicknesses of the metal silicide layer 105 and the metal wire layer 1141 are small, the over-etching thicknesses of the contact hole 1081 and the via 1131 are even smaller. However, only the overall depth of the contact hole 1081 or the via 1131 can be detected by optical methods. Due to the errors between the film thicknesses of each layer, the over-etching degree of the contact hole 1081 and the via 1131 cannot be accurately detected. If the over-etching thicknesses of the contact hole 1081 and the via 1131 are measured by a transmission electron microscope (TEM), it will damage the wafer and is not suitable for wafer production and manufacturing. The present application provides a measurement structure for a contact / via etch process, which can effectively and non-destructively monitor the over-etching degree of the contact hole / via, correct the errors generated during the etching process, and ensure the quality of the formed product.

[0046] Please refer to Figures 6 to 9As shown, the measurement structure of the contact / via etching process provided by the present invention includes a first test pad 201 and a second test pad 202. Among them, the first test pad 201 includes an etched stacked film, and the second test pad 202 includes a monitoring dielectric layer and an etched stacked film. The first test pad 201 is disposed on the insulating dielectric layer, and the second test pad 202 is disposed on the wafer silicon substrate 101. The etched stacked film includes an etch stop layer and a contact hole / via dielectric layer disposed on the etch stop layer. A first contact / via array is provided on the first test pad 201, and a second contact / via array is provided on the second test pad 202. The first contact / via array includes a plurality of first contacts / vias 2011 arranged in an array, and the first contacts / vias 2011 penetrate through the etched stacked film into the insulating dielectric layer. The second contact / via array includes a plurality of second contacts / vias 2021 arranged in an array, and the second contacts / vias 2021 penetrate through the etched stacked film into the monitoring dielectric layer. The first contacts / vias 2011 and the second contacts / vias 2021 are etched synchronously. The etching rate of the insulating dielectric layer in the first contacts / vias 2011 is much greater than the etching rate of the monitoring dielectric layer in the second contacts / vias 2021. Finally, the depth difference between the first contacts / vias 2011 and the second contacts / vias 2021 is the monitoring result of the contact / via over-etching. The monitoring dielectric layer is a semiconductor layer over-etched by the contact hole 1081 or the via 1131, that is, the metal silicide layer 105 or the metal wire layer 1141. The semiconductor layers in the insulating dielectric layer and the etched stacked film are specifically set according to the positions of the first test pad 201 and the second test pad 202.

[0047] Please refer to Figures 1 to 7As shown, in an embodiment of the present invention, when the measurement structure is used to measure the contact hole 1081, the first test pad 201 is located on the shallow trench isolation structure 102, and the second test pad 202 is located on the active region 103. At this time, the monitoring dielectric layer is the metal silicide layer 105, and the insulating dielectric layer is the silicon oxide layer in the shallow trench isolation, that is, the shallow trench isolation structure 102. The etched stack film is the contact hole etched stack film. Among them, the contact hole etched stack film includes a first etch stop layer 106 and a contact hole dielectric layer 107. At this time, when the first test pad 201 and the second test pad 202 are synchronously etched, and a first contact / through hole 2011 is formed on the first test pad 201 and a second contact / through hole 2021 is formed on the second test pad 202, the etching rates of the etched stack films on the two test pads are equal. When over-etching is performed, when the metal silicide layer 105 in the second test pad 202 is slowly etched, the etching rate of the shallow trench isolation structure 102 in the first test pad 201 is much greater than the etching rate of the metal silicide layer 105. Therefore, the shallow trench isolation structure 102 in the first test pad 201 is etched faster. At this time, the difference in depth between the first contact / through hole 2011 and the second contact / through hole 2021 is proportional to the over-etching level. Therefore, the difference in depth between the first contact / through hole 2011 and the second contact / through hole 2021 can be used to obtain the monitoring result of the contact / through hole over-etching, that is, the thickness of the over-etched monitoring dielectric layer.

[0048] Please refer to Figures 1 to 7As shown, in an embodiment of the present invention, the difference in depth between the first contact / through hole 2011 and the second contact / through hole 2021 is the difference in etching depth between the shallow trench isolation structure 102 in the first test pad 201 and the metal silicide layer 105 in the second test pad 202. In the present application, the monitoring dielectric layer is a conductive metal material. When the gas for etching the first etching barrier layer 106 is used to simultaneously etch the shallow trench isolation structure 102 and the metal silicide layer 105, the etching rate ratio of the insulating dielectric layer (shallow trench isolation structure 102) to the monitoring dielectric layer (metal silicide layer 105) is greater than 10, that is, the etching selectivity between the insulating dielectric layer (shallow trench isolation structure 102) and the monitoring dielectric layer (metal silicide layer 105) is greater than 10. Therefore, relative to the etching depth of the shallow trench isolation structure 102 in the first test pad 201, the etching depth of the metal silicide layer 105 in the second test pad 202 is very small. When the etching depth of the metal silicide layer 105 increases, the difference in depth between the first contact / through hole 2011 and the second contact / through hole 2021 also gradually increases. Specifically, when the etching depth of the metal silicide layer 105 is zero, the etching depth of the shallow trench isolation structure 102 is zero, and the difference in depth between the first contact / through hole 2011 and the second contact / through hole 2021 is zero. As the etching depth of the metal silicide layer 105 gradually increases, the etching depth of the shallow trench isolation structure 102 also gradually increases, and the difference in etching depth between the shallow trench isolation structure 102 and the metal silicide layer 105 is approximately equal to the etching depth of the shallow trench isolation structure 102, that is, the difference in etching depth between the shallow trench isolation structure 102 and the metal silicide layer 105 also gradually increases. When the metal silicide layer 105 is etched to completion, the etching depth of the shallow trench isolation structure 102 is the largest, which is the first preset depth. At this time, the difference in depth between the first contact / through hole 2011 and the second contact / through hole 2021 is the largest, which is the first preset depth minus the thickness of the metal silicide layer 105. Therefore, the difference in depth between the first contact / through hole 2011 and the second contact / through hole 2021 can be used as the monitoring result of contact / through hole over-etching. When the metal silicide layer 105 in the second contact / through hole 2021 is etched, the shallow trench isolation structure 102 in the first contact / through hole 2011 is etched, and as the etching depth of the metal silicide layer 105 increases, the difference in etching depth between the shallow trench isolation structure 102 and the metal silicide layer 105 gradually increases.

[0049] Please refer to Figures 1 to 5 , and Figure 8 and Figure 9As shown, in another embodiment of the present invention, when the measurement structure is used to measure the through-hole 1131, the first test pad 201 is located on the inter-metal dielectric layer 1142, that is, on the low-k silicon oxide layer deposited on the surface of the wafer silicon substrate 101, and the second test pad 202 is located on the metal wire layer 1141. At this time, the monitoring dielectric layer is the metal wire layer 1141, and the insulating dielectric layer is the inter-metal dielectric layer 1142, that is, the low-k insulating dielectric layer deposited on the surface of the wafer silicon substrate 101, that is, the low-k silicon oxide layer. The etched stack film is the through-hole etched stack film. Among them, the through-hole etched stack film includes the second etch stop layer 111 and the through-hole dielectric layer 112. At this time, when synchronously etching the through-hole dielectric layer 112 and the second etch stop layer 111 in the first test pad 201 and the second test pad 202 to form the first contact / through-hole 2011 on the first test pad 201 and the second contact / through-hole 2021 on the second test pad 202, the etching rates of the etched stack films on the two test holes are equal. When over-etching the metal wire layer 1141 and the inter-metal dielectric layer 1142 with the gas for etching the second etch stop layer 111, when the metal wire layer 1141 in the second test pad 202 is slowly etched, the etching rate of the inter-metal dielectric layer 1142 in the first test pad 201 is much greater than that of the metal wire layer 1141, so the inter-metal dielectric layer 1142 in the first test pad 201 is etched faster. At this time, the difference in depth between the first contact / through-hole 2011 and the second contact / through-hole 2021 is proportional to the over-etching level, so the difference in depth between the first contact / through-hole 2011 and the second contact / through-hole 2021 can be used to obtain the monitoring result of the contact / through-hole over-etching, that is, the thickness of the over-etched monitoring dielectric layer.

[0050] Please refer to Figures 1 to 5 , and Figure 8 and Figure 9As shown, in another embodiment of the present invention, the difference in depth between the first contact / through hole 2011 and the second contact / through hole 2021 is the difference in etching depth between the inter-metal dielectric layer 1142 in the first test pad 201 and the metal wire layer 1141 in the second test pad 202. In the present application, the monitoring dielectric layer is a conductive metal material. When etching the metal wire layer 1141 and the inter-metal dielectric layer 1142 simultaneously using the gas for etching the second etch stop layer 111, the etching rate ratio of the insulating dielectric layer (inter-metal dielectric layer 1142) to the monitoring dielectric layer (metal wire layer 1141) is greater than 10, that is, the etch selectivity between the insulating dielectric layer (inter-metal dielectric layer 1142) and the monitoring dielectric layer (metal wire layer 1141) is greater than 10. Therefore, the etching depth of the metal wire layer 1141 in the second test pad 202 is very small relative to the etching depth of the inter-metal dielectric layer 1142 in the first test pad 201. Thus, when the etching depth of the metal wire layer 1141 increases, the difference in depth between the first contact / through hole 2011 and the second contact / through hole 2021 also gradually increases. Specifically, when the etching depth of the metal wire layer 1141 is zero, the depth of the inter-metal dielectric layer 1142 is zero, and the difference in depth between the first contact / through hole 2011 and the second contact / through hole 2021 is zero. As the etching depth of the metal wire layer 1141 gradually increases, the etching depth of the inter-metal dielectric layer 1142 also gradually increases, and the difference in etching depth between the inter-metal dielectric layer 1142 and the metal wire layer 1141 is approximately equal to the etching depth of the inter-metal dielectric layer 1142, that is, the difference in etching depth between the inter-metal dielectric layer 1142 and the metal wire layer 1141 also gradually increases. When the metal wire layer 1141 is etched to completion, the etching depth of the inter-metal dielectric layer 1142 is the largest, which is the second preset depth. At this time, the difference in depth between the first contact / through hole 2011 and the second contact / through hole 2021 is the largest, which is the second preset depth minus the thickness of the metal wire layer 1141. Therefore, the difference in depth between the second contact / through hole 2021 and the first contact / through hole 2011 can be used as the monitoring result of the through hole over-etching. When the metal wire layer 1141 in the second contact / through hole 2021 is etched, the inter-metal dielectric layer 1142 in the first contact / through hole 2011 is etched, and as the etching depth of the metal wire layer 1141 increases, the difference in etching depth between the inter-metal dielectric layer 1142 and the metal wire layer 1141 gradually increases.

[0051] Please refer to Figures 6 to 9 As shown, in some embodiments, the first contact / through hole 2011 may also extend into the via dielectric layer 112. Both the via dielectric layer 112 and the inter-metal dielectric layer 1142 are low-k silicon oxide layers. Therefore, the via dielectric layer 112 can also be used as an insulating dielectric layer.

[0052] Please refer toFigures 6 to 9 As shown, in the embodiment provided by the present invention, to ensure that the first test pad 201 and the second test pad 202 do not affect the formation of semiconductor devices in the integrated circuit, the first test pad 201 and the second test pad 202 are arranged on the dicing line. The sizes of the first test pad 201 and the second test pad 202 are equal to or greater than, for example, 50um×50um, and the distance between the centers of the first test pad 201 and the second test pad 202 is, for example, 50um to 1mm. At this time, it is possible to avoid a too large distance between the first test pad 201 and the second test pad 202 resulting in a large difference in the thicknesses of the respective thin films within the first test pad 201 and the second test pad 202, such that the difference in the depth of the first contact / via 2011 and the depth of the second contact / via 2021 cannot be used as a standard for measuring over-etching.

[0053] Please refer to Figures 6 to 9 As shown, in the embodiment provided by the present invention, on the first test pad 201 and the second test pad 202, the numbers of the first contact / vias 2011 and the second contact / vias 2021 are set according to requirements. Specifically, the first contact / via array includes n×m first contact / vias 2011, and the second contact / via array includes n×m second contact / vias 2021, where the values of n and m are integers ranging from dozens to tens of thousands, and n and m can be equal or unequal. In the figure, the first contact / via array including 3×3 first contact / vias 2011 and the second contact / via array including 3×3 second contact / vias 2021 are only schematic diagrams of the contact / via arrays.

[0054] Please refer to Figures 6 to 9 As shown, in the embodiment provided by the present invention, when using the measurement structure provided by this application to monitor the over-etching thickness of the monitoring dielectric layer of the contact hole / via, the depths of the first contact / vias 2011 in the first test pad and the second contact / vias 2021 in the second test pad can first be measured by a scattering measurement method (such as optical critical dimension OCD), then the difference in the depths of the second contact / vias 2021 and the first contact / vias 2011 is obtained, and the difference in the depths of the second contact / vias 2021 and the first contact / vias 2011 is used to monitor the over-etching thickness of the monitoring dielectric layer of the contact hole / via.

[0055] Please refer to Figures 6 to 9As shown, in the embodiments provided by the present invention, there is no limitation on the gases for etching the contact hole dielectric layer 107 and the via hole dielectric layer 112, the gases for etching the first etching barrier layer 106 and the second etching barrier layer 111, and the etching gases for the monitoring dielectric layer and the insulating dielectric layer. Specifically, the etching gases for the contact hole dielectric layer 107, the via hole dielectric layer 112, the first etching barrier layer 106, the second etching barrier layer 111, the monitoring dielectric layer and the insulating dielectric layer can all be fluorine-containing gases, and the content of fluorine can be adjusted according to the specific materials of each semiconductor layer.

[0056] In summary, the present invention provides a measurement structure, a monitoring method and a semiconductor structure for a contact / via etching process. The measurement structure for the contact / via etching process includes a first test pad and a second test pad. The first test pad includes an etching barrier layer and a contact hole / via hole dielectric layer, and the first test pad is provided with a first contact / via array. The second test pad includes a monitoring dielectric layer, an etching barrier layer and a contact hole / via hole dielectric layer, and the second test pad is provided with a second contact / via array. Among them, the first test pad is disposed on the insulating dielectric layer, and the depth of the first contact / via array extends into the insulating dielectric layer. The second test pad is disposed on the wafer silicon substrate layer, and the depth of the second contact / via array extends into the monitoring dielectric layer. The first test pad and the second test pad are adjacently disposed. When using the measurement structure for the contact / via etching process provided by the present application to monitor the over-etching thickness of the monitoring dielectric layer of the contact hole / via hole, first optically measure the depth of the contact / via in the first contact / via array in the first test pad, and then optically measure the depth of the contact / via in the second contact / via array in the second test pad. And obtain the difference between the contact / via depth of the first contact / via array and the contact / via depth of the second contact / via array, and measure the over-etching thickness of the monitoring dielectric layer based on this depth difference and the etching rate difference between the monitoring dielectric layer and the insulating dielectric layer. It can avoid damage to semiconductor devices caused by measurement, and can also avoid that the over-etching depth is too small to be measured, thereby efficiently and non-destructively obtaining the degree of over-etching of the contact / via. The measurement structure, monitoring method and semiconductor structure for a contact / via etching process provided by the present application can accurately monitor the over-etching thickness of the contact / via without damaging the semiconductor structure.

[0057] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art in the technical field can understand and utilize the present invention well. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A measurement structure for a contact / via etching process, the measurement structure being disposed in a saw street of a wafer, characterized in that, And the measurement structure includes: A first test pad, including an etch stop layer and a contact hole / via dielectric layer, the first test pad being provided with a first contact / via array; and A second test pad, including a monitoring dielectric layer, an etch stop layer and a contact hole / via dielectric layer, the second test pad being provided with a second contact / via array; Wherein, the first test pad is disposed on the insulating dielectric layer, and the depth of the first contact / via array extends into the insulating dielectric layer; the second test pad is disposed on the wafer silicon substrate layer, and the depth of the second contact / via array extends into the monitoring dielectric layer; the first test pad and the second test pad are adjacently disposed.

2. The measurement structure according to claim 1, wherein, The monitoring dielectric layer is a conductive metal material, and the etch selectivity between the insulating dielectric layer and the monitoring dielectric layer is greater than 10.

3. The measurement structure according to claim 1, characterized in that, When the measurement structure is used to measure a contact hole, the insulating dielectric layer is a silicon oxide layer in a shallow trench within the wafer silicon substrate.

4. The measuring structure according to claim 1, characterized in that, When the measurement structure is used to measure a contact hole, the monitoring dielectric layer is a metal silicide layer.

5. The measurement structure according to claim 1, wherein When the measurement structure is used to measure a via, the monitoring dielectric layer is a metal wire layer.

6. The measurement structure according to claim 1, characterized in that When the measurement structure is used to measure a via, the insulating dielectric layer is a low-k silicon oxide layer deposited on the surface of the wafer silicon substrate.

7. The measurement structure according to claim 1, characterized in that The distance range between the centers of the first test pad and the second test pad is 50um to 1mm.

8. The measurement structure according to claim 1, characterized in that, The sizes of the first test pad and the second test pad are equal to or greater than 50um×50um.

9. A monitoring method for a measurement structure as described in claim 1, characterized in that, The measurement structure is used to monitor the over-etched thickness of the monitoring dielectric layer of the contact hole / via, and the monitoring method includes: Optically measuring the depth of the contacts / vias in the first contact / via array in the first test pad; Optically measuring the depth of the contacts / vias in the second contact / via array in the second test pad; Obtaining the difference between the depth of the contacts / vias in the first contact / via array and the depth of the contacts / vias in the second contact / via array, and obtaining the over-etched thickness of the monitoring dielectric layer based on this depth difference and the etching rate difference between the monitoring dielectric layer and the insulating dielectric layer.

10. A semiconductor structure, characterized in that, A measurement structure including the contact / via etching process according to any one of claims 1 to 8.

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