Logic control method and device and digital power supply
By detecting the load state and current loop output signals in a dual closed-loop buck circuit in real time, judging the state of the second switching transistor and the output power, and controlling the opening and closing of the first switching transistor, the problem of inductance energy accumulation during load state switching is solved, and faster dynamic response and shorter stabilization time are achieved.
Patent Information
- Application Number
- CN202510014153.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2025-04-25
AI Technical Summary
When the buck circuit suddenly switches from heavy load to light load or no load, the synchronous rectifier tube is not turned on, causing the energy on the inductor to accumulate on the capacitor, the voltage increases, and the dynamic response is poor.
By real-time detection of the load state of the double closed-loop buck circuit, the output signal of the current loop, the shutdown condition of the second switching transistor and the output power are obtained. When the load state is switched, it is determined whether the output signal is smaller than the preset signal value, whether the second switching transistor is turned off, and whether the output power is greater than the preset power value. If the conditions are met, the first switching transistor is closed to achieve energy leakage of the output capacitor, reduce the stabilization time and speed up the dynamic response.
By controlling the opening and closing of the first switching transistor, the energy leakage of the output capacitor in the double closed-loop buck circuit is realized, the stability time is reduced, the dynamic response is accelerated, and the circuit performance is improved during the load state switching.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of power supply technology, and in particular to a logic control method and device thereof, and a digital power supply. Background Art
[0002] The step-down circuit in a digital power supply generally adopts a voltage-current dual closed-loop control, where the inductor current is the inner loop and the output voltage is the outer loop. The inner and outer loops are controlled by two MOS tubes, namely the switching transistor and the synchronous rectifier tube, or the corresponding ones are called Figure 1 The upper tube and lower tube are shown. The dual-loop controller outputs the duty cycle D as the control signal of the upper tube to control the conduction and shutdown of the upper tube in the buck circuit. The lower tube is turned on complementary to the upper tube. In order to improve the efficiency under light load, the synchronous rectifier tube is generally turned on when the output power of the buck circuit is slightly larger, that is, the lower tube is turned on. Therefore, the turn-on logic of the synchronous rectifier tube can be written as (A and B), where condition A represents that the upper tube of the buck circuit is turned off, and condition B represents that the output power of the circuit is greater than a certain power value.
[0003] That is, the synchronous rectifier is not turned on when the load is light, which saves the switching loss of the synchronous rectifier. The synchronous rectifier is turned on when the load is heavy, which saves the conduction loss of the synchronous rectifier. However, when the buck circuit suddenly switches from heavy load to light load or no load, condition A is satisfied, but condition B is not satisfied, (A and B) = 0. At this time, the synchronous rectifier is not turned on, and the energy on the inductor in the circuit will accumulate on the capacitor, causing the voltage to rise. In addition, since the load end resistance becomes very large, the energy on the capacitor is released slowly, which will lead to poor dynamic response of the buck circuit. Summary of the invention
[0004] In view of this, the present application aims to solve one of the problems in the related art at least to a certain extent. To this end, the purpose of the present application is to provide a logic control method and device thereof and a digital power supply.
[0005] The present application provides a logic control method, which is applied to a dual closed-loop buck circuit of a digital power supply. The dual closed-loop buck circuit includes a first loop composed of a current loop and a second loop composed of a voltage loop, wherein a first switch transistor is provided on the first loop and a second switch transistor is provided on the second loop; the logic control method includes: real-time detection of the load state of the dual closed-loop buck circuit, and acquisition of the output signal of the current loop, the shutdown state of the second switch transistor and the output power of the dual closed-loop buck circuit; when the load state of the dual closed-loop buck circuit is switched from the first load state to the second load state, it is determined whether the output signal is less than a preset signal value, whether the second switch transistor is disconnected and whether the output power is greater than a preset power value, and the load amount of the first load state is greater than the load amount of the second load state; if the second switch transistor is in an off state and the output signal is less than the preset signal value, or the second switch transistor is in an off state and the output power is greater than the preset power value, the first switch transistor is controlled to be closed.
[0006] In certain embodiments, when the load condition of the dual closed-loop buck circuit switches from a first load state to a second load state, determining whether the output signal is less than a preset signal value, determining whether the second switch transistor is disconnected, and determining whether the output power is greater than a preset power value, the load amount of the first load state is greater than the load amount of the second load state, including: preferentially determining whether the second switch transistor is in an off state; after determining that the second switch transistor is in an off state, determining whether the value of the output signal is greater than or equal to the preset signal value and determining whether the output power is greater than a preset power value.
[0007] In certain embodiments, the logic control method includes: when the dual closed-loop buck circuit is in steady-state operation, collecting the output voltage of the current loop to obtain a sampled value of the output voltage; and using the sampled value of the output voltage as the preset signal value.
[0008] In some embodiments, the real-time acquisition of the output signal of the current loop includes: acquiring the target current value of the voltage loop output and the current feedback value actually output by the current loop; obtaining a current error value based on the difference between the target current value and the current feedback value; and inputting the current error value into a preset compensator for processing to obtain the output signal.
[0009] In some embodiments, the preset compensator is a proportional-integral compensator.
[0010] In some embodiments, the logic control method includes: after controlling the first switch transistor to close, determining in real time whether the output signal is greater than or equal to the preset signal value; if the output signal is greater than or equal to the preset signal value, controlling the first switch transistor to be disconnected.
[0011] In some embodiments, the logic control method includes: if the second switching transistor is in an off state and the output signal is less than the preset signal value, or the second switching transistor is off and the output power is greater than the preset power value, then controlling to drive the first switching transistor to close with a preset switching cycle.
[0012] In certain embodiments, the logic control method includes: after closing the first switching transistor, obtaining the voltage value across the output capacitor of the dual closed-loop buck circuit in real time; when the difference between the voltage value across the output capacitor and the voltage value when the dual closed-loop buck circuit is in steady-state operation is less than or equal to a preset difference, controlling the disconnection time of the next preset switching cycle to be greater than the disconnection time of the previous preset switching cycle, and the disconnection time of the next preset switching cycle increases with the increase in the number of closing times of the first switching transistor.
[0013] The present application also provides a logic control device, which is applied to a dual closed-loop buck circuit of a digital power supply. The dual closed-loop buck circuit includes a first loop consisting of a current loop and a second loop consisting of a voltage loop, wherein a first switch transistor is provided on the first loop, and a second switch transistor is provided on the second loop. The logic control device includes: an acquisition module, a judgment module and a control module. The acquisition module is used to detect the load state of the dual closed-loop buck circuit in real time, and to obtain the output signal of the current loop, the shutdown state of the second switch transistor and the output power of the dual closed-loop buck circuit; the judgment module is used to judge whether the output signal is less than a preset signal value, whether the second switch transistor is disconnected and whether the output power is greater than a preset power value when the load state of the dual closed-loop buck circuit is switched from the first load state to the second load state, and the load amount of the first load state is greater than the load amount of the second load state; the control module is used to control the closing of the first switch transistor if the second switch transistor is in an off state and the output signal is less than the preset signal value, or if the second switch transistor is in an off state and the output power is greater than the preset power value.
[0014] The present application also provides a digital power supply. The digital power supply includes a dual closed-loop buck circuit and the logic control device described in the above embodiment, the logic control device can perform logic control on and off of the first switch transistor in the dual closed-loop buck circuit, or the digital power supply is used to implement the logic control method described in any one of the above embodiments.
[0015] In this way, when the load state of the dual closed-loop buck circuit is switched from the first load state to the second load state, the logic control method of the present application can control the closing of the first switching transistor by adding a judgment on whether the output signal of the current loop is less than the preset signal value when the second switching transistor is in the off state and the output power of the dual closed-loop buck circuit is greater than the preset power value, thereby realizing the energy discharge of the output capacitor in the dual closed-loop buck circuit, reducing the stabilization time, and accelerating the dynamic response of the dual closed-loop buck circuit.
[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0018] Figure 1 It is a structural schematic diagram of a dual closed-loop buck circuit of a digital power supply in certain embodiments of the present application;
[0019] Figure 2 is a flow chart of a logic control method of certain embodiments of the present application;
[0020] Figure 3 is a schematic diagram of the structure of a logic control device of certain embodiments of the present application;
[0021] Figure 4 It is a schematic diagram of the relationship between time and the output signal of the current loop in the logic control method of certain embodiments of the present application;
[0022] Figure 5 It is a schematic diagram of the relationship between time and the lower tube driving signal in the logic control method of certain implementation modes of the present application;
[0023] Figure 6 It is a schematic diagram of the relationship between time and a current signal flowing through an inductor in a logic control method of certain embodiments of the present application;
[0024] Figure 7 It is a schematic diagram of the relationship between time and the voltage signal of the output capacitor C1 in the logic control method of certain embodiments of the present application;
[0025] Figure 8 is a schematic diagram of the relationship between time and the voltage signal of the output capacitor C1 in the related art;
[0026] Fig. 9 is a flow chart of a logic control method of certain embodiments of the present application;
[0027] Fig.10 is a flow chart of a logic control method of certain embodiments of the present application;
[0028] Fig.11 is a schematic diagram of the structure of a logic control device of certain embodiments of the present application;
[0029] Fig.12 is a flow chart of a logic control method of certain embodiments of the present application;
[0030] Fig.13 is a flow chart of a logic control method of certain embodiments of the present application;
[0031] Fig.14 It is a flow chart of the logic control method of certain embodiments of the present application. DETAILED DESCRIPTION
[0032] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0033] In the description of the present application, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0034] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense, and may refer to fixed connection, detachable connection, or integral connection; mechanical connection, electrical connection, or mutual communication; direct connection, indirect connection through an intermediate medium, internal connection between two elements, or interaction between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0035] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.
[0036] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0037] See also Figure 1 and Figure 2 The present application discloses a logic control method, which is applied to a dual closed-loop buck circuit 100 of a digital power supply. The dual closed-loop buck circuit 100 includes a first loop consisting of a current loop and a second loop consisting of a voltage loop. A first switching transistor 110 is provided on the first loop, and a second switching transistor 120 is provided on the second loop. The logic control method includes:
[0038] 01: Real-time detection of the load state of the dual closed-loop buck circuit, and acquisition of the output signal of the current loop, the shutdown status of the second switch transistor, and the output power of the dual closed-loop buck circuit;
[0039] 03: When the load state of the dual closed-loop buck circuit is switched from the first load state to the second load state, it is determined whether the output signal is less than a preset signal value, whether the second switch transistor is disconnected, and whether the output power is greater than a preset power value, and the load amount of the first load state is greater than the load amount of the second load state;
[0040] 05: If the second switch transistor is in an off state and the output signal is less than a preset signal value, or the second switch transistor is in an off state and the output power is greater than a preset power value, the first switch transistor is controlled to be closed.
[0041] See also Figure 3 The present application further provides a logic control device 10, which is applied to the dual closed-loop buck circuit 100. The logic control device 10 includes an acquisition module 11, a judgment module 13 and a control module 15.
[0042] Step 01 can be implemented by the acquisition module 11, step 03 can be implemented by the judgment module 13, and step 05 can be implemented by the control module 15. That is to say, the acquisition module 11 is used to detect the load state of the dual closed-loop buck circuit in real time, and to obtain the output signal of the current loop, the shutdown condition of the second switch transistor, and the output power of the dual closed-loop buck circuit; the judgment module 13 is used to judge whether the output signal is less than the preset signal value, whether the second switch transistor is disconnected, and whether the output power is greater than the preset power value when the load state of the dual closed-loop buck circuit is switched from the first load state to the second load state, and the load amount of the first load state is greater than the load amount of the second load state; the control module 15 is used to control the closing of the first switch transistor if the second switch transistor is disconnected and the output signal is less than the preset signal value, or the second switch transistor is disconnected and the output power is greater than the preset power value.
[0043] It can be understood that the first switch transistor is a synchronous rectifier. Figure 1 The lower tube shown in the figure, the second switch transistor is a power switch tube, Figure 1 The upper tube shown. That is to say, the dual closed-loop buck circuit 100 controls the on-off of the circuit by controlling the opening and closing of the second switch transistor, and the power switch tube controls the on-off of the circuit according to the control signal (such as the duty cycle D output by the dual-loop controller). When the duty cycle D is at a high level, the power switch tube is turned on, allowing current to pass through the inductor, and the inductor begins to store energy. When the duty cycle D is at a low level, the power switch tube is turned off. When the power switch tube is turned off, the synchronous rectifier tube is turned on, and the current continues to flow through the synchronous rectifier tube, and the inductor releases energy.
[0044] Specifically, the output signal of the current loop is a digital signal, which can be positive, zero or negative. The turn-off condition of the second switch transistor includes two conditions: closed and open. The output power of the dual closed-loop buck circuit is the power provided by the circuit to the load, and the calculation formula is Pout = Vout × Iload, where Vout is the output voltage and Iload is the load current. In the dual closed-loop buck circuit, when the load changes, the voltage loop adjusts its output to maintain the stability of the output voltage.
[0045] When the load state of the dual closed-loop buck circuit is switched from the first load state to the second load state, it is determined whether the output signal is less than the preset signal value, whether the second switch transistor is disconnected, and whether the output power is greater than the preset power value. The load amount of the first load state is greater than the load amount of the second load state. If the second switch transistor is disconnected and the output signal is less than the preset signal value, or the second switch transistor is disconnected and the output power is greater than the preset power value, the first switch transistor is controlled to be closed.
[0046] That is, in the present application, when the load condition of the dual closed-loop buck circuit is switched from the first load state to the second load state, condition A is to determine whether the second switch transistor is disconnected. If it is disconnected, it is considered that condition A is satisfied. Condition B is to determine whether the output power of the dual closed-loop buck circuit is greater than the preset power value. If the output power of the dual closed-loop buck circuit is greater than the preset power value, it is considered that condition B is satisfied. Condition C is to compare the output signal Ipi of the current loop with a fixed value, that is, the output signal Ipi of the current loop is compared with the preset signal value. If the output signal Ipi of the current loop is less than the preset signal value, it means that condition C is satisfied; if the output signal Ipi of the current loop is greater than the preset signal value, it means that condition C is not satisfied. Among them, the preset signal value can be a preset digital signal value.
[0047] The present application adds condition C, i.e., judging whether the output signal of the current loop is less than the preset signal value, so that the control logic of the first switch transistor, i.e., the lower tube, can be changed to (A and (B or C)). In this way, when the load suddenly changes, condition A is satisfied, condition B is not satisfied, but condition C is satisfied. At this time, the lower tube can be turned on to allow the charge on the output capacitor C1 to flow to the negative terminal through the inductor L, thereby discharging energy to the output capacitor C1, reducing the stabilization time, and improving the dynamic response of the dual closed-loop buck circuit 100. When the dual closed-loop buck circuit is in a steady state, if condition C is not satisfied all the time, the logical expression (A and (B or C)) described above is equivalent to (A and B).
[0048] Since the load amount of the first load state is greater than the load amount of the second load state, that is, the first load state is a heavy load state, and the second load state is a light load state or a no-load state. Figure 4 As shown, when the dual closed-loop buck circuit switches from heavy load to light load, the preset signal value can be -60. When the output signal Ipi of the current loop is -61, Ipi is less than -60. Therefore, it can be considered that condition C is satisfied at this time. Therefore, if it is judged that the second switch transistor 120 is in the off state at this time, it is considered that both condition A and condition C are satisfied. At this time, the first switch transistor 110 can be controlled to be turned on, so that the charge on the output capacitor C1 flows to the negative terminal through the inductor L, thereby dissipating energy to the output capacitor C1, reducing the stabilization time, and accelerating the dynamic response of the dual closed-loop buck circuit 100.
[0049] like Figure 5 As shown, when Ipi is less than -60, the corresponding signal output is 1 when the first switch transistor 110 is closed, and when Ipi is greater than or equal to -60, the corresponding signal output is 0 when the first switch transistor 110 is opened.
[0050] The preset power value may be set to 10% to 50% of the output power when the dual closed-loop buck circuit is in a steady state, and is not limited here.
[0051] Understandably, if Figure 6 As shown, since the working condition of the dual closed-loop buck circuit when switching from heavy load to light load is: when the load suddenly changes from heavy load to light load, the loop requires a certain response time, and the duty cycle will not suddenly drop to 0, but there is a process of gradually decreasing to 0. In this process, the current flowing into the output capacitor C1 of the dual closed-loop buck circuit 100 also gradually decreases until it reaches 0. The voltage of the output capacitor C1 increases, the output signal value of the voltage loop decreases, the output signal value of the current loop decreases at a faster rate, and the duty cycle of the upper tube quickly drops to 0. In the above working process, the charge on the output capacitor C1 has been increasing since the load was disconnected, and there is nowhere to release it. The present application adds condition C. Once the value of the output signal Ipi of the current loop is less than the preset signal value, the synchronous rectifier tube is turned on, allowing the charge on the output capacitor C1 to flow to the negative end of the dual closed-loop buck circuit 100 through the inductor L, thereby dissipating energy to the output capacitor C1, reducing the stabilization time, and accelerating the dynamic response of the dual closed-loop buck circuit 100.
[0052] Among them, see Figure 7 and Figure 8 The energy dissipation of the output capacitor C1 is reflected in the voltage Uo across the output capacitor C1 dropping from 50V to the initial normal voltage value of 48V. Figure 7 To add a condition C to determine the situation where the voltage of the output capacitor C1 drops to 48V when the first switch transistor 110 is turned on, Figure 8 This is the case where the voltage of the output capacitor C1 drops to 48V when the condition C is not added. Figure 7 The time taken for the voltage Uo to drop from 50V to 48V is significantly less than Figure 8 The time it takes for the voltage Uo to drop from 50V to 48V.
[0053] Therefore, the present application adds condition C. Once the value of the output signal Ipi of the current loop is less than the preset signal value, the synchronous rectifier is turned on to allow the charge on the output capacitor C1 to flow to the negative end of the dual closed-loop buck circuit 100 through the inductor L, thereby dissipating energy of the output capacitor C1, reducing the stabilization time and accelerating the dynamic response of the dual closed-loop buck circuit 100.
[0054] In this way, when the load state of the dual closed-loop buck circuit is switched from the first load state to the second load state, the logic control method of the present application can control the closing of the first switch transistor by adding a judgment on whether the output signal of the current loop is less than the preset signal value when the second switch transistor is in the off state and the output power of the dual closed-loop buck circuit is greater than the preset power value, thereby realizing the energy discharge of the output capacitor C1 in the dual closed-loop buck circuit 100, reducing the stabilization time, and accelerating the dynamic response of the dual closed-loop buck circuit 100.
[0055] In detail, the advantages of this control method are precisely described below in principle:
[0056] The mathematical expression of the current loop PI output value is as follows:
[0057] Ipi=(Iref-IL)*(kp2*s+Ki2) / s Formula 1
[0058] Iref = (Uref-Uo)*(kp1*s+Ki1) / s Formula 2
[0059] In the formula, Ipi is the current loop output value, Iref is the current target value, IL is the current value flowing through the inductor, kp2 and Ki2 are the PI parameters of the current loop respectively; Uref is the target value of the voltage loop, Uo is the circuit feedback value, kp1 and Ki1 are the PI parameters of the voltage loop respectively.
[0060] The dual closed-loop buck circuit in the digital power supply generally uses an average model as the controlled model, and the applicable conditions of the controlled model can be estimated by Shannon's sampling theorem. Assuming the switching frequency is Fs, the cutoff frequency of the current loop should be less than Fs / 2, so that the output signal of the current loop can be completely sampled by the carrier signal and converted into a duty cycle. For the sake of system stability, the cutoff frequency of the current loop is generally Fs / 10, which is a compromise choice that takes into account both the rapidity and stability of the system. Similarly, the voltage loop is used as an outer loop, and its cutoff frequency should also be less than 1 / 2 of the current loop cutoff frequency. Since the present invention is directly related to the output value of the current loop, the outer voltage loop will not be described in detail. For the entire dual closed-loop controlled BUCK, the speed of the current loop determines its dynamic response performance, and its current inner loop transfer function can be approximated as a first-order system:
[0061] G(s)=1 / (s / w+1)…………………Formula 3
[0062] W=2*3.14*Fs / 10………………Formula 4
[0063] When the inductor current is suddenly unloaded, it approximates an exponential function curve, that is, e -wt Energy is transferred to the output capacitor. According to the law of conservation of charge
[0064] ΔQ=ΔU*Co…………………Formula 5
[0065]
[0066] In the formula, ΔQ is the charge increment, ΔU is the voltage increment, and Co is the output capacitance of the circuit.
[0067] i(t) is the waveform function of the inductor current when the load is suddenly unloaded. As mentioned above, i(t) = e -ωt , t is the time from the start of sudden unloading to the current reaching 0. Let the two equations be equal, eliminate ΔQ, and ΔU can be obtained.
[0068] From the above, it can be seen that sudden unloading will cause voltage overshoot, and once the circuit PI parameters are selected, in the circuit, the amplitude difference ΔU of the peak or valley value of the output voltage waveform exceeding the set DC voltage is related to the loop response time t, the inductor current i(t) and the output capacitance Co, as shown in the following conditional formula:
[0069]
[0070] At this time, the output voltage overshoots to Uo+ΔU, and the voltage error signal Uerror is:
[0071] Uerror=Uref-Uo………………Formula 8
[0072] Among them, Uerror becomes a negative value, and then after the integration of the voltage loop PI, a rapidly decreasing Iref is obtained. Due to the inertia link of the current loop, the inductor current cannot suddenly change to 0, so Ierror = Iref-IL, and Ierror will decrease at a faster rate.
[0073] When Ierror enters the integral link of the PI of the current loop as input, the duty cycle will drop rapidly. At this time, although the duty cycle can drop to 0 quickly, the value of the output signal Ipi of the current loop can reach below 0.
[0074] The logic control method of the present application is to control when the value of the output signal Ipi of the current loop reaches below 0. First, after the duty cycle is 0, the second switch transistor 120 will no longer be closed, and the load end is disconnected. If the first switch transistor 110 is not closed, the output capacitor C1 is equivalent to an open circuit. In this way, the voltage Uo+ΔU accumulated on the output capacitor C1 will hardly be discharged, so the dynamic response of the dual closed-loop buck circuit is relatively slow.
[0075] The logic control method of the present application is to control when the value of the output signal Ipi of the current loop reaches below 0. By using the rapid decline of the output signal Ipi, a fixed preset signal value can be set to compare with the output signal Ipi. When the output signal Ipi is less than the preset signal value, the synchronous rectifier is closed so that the charge on the output capacitor C1 can be backflowed and discharged. Once the charge is discharged, the output voltage Uo of the output capacitor C1 will decrease, and the voltage loop will also work accordingly, forming an active hiccup working mode. The active hiccup working mode has a faster load shedding dynamic response. At the same time, because the current loop output value Ipi will not be less than the set fixed value during steady-state operation, that is, condition C is not satisfied, it is no different from the normal mode, taking into account the loss of the dual closed-loop buck circuit during steady-state operation.
[0076] See also Fig. 9 In some embodiments, step 03 includes:
[0077] 031: Prioritize determining whether the second switch transistor is in an off state;
[0078] 032: After determining that the second switch transistor is in the off state, determine whether the value of the output signal is greater than or equal to the preset signal value and determine whether the output power is greater than the preset power value.
[0079] See also Figure 3 , step 031 and step 032 can be implemented by the judgment module 13. The judgment module 13 is used to preferentially judge whether the second switch transistor is in the off state; after judging that the second switch transistor is in the off state, judge whether the value of the output signal is greater than or equal to the preset signal value and judge whether the output power is greater than the preset power value.
[0080] Specifically, since the second switch transistor 120 being in the off state is a necessary condition for controlling the closing of the first switch transistor 110, during the judgment process, it can be set to prioritize whether the second switch transistor 120 is in the off state, and then after determining that the second switch transistor 120 is in the off state, it is then possible to determine whether the value of the output signal is greater than or equal to the preset signal value and whether the output power is greater than the preset power value, so that a more accurate judgment result can be obtained.
[0081] In this way, the logic control method of the present application can preferentially determine whether the second switch transistor 120 is in the off state, and then determine whether the value of the output signal is greater than or equal to the preset signal value and whether the output power is greater than the preset power value. This can obtain a more accurate judgment result, facilitating more precise control of the first switch transistor 110.
[0082] See also Fig.10 In some embodiments, the logic control method includes:
[0083] 021: When the dual closed-loop buck circuit is in steady-state operation, the output voltage of the current loop is collected to obtain a sampled value of the output voltage;
[0084] 022: Use the sampled value of the output voltage as the preset signal value.
[0085] See also Fig.11 , the logic control device 10 further includes a determination module 12. Step 021 and step 022 can be implemented by the determination module 12. That is, the determination module 12 is used to collect the output voltage of the current loop when the double closed-loop buck circuit is in a steady state, obtain a sampled value of the output voltage, and use the sampled value of the output voltage as a preset signal value.
[0086] Specifically, when the dual closed-loop buck circuit is in steady-state operation, the output voltage of the current loop is collected to obtain a sampled value of the output voltage, and the sampled value of the output voltage is used as a preset signal value, that is, the output voltage value of the current loop when the dual closed-loop buck circuit is in steady state can be used as a feedforward quantity.
[0087] For example, when the dual closed-loop buck circuit is in steady-state operation, if the sampled value of the output voltage of the current loop is Figure 7 As shown, Uo=48V, the preset signal value as the feedforward value is 48. Specifically, since the output signal value of Ipi as the feedback amount and the preset signal value as the feedforward amount jointly determine the duty cycle of the pulse signal that drives the upper tube to turn on. When the dual closed-loop buck circuit 100 is suddenly unloaded, the load end no longer needs energy, so the dual closed-loop buck circuit 100 is required to no longer provide energy, that is, the duty cycle D of the upper tube is 0. According to the equation, the output signal value of Ipi+48=upper tube duty cycle*Vdc, Ipi+48=0, that is, Ipi+feedforward amount=0, then Ipi=-48. Therefore, the preset signal value can be -48.
[0088] In this way, the present application determines the preset signal value based on the sampled value of the output voltage of the current loop collected when the dual closed-loop buck circuit is in steady-state operation, so that a reference signal value can be introduced in the control process, so that when the dual closed-loop buck circuit is in the process of switching loads and generating fluctuations, the performance of the dual closed-loop buck circuit 100 can be better compensated and adjusted based on the preset signal value as the reference signal value.
[0089] See also Fig.12 In some embodiments, step 01 includes:
[0090] 011: Get the target current value of the voltage loop output and the current feedback value of the current loop actual output;
[0091] 012: The current error value is obtained according to the difference between the target current value and the current feedback value;
[0092] 013: After the current error value is input into the preset compensator for processing, an output signal is obtained.
[0093] Please combine Figure 3 Step 011, step 012 and step 013 can be implemented by the acquisition module 11, and the acquisition module 11 is used to obtain the target current value output by the voltage loop and the current feedback value actually output by the current loop; obtain the current error value according to the difference between the target current value and the current feedback value; input the current error value into the preset compensator for processing, and obtain the output signal.
[0094] Specifically, the preset compensator can be a proportional-integral controller, or other devices, which are not limited here. The PI compensator combines the proportional (P) and integral (I) control strategies to achieve precise adjustment of the system error, thereby optimizing the stability and control accuracy of the system.
[0095] It can be understood that since the present application first obtains the target current value of the voltage loop output and the current feedback value of the current loop actual output, and then obtains the current error value based on the difference between the target current value and the current feedback value, and then inputs the current error value into the preset compensator for processing to obtain the actual output signal of the current loop, the actual output signal of the current loop of the present application not only includes the information of the error signal, but also includes the adjustment strategy and effect of the PI compensator.
[0096] In this way, the present application can obtain in real time the actual output signal of the current loop in the dual closed-loop buck circuit 100 that changes with the load as a feedback quantity, compare the feedback quantity with the feedforward quantity, and obtain a comparison result to control whether to turn on the first switching transistor.
[0097] See also Fig.13 In some embodiments, the logic control method includes:
[0098] 07: After controlling the first switch transistor to close, determining in real time whether the output signal is greater than or equal to a preset signal value;
[0099] 09: If the output signal is greater than or equal to the preset signal value, the first switch transistor is controlled to be disconnected.
[0100] Please combine Figure 3 , step 07 can be implemented by the judgment module 13, and step 09 can be implemented by the control module 15. That is, the judgment module 13 is used to judge in real time whether the output signal is greater than or equal to the preset signal value after controlling the first switch transistor to close; the control module 15 is used to control the first switch transistor to be disconnected if the output signal is greater than or equal to the preset signal value.
[0101] That is, when the first switching transistor 110 is closed, the logic control method of the present application also needs to detect the output signal of the current loop in real time, and compare the output signal of the current loop with the preset signal value. When it is determined that the output signal of the current loop is greater than or equal to the preset signal value, it indicates that the dual closed-loop buck circuit is no longer in a fluctuating unstable state. Therefore, controlling the disconnection of the first switching transistor at this time can ensure the normal operation of the dual closed-loop buck circuit in the steady state.
[0102] In this way, the present application can control the disconnection timing of the first switch transistor by judging that the output signal of the current loop is greater than or equal to the preset signal value, thereby ensuring the normal operation of the dual closed-loop buck circuit in steady state.
[0103] In some embodiments, the logic control method includes:
[0104] 051: If the second switch transistor is in an off state and the output signal is less than a preset signal value, or the second switch transistor is off and the output power is greater than a preset power value, the control drives the first switch transistor to close with a preset switching cycle.
[0105] Please combine Figure 3 Step 05 can be implemented by the control module 15. The control module 15 is used to control the first switch transistor to be closed with a preset switching cycle if the second switch transistor is in an off state and the output signal is less than a preset signal value, or the second switch transistor is off and the output power is greater than a preset power value.
[0106] Specifically, the preset switching period may be a time period in which the first switching transistor is turned on and off.
[0107] like Figure 6 As shown, the preset switching period may be T1, and the value of T1 may be 0.0001S, 0.0002S or 0.0003S, which is not limited here. The switching period determines the frequency of closing and opening of the first switch transistor 110. A stable switching period helps ensure that the first switch transistor 110 can be reliably closed or opened when needed.
[0108] That is, the logic control method of the present application can drive the first switch transistor 110 to close at a preset switch period, thereby ensuring reliable closing of the first switch transistor 110 .
[0109] See also Fig.14 In some embodiments, the logic control method includes:
[0110] 06: After closing the first switch transistor, the voltage value across the output capacitor of the dual closed-loop buck circuit is obtained in real time;
[0111] 08: When the difference between the voltage value across the output capacitor and the voltage value when the dual closed-loop buck circuit is in steady-state operation is less than or equal to the preset difference, the disconnection time of the next preset switching cycle is controlled to be greater than the disconnection time of the previous preset switching cycle, and the disconnection time of the next preset switching cycle increases with the increase in the number of closing times of the first switching transistor.
[0112] Please combine Figure 3, step 06 can be implemented by the acquisition module 11, and step 08 can be implemented by the control module 15. That is, the acquisition module 11 is used to acquire the voltage value across the output capacitor of the dual closed-loop buck circuit in real time after closing the first switch transistor; the control module 15 is used to control the disconnection time of the next preset switch cycle to be greater than the disconnection time of the previous preset switch cycle when the difference between the voltage value across the output capacitor and the voltage value when the dual closed-loop buck circuit is in steady-state operation is less than or equal to the preset difference, and the disconnection time of the next preset switch cycle increases with the increase in the number of closing times of the first switch transistor.
[0113] Specifically, the preset difference value may be, for example, 0.1V, 0.2V, 0.3V, 0.4V, 0.5V, 0.6V, 0.7V, 0.8V or 0.9V, which is not limited here.
[0114] It can be understood that when the difference between the voltage value across the output capacitor C1 and the voltage value when the dual closed-loop buck circuit is in steady-state operation is less than or equal to the preset difference, it means that the energy accumulated in the output capacitor C1 has been released more. Therefore, there is no need to close and open the first switch transistor 110 more frequently at this time. The remaining energy in the output capacitor C1 can be slowly discharged. Therefore, the first switch transistor 110 can be closed again after being opened for a long time.
[0115] That is, in the logic control method of the present application, the closing time length of the first switch transistor 110 in the preset switching cycle can be fixed, and when the difference between the voltage value across the output capacitor C1 and the voltage value when the dual closed-loop buck circuit is in steady-state operation is less than or equal to the preset difference, the disconnection time length of the first switch transistor 110 in the preset switching cycle can increase with the increase in the number of closing times of the first switch transistor.
[0116] In this way, the logic control method of the present application can more reasonably control the closing and opening of the first switch transistor 110, so that the dual closed-loop buck circuit 100 can achieve a shorter stabilization time of the dual closed-loop buck circuit 100 and accelerate the dynamic response of the dual closed-loop buck circuit 100 with lower energy consumption.
[0117] The present application also provides a digital power supply. The digital power supply includes a dual closed-loop buck circuit and a logic control device of the above embodiment, the logic control device can perform logic control on and off of the first switch transistor in the dual closed-loop buck circuit, or the digital power supply is used to implement the logic control method in any one of the above embodiments.
[0118] In this way, the digital power supply of the present application applies the above-mentioned logic control method. When the load state of the dual closed-loop buck circuit is switched from the first load state to the second load state, by adding a judgment as to whether the output signal of the current loop is less than the preset signal value, the second switch transistor can be in the off state and the output power of the dual closed-loop buck circuit is greater than the preset power value, and the first switch transistor can be controlled to be closed, thereby realizing the energy discharge of the output capacitor C1 in the dual closed-loop buck circuit 100, reducing the stabilization time, and accelerating the dynamic response of the dual closed-loop buck circuit 100.
[0119] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A logic control method, applied to a dual closed-loop buck circuit of a digital power supply, characterized in that: The dual closed-loop buck circuit comprises a first loop consisting of a current loop and a second loop consisting of a voltage loop, the first loop is provided with a first switching transistor, and the second loop is provided with a second switching transistor; the logic control method comprises: Real-time detection of the load state of the dual closed-loop buck circuit, and acquisition of the output signal of the current loop, the shutdown state of the second switch transistor, and the output power of the dual closed-loop buck circuit; When the load state of the dual closed-loop buck circuit is switched from the first load state to the second load state, it is determined whether the output signal is less than a preset signal value, whether the second switch transistor is disconnected, and whether the output power is greater than a preset power value, and the load amount of the first load state is greater than the load amount of the second load state; If the second switch transistor is in an off state and the output signal is smaller than the preset signal value, or if the second switch transistor is in an off state and the output power is greater than the preset power value, the first switch transistor is controlled to be closed.
2. The logic control method according to claim 1, characterized in that: When the load condition of the dual closed-loop buck circuit is switched from the first load state to the second load state, judging whether the output signal is less than a preset signal value, judging whether the second switch transistor is disconnected, and judging whether the output power is greater than a preset power value, the load amount of the first load state is greater than the load amount of the second load state, including: Prioritizingly determining whether the second switch transistor is in an off state; After determining that the second switch transistor is in the off state, determining whether the value of the output signal is greater than or equal to the preset signal value and determining whether the output power is greater than a preset power value.
3. The logic control method according to claim 1, characterized in that: The logic control method comprises: When the dual closed-loop buck circuit is in steady-state operation, collecting the output voltage of the current loop to obtain a sampled value of the output voltage; The sampled value of the output voltage is used as the preset signal value.
4. The logic control method according to claim 1, characterized in that: The real-time acquisition of the output signal of the current loop comprises: Obtaining a target current value output by the voltage loop and a current feedback value actually output by the current loop; Obtaining a current error value according to a difference between the target current value and the current feedback value; After the current error value is input into a preset compensator for processing, the output signal is obtained.
5. The logic control method according to claim 4, characterized in that: The preset compensator is a proportional-integral compensator.
6. The logic control method according to claim 1, characterized in that: The logic control method comprises: After controlling the first switch transistor to close, determining in real time whether the output signal is greater than or equal to the preset signal value; If the output signal is greater than or equal to the preset signal value, the first switch transistor is controlled to be turned off.
7. The logic control method according to claim 1, characterized in that: The logic control method comprises: If the second switch transistor is in an off state and the output signal is less than the preset signal value, or the second switch transistor is off and the output power is greater than the preset power value, the first switch transistor is controlled to be closed with a preset switching cycle.
8. The logic control method according to claim 7, characterized in that: The logic control method comprises: After closing the first switch transistor, obtaining the voltage value across the output capacitor of the dual closed-loop buck circuit in real time; When the difference between the voltage value across the output capacitor and the voltage value when the dual closed-loop buck circuit is in steady-state operation is less than or equal to a preset difference, the disconnection time of the next preset switching cycle is controlled to be greater than the disconnection time of the previous preset switching cycle, and the disconnection time of the next preset switching cycle increases with the increase in the number of closing times of the first switching transistor.
9. A logic control device, characterized in that: A dual closed-loop buck circuit applied to a digital power supply, characterized in that the dual closed-loop buck circuit comprises a first loop consisting of a current loop and a second loop consisting of a voltage loop, a first switching transistor is provided on the first loop, and a second switching transistor is provided on the second loop; the logic control device comprises: An acquisition module, used for detecting the load state of the dual closed-loop buck circuit in real time, and acquiring the output signal of the current loop, the turn-off state of the second switch transistor, and the output power of the dual closed-loop buck circuit; a judgment module, used for judging whether the output signal is less than a preset signal value, judging whether the second switch transistor is disconnected, and judging whether the output power is greater than a preset power value when the load state of the dual closed-loop buck circuit is switched from a first load state to a second load state, and the load amount of the first load state is greater than the load amount of the second load state; and The control module is used to control the closing of the first switch transistor if the second switch transistor is in an off state and the output signal is less than the preset signal value, or the second switch transistor is in an off state and the output power is greater than the preset power value.
10. A digital power supply, characterized in that: The digital power supply includes a dual closed-loop buck circuit and the logic control device described in claim 9, and the logic control device can perform logic control on the closing and opening of the first switching transistor in the dual closed-loop buck circuit, or the digital power supply is used to implement the logic control method described in claims 1 to 8.