Rapid oscillation starting device for active crystal oscillator

Abstract

The invention relates to a rapid oscillation starting device for an active crystal oscillator, belongs to the technical field of crystal oscillators, and solves the problems that an oscillation starting circuit of a crystal oscillator in the prior art needs long time and is complex in design. The rapid oscillation starting device comprises an LC-DCO used for generating an output frequency signal according to an output control word of a phase difference control circuit; the phase difference control circuit is used for receiving a reference frequency signal output by the active crystal oscillator and an output frequency signal of the LC-DCO, calculating an overall phase difference of the two frequency signals, generating an output control word according to the overall phase difference, and sending the output control word to the LC-DCO; the total phase difference comprises integer phase difference and decimal phase difference; and the energy injection circuit receives the output frequency signal generated by the LC-DCO, and performs energy injection on the active crystal oscillator according to the output frequency signal, so that the active crystal oscillator quickly outputs a stable reference frequency signal. Rapid oscillation starting of the active crystal oscillator is achieved, and meanwhile rapid locking of the all-digital phase-locked loop is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of crystal oscillators, and in particular to a fast oscillation starting device for an active crystal oscillator. Background Art

[0002] With the rapid development of Internet of Things technology, low-power wireless sensor nodes and wearable devices are widely used in various fields such as military industry and biomedicine. These wearable devices and sensor nodes are usually small and easy to carry. They are usually powered by batteries and can work for a long time, which places very high demands on the low power consumption of chips. In order to reduce chip power consumption, the chip not only needs to consume as little power as possible when working, but also needs to be in a very low-power sleep mode when idle. Therefore, the use of the periodic (Duty-Cycle) working mode can well meet the low power consumption requirements of the chip. The system in the Duty-Cycle working mode is in a very low-power sleep state most of the time, and it will only be turned on briefly when and only when the system transmits or receives data, that is, in the active mode. The wireless sensor node system periodically switches between the sleep and active states, which can greatly reduce the average power consumption of the system.

[0003] The low-power transmitter on the wireless sensor node not only needs the transmitter to provide accurate modulation signal frequency, but also needs to meet the low-power operation of the transmitter in the duty-cycle mode. Therefore, the transmitter clock frequency source generation circuit with high precision and low power consumption has become the key in the low-power transmitter.

[0004] However, if the crystal oscillator is not driven by an auxiliary startup circuit, it will take hundreds of microseconds or even milliseconds for the crystal oscillator to output a stable frequency signal. This will cause the startup time of the crystal oscillator to occupy the vast majority of the entire Duty-Cycle mode cycle. In this mode, including the sleep state and the active mode, the energy consumption in the cycle is increased, significantly reducing the energy efficiency ratio of the cycle.

[0005] Therefore, there is an urgent need for a fast starting circuit for a crystal oscillator. Summary of the invention

[0006] In view of the above analysis, an embodiment of the present invention aims to provide a fast starting device for an active crystal oscillator, so as to solve the problem in the prior art that the starting circuit of the crystal oscillator requires a long time and has a complex design.

[0007] The embodiment of the present invention provides a fast oscillation starting device for an active crystal oscillator, the fast oscillation starting device comprising an energy injection circuit, an LC-DCO oscillator based on an inductor-capacitor resonance digital control, and a phase difference control circuit;

[0008] LC-DCO, used for generating an output frequency signal according to an output control word of a phase difference control circuit;

[0009] The phase difference control circuit is used to receive the reference frequency signal output by the active crystal oscillator and the output frequency signal of the LC-DCO, calculate the overall phase difference between the two frequency signals, generate an output control word according to the overall phase difference and send it to the LC-DCO; the overall phase difference includes an integer phase difference and a fractional phase difference;

[0010] The energy injection circuit receives the output frequency signal generated by the LC-DCO and injects energy into the active crystal oscillator according to the output frequency signal, so that the active crystal oscillator can quickly output a stable reference frequency signal.

[0011] Based on the further improvement of the above-mentioned fast oscillation device, the phase difference control circuit includes a phase difference acquisition circuit and a digital filter circuit;

[0012] The phase difference acquisition circuit is used to receive the reference frequency signal output by the active crystal oscillator and the output frequency signal of the LC-DCO, and calculate the overall phase difference;

[0013] The digital filter circuit is used to determine the control mode of the LC-DCO according to the overall phase difference, and to generate a corresponding output control word according to the control mode to control the LC-DCO.

[0014] Based on the further improvement of the above-mentioned fast oscillation device, the phase difference acquisition circuit includes a retiming circuit, an accumulator, a frequency detector, a phase detector, a radio frequency counter and an embedded digital converter TDC circuit;

[0015] A retiming circuit provides a working clock for an accumulator, a frequency detector, a phase detector, a radio frequency counter and an embedded TDC circuit according to a reference frequency signal;

[0016] An accumulator accumulates the preset frequency division ratio to obtain the sum PHR of the integer phases of the reference frequency signal before the current clock;

[0017] The radio frequency counter accumulates and counts the integer phases of the output frequency signal to obtain the sum PHV of the integer phases of the output frequency signal before the current clock;

[0018] An embedded TDC circuit determines a fractional phase difference PHF between a reference frequency signal and an output frequency signal of a current clock;

[0019] The phase frequency detector is used to calculate the overall phase difference according to the integer phase sum PHR of the reference frequency signal before the current clock, the integer phase sum PHV of the output frequency signal before the current clock and the fractional phase difference PHF.

[0020] Based on the further improvement of the above-mentioned fast oscillation device, the digital filter circuit includes a mode control module, and the mode control module is used to perform the following steps:

[0021] Compare the overall phase difference of the current clock with the overall phase difference of the previous clock to determine whether the mode switching condition is met;

[0022] When the mode switching condition is met, the control mode of the LC-DCO is switched to the fine adjustment mode; otherwise, the control mode of the LC-DCO is the coarse adjustment mode.

[0023] Based on the further improvement of the above-mentioned fast oscillation device, the digital filter circuit further includes a frequency control module, and the frequency control module is used to perform the following steps:

[0024] In the coarse adjustment mode, a 1-level dynamic loop bandwidth adjustment operation is added to lock with a larger bandwidth;

[0025] In fine tuning mode, a 2-stage dynamic loop bandwidth adjustment operation is added to lock at a lower bandwidth.

[0026] Based on the further improvement of the above-mentioned fast oscillation device, the phase difference acquisition circuit further includes a selector, and the selector includes a coarse adjustment path input terminal and a fine adjustment path input terminal;

[0027] In the coarse tuning mode, the selector directly receives the output frequency signal of the current clock through the coarse tuning path input terminal and transmits it to the RF counter;

[0028] In the fine tuning mode, the embedded TDC circuit receives the output frequency signal of the current clock, and transmits the output frequency signal of the current clock to the RF counter through the fine tuning path input terminal of the selector.

[0029] Based on the further improvement of the above-mentioned fast oscillation device, the embedded TDC circuit includes a ring oscillator RO and N independent D flip-flops, and the RO includes N pseudo-differential structures cascaded in sequence; each pseudo-differential structure corresponds to a D flip-flop;

[0030] The two input ends of the first pseudo differential structure receive the output frequency signal of the current clock through differential, and the two output ends of each pseudo differential structure are respectively connected to the two input ends of the corresponding D flip-flop;

[0031] The rising edge sampling ports of each D flip-flop are connected to each other and receive the reference frequency signal together;

[0032] The two output signals of each D flip-flop are transmitted to a TDC encoder, and the TDC encoder encodes the output signals of the N D flip-flops to obtain a fractional phase difference, and sends it to a frequency detector and a phase detector.

[0033] Based on the further improvement of the above-mentioned fast oscillation device, the embedded TDC circuit further includes a current-controlled digital-to-analog converter IDAC circuit, and the IDAC circuit is respectively connected to the power supply voltage port of each pseudo-differential structure;

[0034] In the fine tuning mode, the IDAC circuit is used to receive the output control word of the digital filter circuit, and the output control word is used to adjust the RO so that its frequency is the same as the frequency of the output frequency signal of the LC-DCO, thereby performing injection locking.

[0035] Based on the further improvement of the above-mentioned fast oscillation starting device, the energy injection circuit includes a programmable frequency divider, a duty cycle modulation circuit and a delay selection circuit;

[0036] A programmable frequency divider is used to receive an output frequency signal from the LC-DCO and divide the frequency according to a preset frequency division ratio to obtain a reference frequency signal;

[0037] The duty cycle modulation circuit performs duty cycle modulation on the divided reference frequency signal so that the duty cycle reaches 50% to obtain a modulated signal;

[0038] The delay selection circuit is used to perform delay control according to the modulated signal and inject energy into the active crystal oscillator.

[0039] Based on the further improvement of the above-mentioned rapid oscillation device, N=6.

[0040] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0041] 1. The overall phase difference between the reference frequency signal and the output frequency signal is determined by the phase difference control circuit to generate an output control word. The LC-DCO generates an output frequency signal according to the output control word. The energy injection circuit receives the output frequency signal generated by the LC-DCO and injects energy into the active crystal oscillator according to the output frequency signal, so that the active crystal oscillator can quickly output a stable reference frequency signal.

[0042] 2. The fractional phase difference PHF between the reference frequency signal and the output frequency signal of the current clock is determined by the embedded TDC circuit, so that a more accurate overall phase difference is provided when entering the fine adjustment mode, so that the LC-DCO can be controlled to obtain an accurate output frequency signal more quickly.

[0043] 3. The mode control module determines whether the mode switching conditions are met to provide more precise control for the frequency of the LC-DCO. In the coarse adjustment mode, a 1-level dynamic loop bandwidth adjustment operation is added to lock with a larger bandwidth; in the fine adjustment mode, a 2-level dynamic loop bandwidth adjustment operation is added to lock with a lower bandwidth, so that the digital phase-locked loop can achieve faster locking.

[0044] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0046] Figure 1 A schematic structural diagram of a fast oscillation starting device for an active crystal oscillator provided in an embodiment of the present invention;

[0047] Figure 2 A schematic diagram of a structure in which a level 1 dynamic loop bandwidth adjustment operation is added in a coarse adjustment mode provided by an embodiment of the present invention;

[0048] Figure 3 A structural schematic diagram of adding a 2-level dynamic loop bandwidth adjustment operation in the fine adjustment mode provided by an embodiment of the present invention;

[0049] Figure 4 A schematic diagram of the structure of an embedded TDC circuit provided by an embodiment of the present invention;

[0050] Figure 5 A schematic diagram of the stages of quickly starting an active crystal oscillator by a fast oscillation starting device for an active crystal oscillator provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0052] The research on crystal oscillator fast start-up circuit based on energy injection technology has become a hot topic. Energy injection technology is mainly a constant frequency injection technology, which usually uses digital calibration technology or phase-locked loop-based methods to generate accurate frequency signals. However, these methods require integrating an additional low-frequency phase-locked loop on the basis of the overall crystal oscillator circuit or introducing additional oscillators and digital calibration circuits. The role of the crystal oscillator is not considered from the specific application aspect, which makes the design of low-power transmitters based on duty-cycle mode complicated.

[0053] A specific embodiment of the present invention discloses a fast oscillation starting device for an active crystal oscillator, such as Figure 1As shown, the fast oscillation device includes an energy injection circuit, an LC-DCO oscillator based on an inductor-capacitor resonance digital control, and a phase difference control circuit;

[0054] LC-DCO, used for generating an output frequency signal according to an output control word of a phase difference control circuit;

[0055] The phase difference control circuit is used to receive the reference frequency signal output by the active crystal oscillator and the output frequency signal of the LC-DCO, calculate the overall phase difference between the two frequency signals, generate an output control word according to the overall phase difference and send it to the LC-DCO; the overall phase difference includes an integer phase difference and a fractional phase difference;

[0056] The energy injection circuit receives the output frequency signal generated by the LC-DCO and injects energy into the active crystal oscillator according to the output frequency signal, so that the active crystal oscillator can quickly output a stable reference frequency signal.

[0057] Specifically, Figure 1 As shown, the active crystal oscillator is used to output a reference frequency signal, and the reference frequency signal is input to the phase difference control circuit through a buffer. The buffer converts the sinusoidal signal output by the active crystal oscillator into a square wave signal, which is convenient for subsequent processing by the phase difference control circuit.

[0058] As a circuit for stabilizing the output signal of the crystal oscillator, the active crystal oscillator needs hundreds of microseconds or even milliseconds to output a stable frequency signal without the drive of an auxiliary circuit. This will cause the startup time of the active crystal oscillator to occupy most of the entire Duty-Cycle mode cycle, increasing the energy consumption within the cycle and significantly reducing the energy efficiency ratio of the cycle.

[0059] The reference frequency signal output by the active crystal oscillator is input into the phase difference control circuit provided in the embodiment of the present invention. The phase difference control circuit is used to calculate the reference frequency signal and the output frequency signal of the LC-DCO (Resonant Capacitor-based Digital Control Oscillator, an oscillator based on inductor-capacitor resonance type digital control), calculate the overall phase difference between the two frequency signals, generate a control word and send it to the LC-DCO. The LC-DCO generates an output frequency signal according to the output control word of the phase difference control circuit. The energy injection circuit receives the output frequency signal generated by the LC-DCO, and injects energy into the active crystal oscillator according to the output frequency signal, so that the active crystal oscillator quickly outputs a stable reference frequency signal.

[0060] It is understandable that the quartz crystal included in the active crystal oscillator can be designed according to the specific reference frequency signal required, so that when the quartz crystal resonates, the active crystal oscillator can continuously output a stable reference frequency signal. For example, when the reference frequency signal is 32MHz, when the active crystal oscillator is quickly started, the LC-DCO can output an output frequency signal with an accurate preset frequency division ratio, such as 2.4GHz, and the preset frequency division ratio is 75.

[0061] Specifically, the active crystal oscillator can use a Pierce oscillator as a circuit to stabilize the output signal of the crystal oscillator, while maintaining the crystal oscillator output signal, the power consumption is less than 70uW, which is very suitable for low-power applications.

[0062] Specifically, the fast oscillation starting device of the active crystal oscillator provided in the embodiment of the present invention can be used in a low-power Bluetooth transmitter in a duty-cycle working mode so that the crystal oscillator can start oscillating quickly to provide an accurate reference clock frequency source.

[0063] Preferably, the phase difference control circuit includes a phase difference acquisition circuit and a digital filter circuit;

[0064] The phase difference acquisition circuit is used to receive the reference frequency signal output by the active crystal oscillator and the output frequency signal of the LC-DCO, and calculate the overall phase difference;

[0065] The digital filter circuit is used to determine the control mode of the LC-DCO according to the overall phase difference, and to generate a corresponding output control word according to the control mode to control the LC-DCO.

[0066] Preferably, the phase difference acquisition circuit comprises a retiming circuit, an accumulator, a frequency and phase detector, a radio frequency counter and an embedded digital converter TDC circuit;

[0067] A retiming circuit provides a working clock for an accumulator, a frequency detector, a phase detector, a radio frequency counter and an embedded TDC circuit according to a reference frequency signal;

[0068] An accumulator accumulates the preset frequency division ratio to obtain the sum PHR of the integer phases of the reference frequency signal before the current clock;

[0069] The radio frequency counter accumulates and counts the integer phases of the output frequency signal to obtain the sum PHV of the integer phases of the output frequency signal before the current clock;

[0070] An embedded TDC circuit determines a fractional phase difference PHF between a reference frequency signal and an output frequency signal of a current clock;

[0071] The phase frequency detector is used to calculate the overall phase difference according to the integer phase sum PHR of the reference frequency signal before the current clock, the integer phase sum PHV of the output frequency signal before the current clock and the fractional phase difference PHF.

[0072] Specifically, Figure 1 As shown, the phase difference control circuit includes a phase difference acquisition circuit and a digital filter circuit. The phase difference acquisition circuit includes a retiming circuit, an accumulator, a frequency detector, a phase detector, a radio frequency counter and an embedded digital converter TDC circuit.

[0073] Specifically, Figure 1 As shown, the retiming circuit can receive a reference frequency signal, and provide a working clock for the accumulator, the frequency detector, the RF counter and the embedded TDC circuit according to the frequency of the reference frequency signal. For example, when the reference frequency signal output is a high level, the accumulator works once, and the value obtained by the accumulator is related to the preset frequency division ratio and the working clock. When it is the first clock, the accumulator obtains 75, when it is the second clock, the accumulator obtains 75*2, and when it is the Nth clock, the accumulator obtains 75*N, and the obtained value is output to the frequency detector as the sum of integer phases of the reference frequency signal before the current clock PHR. At the same time, when the reference frequency signal output is a high level, the RF counter outputs the sum of integer phases of the output frequency signal before the current clock PHV accumulated to the frequency detector, and the embedded TDC circuit outputs the fractional phase difference PHF between the reference frequency signal and the output frequency signal of the current clock to the frequency detector. In addition, when the reference frequency signal output is a high level, the frequency detector calculates the overall phase difference.

[0074] It is understandable that if Figure 1 As shown, the RF counter starts timing from the system startup, and the obtained value can be regarded as the integer phase sum PHV of the output frequency signal before the current clock. The accumulator starts timing from the system startup and accumulates according to the preset division ratio. The obtained value can be regarded as the integer phase sum PHR of the reference frequency signal before the current clock. The embedded TDC circuit receives the output frequency signal and the reference frequency signal from the LC-DCO and calculates the fractional phase difference PHF.

[0075] It can be understood that the phase difference control circuit actually constitutes a full digital phase-locked loop. When the digital signal of the phase error output by the phase frequency detector is equal to 0 or a constant, the full digital phase-locked loop is locked and the full digital phase-locked loop outputs a stable frequency, that is, the LC-DCO outputs an accurate and stable output frequency signal. Preferably, the digital filter circuit includes a mode control module, which is used to perform the following steps:

[0076] Compare the overall phase difference of the current clock with the overall phase difference of the previous clock to determine whether the mode switching condition is met;

[0077] When the mode switching condition is met, the control mode of the LC-DCO is switched to the fine adjustment mode; otherwise, the control mode of the LC-DCO is the coarse adjustment mode.

[0078] Preferably, the digital filter circuit further includes a frequency control module, and the frequency control module is used to perform the following steps:

[0079] In the coarse adjustment mode, a 1-level dynamic loop bandwidth adjustment operation is added to lock with a larger bandwidth;

[0080] In fine tuning mode, a 2-stage dynamic loop bandwidth adjustment operation is added to lock at a lower bandwidth.

[0081] Specifically, Figure 1 As shown, under the control of the retiming circuit, the frequency detector outputs the obtained overall phase difference to the digital filter circuit. The digital filter circuit determines the control mode of the LC-DCO according to the overall phase difference, and generates a corresponding output control word according to the control mode to control the LC-DCO.

[0082] It is worth noting that the digital filter can increase and decrease the bandwidth. The way to adjust the bandwidth is to shift the digital signal to the left to increase it and to the right to decrease it. In the process of coarse and fine adjustment, the bandwidth can be increased by shifting the digital bit to the left. The larger the bandwidth, the faster the locking speed.

[0083] It can be understood that the overall phase difference under different clocks is continuously saved in the mode control module. By comparing the integer phase differences under two adjacent clocks, the signal frequency accuracy of the output frequency signal of the LC-DCO can be continuously obtained. When modulating the LC-DCO, coarse adjustment mode and fine adjustment mode can be used.

[0084] At the beginning of modulation, the coarse adjustment mode is used to modulate the LC-DCO. At this time, only the integer phase difference is counted. When the integer phase difference meets the mode switching condition, the coarse adjustment mode is switched to the fine adjustment mode. In the fine adjustment mode, the integer phase difference and the fractional phase difference are counted to obtain a more accurate overall phase difference.

[0085] Specifically, in the coarse adjustment mode, a 1-stage dynamic loop bandwidth adjustment (Gear-shifting) operation is added to lock with a larger bandwidth; in the fine adjustment mode, a 2-stage dynamic loop bandwidth adjustment (Gear-shifting) operation is added to lock with a lower bandwidth.

[0086] It is worth noting that the digital filter includes two branches, such as Figure 2 The figure shows a coarse adjustment branch; in the coarse adjustment mode, the phase error, that is, the overall phase difference, is shifted once, and the original bandwidth is introduced into the 1st gear-shifting operation to obtain the 1st gear-shifting bandwidth, and a bandwidth adjustment is performed, and the phase error before the shift is input to the 0 port of the two-to-one selector, and the phase error after the shift is input to the adder and the subtractor; in the subtractor, the phase error before the shift and the phase error after the shift are subtracted, and the phase error before the shift is subtracted from the phase error after the shift to obtain the subtractor output signal, the subtractor output signal is input to the D flip-flop, and the D flip-flop output signal is input to the adder; in the adder, the shifted phase error and the D flip-flop output signal are operated, and the two are added to obtain the adder output signal, and the adder output signal is input to the 1 port of the two-to-one selector, and the two-to-one selector outputs a control word to modulate the output frequency signal of the LC-DCO to change the frequency of the output frequency signal of the LC-DCO.

[0087] It is understandable that the loop bandwidth of the phase-locked loop is large in order to be able to approach the target frequency faster, but at the expense of increased loop phase noise.

[0088] It is worth noting that if Figure 3 As shown in FIG. 1 , it is the fine adjustment branch of the digital filter. In the fine adjustment mode, the phase error is locked with a lower bandwidth by adding a 2-stage gear-shifting operation through two shift operations. Specifically, the phase error before the shift is directly input to the 00 port of the three-selection selector. Figure 3As shown, the phase error after one shift is input to the first adder and the first subtractor; at the same time, the phase error after the first shift is shifted for the second time to obtain the phase error after the second shift, and the phase error after the second shift is input to the second adder and the second subtractor; in the first subtractor, the phase error before the shift is subtracted from the phase error after the first shift to obtain the output signal of the first subtractor, the output signal of the first subtractor is input to the first D flip-flop, and the output signal of the first D flip-flop is transmitted to the first adder; in the first adder, the output signal of the first D flip-flop is added to the phase error after the first shift to obtain the output signal of the first adder; the output signal of the first adder is directly output to one of three selectors. The 01 port of the selector is output to the second subtractor; in the second subtractor, the output signal of the first adder is added with the phase error after the second shift to obtain the output signal of the second subtractor, and the output signal of the second subtractor is input to the second D flip-flop, and the output signal of the second D flip-flop is input to the second adder; in the second adder, the output signal of the second D flip-flop is added with the phase error after the second shift to obtain the output signal of the second adder, and finally input to the 1x port of the three-to-one selector; finally, the three-to-one selector controls the frequency of the output frequency signal of the LC-DCO by outputting a control word, and the phase-locked loop maintains and tracks the precise target frequency, which will increase the locking time but reduce the phase noise of the loop.

[0089] It can be understood that the Gear-shifting operation can reduce the locking time and effectively suppress loop noise by dynamically controlling the bandwidth.

[0090] Preferably, if Figure 1 As shown, the phase difference acquisition circuit further includes a selector, and the selector includes a coarse adjustment path input terminal and a fine adjustment path input terminal;

[0091] In the coarse tuning mode, the selector directly receives the output frequency signal of the current clock through the coarse tuning path input terminal and transmits it to the RF counter;

[0092] In the fine tuning mode, the embedded TDC circuit receives the output frequency signal of the current clock, and transmits the output frequency signal of the current clock to the RF counter through the fine tuning path input terminal of the selector.

[0093] Specifically, Figure 1As shown, in the coarse adjustment mode and the fine adjustment mode, different paths are used to obtain the sum of the integer phases of the output reference frequency signal, and the coarse adjustment path and the fine adjustment path are designed respectively. In the coarse adjustment mode, the selector directly receives the output frequency signal of the current clock through the coarse adjustment path input terminal and transmits it to the RF counter; in the fine adjustment mode, the embedded TDC circuit receives the output frequency signal of the current clock, and transmits the output frequency signal of the current clock to the RF counter through the fine adjustment path input terminal of the selector.

[0094] It can be understood that the coarse adjustment mode is used to lock the frequency. In the coarse adjustment mode, the locking bandwidth is relatively large. The purpose is to increase the locking range of the phase-locked loop so that the output frequency of the phase-locked loop is close to the target frequency. In the coarse adjustment mode, there is no embedded TDC circuit involved, only the integer phase difference parameter is locked. After entering the fine adjustment mode, the embedded TDC circuit begins to adjust RO so that its frequency gradually approaches the frequency of LC-DCO, reducing the injection locking bandwidth and saving injection current. Since RO is injection locked by LCDCO, it can be known from the injection locking related theory that the phase noise of RO has no effect on the phase noise contribution of the output of the full digital phase-locked loop. When the RO adjustment stage is over, the full digital phase-locked loop enters the fine adjustment mode, and the embedded TDC provides a fractional phase error. The frequency resolution in this state is the smallest and the bandwidth is the lowest, and it is closer to the target frequency after locking.

[0095] Preferably, if Figure 4 As shown, the embedded TDC circuit includes a ring oscillator RO and N independent D flip-flops, and the RO includes N pseudo-differential structures cascaded in sequence; each pseudo-differential structure corresponds to a D flip-flop;

[0096] The two input ends of the first pseudo differential structure receive the output frequency signal of the current clock through differential, and the two output ends of each pseudo differential structure are respectively connected to the two input ends of the corresponding D flip-flop;

[0097] The rising edge sampling ports of each D flip-flop are connected to each other and receive the reference frequency signal together;

[0098] The two output signals of each D flip-flop are transmitted to a TDC encoder, and the TDC encoder encodes the output signals of the N D flip-flops to obtain a fractional phase difference, and sends it to a frequency detector and a phase detector.

[0099] Specifically, Figure 1 As shown, in the fine tuning mode, the embedded TDC circuit receives the output frequency signal of the LC-DCO.

[0100] like Figure 4As shown, the output frequency signal of the LC-DCO is output to the embedded TDC circuit through differential output, the two input ends of the pseudo-differential structure receive the output frequency signal of the current clock, the rising edge sampling port of the D flip-flop receives the reference frequency signal, and the two output signals of the D flip-flop are transmitted to the TDC encoder. The TDC encoder encodes the output signals of N D flip-flops to obtain the fractional phase difference and sends it to the frequency detector and phase detector.

[0101] Specifically, Figure 4 As shown, one output end of the pseudo differential structure is connected to the fine adjustment path of the two-to-one selector and output to the RF counter. At this time, the RF counter counts the output frequency signal passing through the embedded TDC circuit.

[0102] Preferably, if Figure 4 As shown, the embedded TDC circuit further includes a current-controlled digital-to-analog converter IDAC circuit, and the IDAC circuit is respectively connected to the power supply voltage port of each pseudo-differential structure;

[0103] In the fine tuning mode, the IDAC circuit is used to receive the output control word of the digital filter circuit, and the output control word is used to adjust the RO so that its frequency is the same as the frequency of the output frequency signal of the LC-DCO, thereby performing injection locking.

[0104] In the fully digital phase-locked loop circuit, a ring oscillator (RO) is used to form an embedded TDC circuit. Each stage of the RO is used as a delay unit of the TDC. The oscillation cycle of a RO is divided into different phases as the delay signal of the TDC, which saves the TDC normalization step. The Gear-shifting operation is connected to the digital filter circuit, which can greatly shorten the locking time of the fully digital phase-locked loop. The ring oscillator is injection locked using an inductor-capacitor resonant digital control oscillator (LC-based Digital Control Oscillator, LC-DCO) to improve the RO phase noise and meet the transmitter performance requirements.

[0105] Specifically, Figure 4 As shown, N=6, a pseudo differential structure provides two outputs, a total of 12 outputs, the phases of these 12 outputs are different, and these 12 outputs are connected to the two ends of the D flip-flop, which is composed of a sensitive amplifier. Each D flip-flop has two input terminals and two output terminals, and there are a total of 6 D flip-flops of this type. The level of the input signal at both ends of the D flip-flop is collected through the rising edge of the reference frequency signal. The result is output to the TDC encoder through the two output Q terminals of the D flip-flop, and the collected 12-bit output is encoded into binary and evenly distributed between 0 and 1 to produce a decimal error.

[0106] In addition, since each output end of the RO is very sensitive to parasitic capacitance, the same buffer needs to be added to each output to ensure that the load capacitance at each end is consistent. At the same time, the layout design of the RO must also be very careful to reduce unnecessary parasitic capacitance.

[0107] Preferably, if Figure 1 As shown, the energy injection circuit includes a programmable frequency divider, a duty cycle modulation circuit and a delay selection circuit;

[0108] A programmable frequency divider is used to receive an output frequency signal from the LC-DCO and divide the frequency according to a preset frequency division ratio to obtain a reference frequency signal;

[0109] The duty cycle modulation circuit performs duty cycle modulation on the divided reference frequency signal so that the duty cycle reaches 50% to obtain a modulated signal;

[0110] The delay selection circuit is used to perform delay control according to the modulated signal and inject energy into the active crystal oscillator.

[0111] Specifically, the duty cycle modulation circuit and the programmable frequency divider divide the output frequency signal of the LC-DCO and modulate the divided frequency signal into an injection signal of a precise frequency with a duty cycle of 50%, so that the active crystal oscillator starts oscillating quickly.

[0112] Specifically, the duty cycle of the output signal of the programmable frequency divider is not 50%. The signal needs to be modulated to a 50% duty cycle through a duty cycle modulation circuit to generate an accurate energy signal that can be injected into the crystal oscillator, and the power consumption of the duty cycle modulation circuit is less than 100uW. It can be understood that the duty cycle modulation circuit includes a duty cycle modulator, a single-ended differential circuit and an operational transconductance amplifier. The duty cycle modulation circuit is composed of a waveform duty cycle modulation circuit based on an inverter, and the size of the duty cycle controls the position of the rising and falling edges of the waveform by controlling the voltage. The function of the single-ended differential circuit is to steepen the rising and falling edges of the waveform output by the duty cycle modulation circuit and generate a pair of fully differential signals. The function of the operational transconductance amplifier is to detect the deviation between the duty cycle of this pair of differential signals and the 50% duty cycle, and then generate a voltage through a capacitor to form a negative feedback control duty cycle modulation circuit to further adjust the duty cycle until the duty cycle reaches 50%.

[0113] It is worth noting that if Figure 5 As shown, the active crystal oscillator is quickly started using the fast oscillation device for the active crystal oscillator provided by the embodiment of the present invention, which includes four stages.

[0114] In the first stage, the LC-DCO is injected in an open loop. At this time, the LC-DCO works in an open loop, so the frequency is relatively rough. The main purpose is to allow both ends of the quartz crystal (active crystal oscillator) to generate a reference frequency signal that can be sensed by the buffer. At this time, the voltage amplitude of the reference frequency signal is relatively small and unstable, but because it can be sensed by the buffer and amplified into a square wave reference frequency signal, it can be used to lock the fully digital phase-locked loop in the second stage. In the first stage, the LC-DCO is open-loop, which can oscillate a relatively accurate frequency signal near 2.4GHz. Then, by configuring the programmable divider, its division ratio is 75. The divided signal frequency is 32MHz (the series resonant frequency of the quartz crystal), but the duty cycle of the signal is not 50%. The duty cycle modulation circuit can modulate an injection signal with a duty cycle of 50%. The purpose is to inject a relatively accurate frequency signal (<5000ppm) into the quartz crystal. Since the frequency signal is still far from the series resonant frequency of the quartz crystal, the internal current of the quartz crystal can only reach about 100uA, and the crystal oscillator cannot reach a stable state (the internal current of the quartz crystal I M However, the oscillating voltage across the quartz crystal can be sensed by the buffer to generate a relatively accurate square wave reference frequency signal. Since the quartz crystal is still not stable at this time, the reference frequency signal can only be maintained for about 10us. However, this signal is sufficient to lock the full digital phase-locked loop as the reference frequency signal of the phase-locked loop.

[0115] The second stage is the fully digital phase-locked loop locking stage (about 6us). In this stage, the frequency of the reference frequency signal generated in the first stage is used as the reference frequency. Combined with the fast locking of the fast starting device for the active crystal oscillator provided in the embodiment of the present invention, the fully digital phase-locked loop is locked to a precise target frequency. This frequency can be used as a modulation signal for sending data, and can also be used through a programmable divider and a duty cycle modulation circuit to generate an energy injection signal with a precise frequency and a duty cycle of 50%.

[0116] The third stage is the precise frequency injection stage (about 10us). In this stage, the precise frequency energy injection signal obtained in the second stage is injected into the quartz crystal to make it oscillate quickly. In this stage, the internal current of the quartz crystal can quickly increase to about 500uA (greater than 90% of the steady-state current) to reach a stable condition, and the energy consumption in this stage is only 13nJ.

[0117] The fourth stage is the crystal oscillator stabilization stage, which mainly stabilizes the output of the crystal oscillator through the Pierce oscillator to provide a stable frequency source for the entire low-power Bluetooth transmitter system.

[0118] Compared with the prior art, the fast oscillation device for active crystal oscillator provided in this embodiment determines the overall phase difference between the reference frequency signal and the output frequency signal through the phase difference control circuit, generates an output control word, and the LC-DCO generates an output frequency signal according to the output control word. The energy injection circuit receives the output frequency signal generated by the LC-DCO, and injects energy into the active crystal oscillator according to the output frequency signal, so that the active crystal oscillator quickly outputs a stable reference frequency signal; and, the fractional phase difference PHF between the reference frequency signal and the output frequency signal of the current clock is determined through the embedded TDC circuit, so that when entering the fine adjustment mode, a more accurate overall phase difference is provided, so that the LC-DCO is controlled to obtain an accurate output frequency signal more quickly; at the same time, the mode control module determines whether the mode switching condition is met, and provides more accurate control for the frequency of the LC-DCO. In the coarse adjustment mode, a 1-level dynamic loop bandwidth adjustment operation is added to lock with a larger bandwidth; in the fine adjustment mode, a 2-level dynamic loop bandwidth adjustment operation is added to lock with a lower bandwidth, so that the LC-DCO quickly outputs an accurate output frequency signal, and the full digital phase-locked loop is quickly locked.

[0119] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A fast oscillation starting device for an active crystal oscillator, characterized in that: The fast oscillation device comprises an energy injection circuit, an LC-DCO oscillator based on an inductor-capacitor resonance digital control, and a phase difference control circuit; LC-DCO, used for generating an output frequency signal according to an output control word of a phase difference control circuit; The phase difference control circuit is used to receive the reference frequency signal output by the active crystal oscillator and the output frequency signal of the LC-DCO, calculate the overall phase difference between the two frequency signals, generate an output control word according to the overall phase difference and send it to the LC-DCO; the overall phase difference includes an integer phase difference and a fractional phase difference; The energy injection circuit receives the output frequency signal generated by the LC-DCO and injects energy into the active crystal oscillator according to the output frequency signal, so that the active crystal oscillator can quickly output a stable reference frequency signal.

2. The rapid oscillation device according to claim 1, characterized in that: The phase difference control circuit includes a phase difference acquisition circuit and a digital filter circuit; The phase difference acquisition circuit is used to receive the reference frequency signal output by the active crystal oscillator and the output frequency signal of the LC-DCO, and calculate the overall phase difference; The digital filter circuit is used to determine the control mode of the LC-DCO according to the overall phase difference, and to generate a corresponding output control word according to the control mode to control the LC-DCO.

3. The rapid oscillation device according to claim 2, characterized in that: The phase difference acquisition circuit includes a retiming circuit, an accumulator, a frequency detector, a phase detector, a radio frequency counter and an embedded digital converter TDC circuit; A retiming circuit provides a working clock for an accumulator, a frequency detector, a phase detector, a radio frequency counter and an embedded TDC circuit according to a reference frequency signal; An accumulator accumulates the preset frequency division ratio to obtain the sum PHR of the integer phases of the reference frequency signal before the current clock; The radio frequency counter accumulates and counts the integer phases of the output frequency signal to obtain the sum PHV of the integer phases of the output frequency signal before the current clock; An embedded TDC circuit determines a fractional phase difference PHF between a reference frequency signal and an output frequency signal of a current clock; The phase frequency detector is used to calculate the overall phase difference according to the integer phase sum PHR of the reference frequency signal before the current clock, the integer phase sum PHV of the output frequency signal before the current clock and the fractional phase difference PHF.

4. The rapid oscillation device according to claim 2, characterized in that: The digital filter circuit includes a mode control module, which is used to perform the following steps: Compare the overall phase difference of the current clock with the overall phase difference of the previous clock to determine whether the mode switching condition is met; When the mode switching condition is met, the control mode of the LC-DCO is switched to the fine adjustment mode; otherwise, the control mode of the LC-DCO is the coarse adjustment mode.

5. The rapid oscillation device according to claim 4, characterized in that: The digital filter circuit further includes a frequency control module, which is used to perform the following steps: In the coarse adjustment mode, a 1-level dynamic loop bandwidth adjustment operation is added to lock with a larger bandwidth; In fine tuning mode, a 2-stage dynamic loop bandwidth adjustment operation is added to lock at a lower bandwidth.

6. The rapid oscillation device according to claim 5, characterized in that: The phase difference acquisition circuit also includes a selector, and the selector includes a coarse adjustment path input terminal and a fine adjustment path input terminal; In the coarse tuning mode, the selector directly receives the output frequency signal of the current clock through the coarse tuning path input terminal and transmits it to the RF counter; In the fine tuning mode, the embedded TDC circuit receives the output frequency signal of the current clock, and transmits the output frequency signal of the current clock to the RF counter through the fine tuning path input terminal of the selector.

7. The rapid oscillation device according to claim 6, characterized in that: The embedded TDC circuit includes a ring oscillator RO and N independent D flip-flops, wherein the RO includes N pseudo-differential structures cascaded in sequence; each pseudo-differential structure corresponds to a D flip-flop; The two input ends of the first pseudo differential structure receive the output frequency signal of the current clock through differential, and the two output ends of each pseudo differential structure are respectively connected to the two input ends of the corresponding D flip-flop; The rising edge sampling ports of each D flip-flop are connected to each other and receive the reference frequency signal together; The two output signals of each D flip-flop are transmitted to a TDC encoder, and the TDC encoder encodes the output signals of the N D flip-flops to obtain a fractional phase difference, and sends it to a frequency detector and a phase detector.

8. The rapid oscillation device according to claim 7, characterized in that: The embedded TDC circuit further includes a current-controlled digital-to-analog converter IDAC circuit, which is respectively connected to the power supply voltage port of each pseudo-differential structure; In the fine tuning mode, the IDAC circuit is used to receive the output control word of the digital filter circuit, and the output control word is used to adjust the RO so that its frequency is the same as the frequency of the output frequency signal of the LC-DCO, thereby performing injection locking.

9. The rapid oscillation device according to claim 1, characterized in that: The energy injection circuit includes a programmable frequency divider, a duty cycle modulation circuit and a delay selection circuit; A programmable frequency divider is used to receive an output frequency signal from the LC-DCO and divide the frequency according to a preset frequency division ratio to obtain a reference frequency signal; The duty cycle modulation circuit performs duty cycle modulation on the divided reference frequency signal so that the duty cycle reaches 50% to obtain a modulated signal; The delay selection circuit is used to perform delay control according to the modulated signal and inject energy into the active crystal oscillator.

10. The rapid oscillation device according to claim 7, characterized in that: N＝6。

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