Operational amplification circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of integrated circuits, and discloses an operational amplifier circuit, a chip and electronic equipment. The operational amplification circuit comprises an amplification module, and the amplification module comprises a first amplification unit, a second amplification unit and a modulation unit; wherein the first amplification unit is used for receiving a first differential signal, and the second amplification unit is used for receiving a second differential signal; the first amplification unit outputs a first difference signal between the first differential signal and the second differential signal through a first output node; the second amplification unit outputs a second difference signal between the first difference signal and the second difference signal through a second output node; the output end of the modulation unit is alternately communicated with the first output node and the second output node so as to periodically and alternately output the first difference signal and the second difference signal. On the basis, the difference between the first amplification unit and the second amplification unit can be counteracted, so that the offset voltage generated in the amplification module is reduced, and the precision of the operational amplification circuit is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an operational amplifier circuit, a chip and an electronic device. Background Art

[0002] The operational amplifier circuit includes two positive and negative input terminals for receiving input signals respectively, and includes an amplification module for amplifying the difference between the two input signals. The amplification module usually includes at least one pair of transistors, and the two transistors in the same pair of transistors are respectively used to connect the positive input terminal and the negative input terminal. Various fixed parameters (such as threshold voltage, etc.) of the two transistors must be the same to ensure that during the amplification process, the two input signals are treated equally when flowing through the two transistors, so that the difference between the two input signals can be accurately amplified.

[0003] However, the transistors of the amplification module are usually complementary metal oxide semiconductor field effect transistors (MOSFET or MOS tubes), and the error in the manufacturing process of MOS tubes is large, and there is inevitable non-uniformity, resulting in slight differences between different MOS tubes. Therefore, the two transistors in the same pair of transistors are not exactly the same. When two input signals flow through these two transistors, in addition to the voltage difference generated between the two input signals (that is, the difference that needs to be amplified), the difference between the transistors themselves will also cause a new voltage difference (that is, the offset voltage). In other words, when there is no difference in the input signal, the output voltage of the circuit is not zero, and this non-zero output voltage is the offset voltage.

[0004] Therefore, how to further reduce the offset voltage in the operational amplifier circuit to improve the accuracy of the operational amplifier circuit is a problem that needs to be solved urgently. Summary of the invention

[0005] In order to solve the above technical problems, the embodiments of the present application provide an operational amplifier circuit, a chip and an electronic device.

[0006] In a first aspect, an embodiment of the present application provides an operational amplifier circuit, which includes an amplifier module, and the amplifier module includes a first amplifier unit, a second amplifier unit and a modulation unit; wherein the first amplifier unit is used to receive a first differential signal, and the second amplifier unit is used to receive a second differential signal; the first amplifier unit has a first output node, and the first amplifier unit outputs a first difference signal between the first differential signal and the second differential signal through the first output node; the second amplifier unit has a second output node, and the second amplifier unit outputs a second difference signal between the first differential signal and the second differential signal through the second output node; the modulation unit is connected to the first output node and the second output node respectively, and the output end of the modulation unit is the output end of the amplifier module, and the output end of the modulation unit is alternately connected to the first output node and the second output node to periodically alternately output the first difference signal and the second difference signal.

[0007] Based on the above scheme, since the modulation unit can periodically and alternately output the first difference signal and the second difference signal, when the frequency of the periodically and alternately output signal is high (for example, the frequency is higher than the frequency of the first differential signal and the second differential signal), the output end of the amplification module can output the average value between the first difference signal and the second difference signal, thereby offsetting the difference between the first amplification unit and the second amplification unit, and reducing the offset voltage generated in the amplification module. Therefore, in the voltage change at the output end of the operational amplifier circuit, the offset voltage generated by the difference between the MOS tubes in the amplification module is eliminated, so that the difference between the input signals is amplified more accurately.

[0008] In some possible implementations of the first aspect above, the modulation unit is used to connect the first output node and the output end of the modulation unit when receiving a first control signal, and is used to connect the second output node and the output end of the modulation unit when receiving a second control signal.

[0009] It can be understood that the modulation unit can alternately receive the first control signal and the second control signal, thereby alternately connecting the first output node and the second output node, so as to periodically and alternately output the first difference signal and the second difference signal.

[0010] In some possible implementations of the first aspect above, the modulation unit includes a first modulation transistor, a second modulation transistor, a third modulation transistor and a fourth modulation transistor of the same doping type; the first end of the first modulation transistor and the first end of the third modulation transistor are both connected to the first output node, and the first end of the second modulation transistor and the first end of the fourth modulation transistor are both connected to the second output node; the second end of the first modulation transistor is connected to the second end of the second modulation transistor, and the second end of the third modulation transistor is connected to the second end of the fourth modulation transistor; the gate of the first modulation transistor and the gate of the fourth modulation transistor are both used to receive an inverted clock signal, and the gate of the second modulation transistor and the gate of the third modulation transistor are both used to receive a clock signal.

[0011] In some embodiments, the clock signal is a periodic square wave signal with a duty cycle of 50%, the first control signal includes the clock signal at a first level and the inverted clock signal at a second level; the second control signal includes the clock signal at a second level and the inverted clock signal at a first level; the first level and the second level are different.

[0012] It can be understood that, for example, in the t1 time period, the modulation unit receives the first control signal, the clock signal is at the first level, and the inverted clock signal is at the second level. At this time, the first output node can be connected to the output end of the modulation unit, and the second output node can be connected to the feedback end of the modulation unit. Similarly, in the t2 time period, the modulation unit receives the second control signal. At this time, the second output node can be connected to the output end of the modulation unit, and the first output node can be connected to the feedback end of the modulation unit. Therefore, the output end of the amplification module can alternately output the first difference signal and the second difference signal, thereby offsetting the difference between the first amplification unit and the second amplification unit and reducing the offset voltage generated in the amplification module.

[0013] In some possible implementations of the first aspect above, the doping types of the first modulation transistor, the second modulation transistor, the third modulation transistor and the fourth modulation transistor are all N-type; or, the doping types of the first modulation transistor, the second modulation transistor, the third modulation transistor and the fourth modulation transistor are all P-type.

[0014] In some possible implementations of the first aspect above, the first amplifying unit includes a first amplifying transistor and a second amplifying transistor, the second amplifying unit includes a third amplifying transistor and a fourth amplifying transistor, the first amplifying transistor and the third amplifying transistor have the same doping type, the second amplifying transistor and the fourth amplifying transistor have the same doping type, and the first amplifying transistor and the second amplifying transistor have opposite doping types; wherein the first end of the first amplifying transistor and the first end of the second amplifying transistor are both connected to the first output node, and the first end of the third amplifying transistor and the first end of the fourth amplifying transistor are both connected to the second output node; the gate of the first amplifying transistor and the gate of the third amplifying transistor are both connected to the first bias voltage, and the gate of the second amplifying transistor and the gate of the fourth amplifying transistor are both connected to the second bias voltage.

[0015] It can be understood that in the above-mentioned first amplifying unit and the second amplifying unit, the difference between the first amplifying transistor and the third amplifying transistor, and the difference between the second amplifying transistor and the fourth amplifying transistor will both produce an offset voltage, and the modulation unit is set on the first output node and the second output node to reduce the above-mentioned offset voltage, thereby improving the amplification accuracy of the amplifying module.

[0016] In some possible implementations of the first aspect above, the operational amplifier circuit also includes a current source module and a current drain module; wherein the first end of the current source module is connected to the second end of the first amplifying transistor, and the second end of the current source module is connected to the second end of the third amplifying transistor; the first end of the current drain module is connected to the second end of the second amplifying transistor, and the second end of the current drain module is connected to the second end of the fourth amplifying transistor.

[0017] In some possible implementations of the first aspect above, the current source module includes a first transistor and a second transistor, the current drain module includes a third transistor and a fourth transistor, the first transistor and the second transistor have the same doping type, the third transistor and the fourth transistor have the same doping type, and the first transistor and the third transistor have opposite doping types; wherein the first end of the first transistor and the first end of the second transistor are both connected to a power supply voltage, the gate of the first transistor is connected to the gate of the second transistor, the second end of the first transistor is connected to the second end of the first amplifying transistor, and the second end of the second transistor is connected to the second end of the third amplifying transistor; the first end of the third transistor and the first end of the fourth transistor are both grounded, the gate of the third transistor is connected to the gate of the fourth transistor, the second end of the third transistor is connected to the second end of the second amplifying transistor, and the second end of the fourth transistor is connected to the second end of the fourth amplifying transistor.

[0018] In some possible implementations of the first aspect above, the operational amplifier circuit also includes an input module, and the modulation unit also includes a feedback end; wherein the input module is connected to the second end of the third transistor and the second end of the fourth transistor, and the feedback end is connected to the gate of the third transistor and the gate of the fourth transistor; or, the input module is connected to the second end of the first transistor and the second end of the second transistor, and the feedback end is connected to the gate of the first transistor and the gate of the second transistor.

[0019] In some possible implementations of the first aspect above, the first end of the input module is connected to the first input end of the operational amplifier circuit, and the second end of the input module is connected to the second input end of the operational amplifier circuit; the third end of the input module is connected to the second end of the second amplifying transistor and the second end of the third transistor, and the fourth end of the input module is connected to the second end of the fourth amplifying transistor and the second end of the fourth transistor; the output end of the modulation unit is connected to the second end of the first modulation transistor and the second end of the second modulation transistor, the feedback end of the modulation unit is connected to the second end of the third modulation transistor and the second end of the fourth modulation transistor, the feedback end of the modulation unit is connected to the gate of the third transistor and the gate of the fourth transistor, and the gate of the first transistor and the gate of the second transistor are connected to a third bias voltage.

[0020] It can be understood that the input module is used to transmit the differential input signal of the first input end and the second input end to the amplification module, so that the first amplification unit can receive the first differential signal and the second amplification unit can receive the second differential signal.

[0021] In some possible implementations of the first aspect above, the input module includes a first input transistor, a second input transistor and a third input transistor, and the first input transistor, the second input transistor, the third input transistor, the first transistor and the second transistor have the same doping type; wherein the gate of the first input transistor is connected to a fourth bias voltage, the first end is connected to a power supply voltage, and the second end is connected to a first end of the second input transistor and a first end of the third input transistor; the gate of the second input transistor serves as the first end of the input module, and the second end is connected to the second end of the second amplifying transistor and the second end of the third transistor; the gate of the third input transistor serves as the second end of the input module, and the second end is connected to the second end of the fourth amplifying transistor and the second end of the fourth transistor.

[0022] In some possible implementations of the first aspect above, the first end of the input module is connected to the first input end of the operational amplifier circuit, and the second end of the input module is connected to the second input end of the operational amplifier circuit; the third end of the input module is connected to the second end of the first amplifying transistor and the second end of the first transistor, and the fourth end of the input module is connected to the second end of the third amplifying transistor and the second end of the second transistor; the output end of the modulation unit is connected to the second end of the third modulation transistor and the second end of the fourth modulation transistor, the feedback end of the modulation unit is connected to the second end of the first modulation transistor and the second end of the second modulation transistor, the feedback end of the modulation unit is connected to the gate of the first transistor and the gate of the second transistor, and the gate of the third transistor and the gate of the fourth transistor are connected to a third bias voltage.

[0023] In some possible implementations of the first aspect above, the input module includes a first input transistor, a second input transistor and a third input transistor, and the first input transistor, the second input transistor, the third input transistor, the third transistor and the fourth transistor have the same doping type; wherein the gate of the first input transistor is connected to a fourth bias voltage, the first end is grounded, and the second end is connected to the first end of the second input transistor and the first end of the third input transistor; the gate of the second input transistor serves as the first end of the input module, and the second end is connected to the second end of the first amplifying transistor and the second end of the first transistor; the gate of the third input transistor serves as the second end of the input module, and the second end is connected to the second end of the third amplifying transistor and the second end of the second transistor.

[0024] In some possible implementations of the first aspect above, the operational amplifier circuit also includes a first chopping module, and the first chopping module includes a first chopping transistor, a second chopping transistor, a third chopping transistor and a fourth chopping transistor of the same doping type; wherein the gate of the first chopping transistor and the gate of the fourth chopping transistor are both used to receive an inverted clock signal, the gate of the second chopping transistor and the gate of the third chopping transistor are both used to receive a clock signal, the first end of the first chopping transistor and the first end of the third chopping transistor are both connected to the first input end of the operational amplifier circuit, the first end of the second chopping transistor and the first end of the fourth chopping transistor are both connected to the second input end of the operational amplifier circuit, the second end of the first chopping transistor and the second end of the second chopping transistor are both connected to the first end of the input module, and the second end of the third chopping transistor and the second end of the fourth chopping transistor are both connected to the second end of the input module.

[0025] It can be understood that when the first chopping module is set, one of the first input terminal and the second input terminal can be alternately connected to one of the first terminal and the second terminal of the input module, thereby eliminating the interference difference between the two input terminals of the input module.

[0026] In some possible implementations of the first aspect above, the operational amplifier circuit also includes a second chopping module, and the second chopping module includes a fifth chopping transistor, a sixth chopping transistor, a seventh chopping transistor and an eighth chopping transistor of the same doping type; wherein the gate of the fifth chopping transistor and the gate of the eighth chopping transistor are both used to receive an inverted clock signal, the gate of the sixth chopping transistor and the gate of the seventh chopping transistor are both used to receive a clock signal, the first end of the fifth chopping transistor and the first end of the seventh chopping transistor are both connected to the second end of the first transistor, the first end of the sixth chopping transistor and the first end of the eighth chopping transistor are both connected to the second end of the second transistor, the second end of the fifth chopping transistor and the second end of the sixth chopping transistor are both connected to the second end of the first amplifying transistor, and the second end of the seventh chopping transistor and the second end of the eighth chopping transistor are both connected to the second end of the third amplifying transistor.

[0027] It can be understood that, in the case of providing the second chopping module, one of the first transistor and the second transistor can be alternately connected to one of the first amplifying unit and the second amplifying unit, respectively, so as to eliminate the interference difference generated in the current source module.

[0028] In some possible implementations of the first aspect above, the operational amplifier circuit also includes a third chopping module, and the third chopping module includes a ninth chopping transistor, a tenth chopping transistor, an eleventh chopping transistor and a twelfth chopping transistor of the same doping type; wherein the gate of the ninth chopping transistor and the gate of the twelfth chopping transistor are both used to receive an inverted clock signal, the gate of the tenth chopping transistor and the gate of the eleventh chopping transistor are both used to receive a clock signal, the first end of the ninth chopping transistor and the first end of the eleventh chopping transistor are both connected to the second end of the second amplifying transistor, the first end of the tenth chopping transistor and the first end of the twelfth chopping transistor are both connected to the second end of the fourth amplifying transistor, the second end of the ninth chopping transistor and the second end of the tenth chopping transistor are both connected to the second end of the third transistor, and the second end of the eleventh chopping transistor and the second end of the twelfth chopping transistor are both connected to the second end of the fourth transistor.

[0029] It can be understood that, in the case of providing the second chopping module, one of the first transistor and the second transistor can be alternately connected to one of the first amplifying unit and the second amplifying unit, respectively, so as to eliminate the interference difference generated in the current source module.

[0030] In some possible implementations of the first aspect above, the operational amplifier circuit also includes a filtering module, the filtering module includes a first capacitor and a first resistor, one end of the first resistor is connected to the output end of the amplifier module, the other end is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; or, the filtering module includes a first capacitor, one end of the first capacitor is connected to the output end of the amplifier module, and the other end is grounded.

[0031] In a second aspect, an embodiment of the present application further provides a chip, comprising the operational amplifier circuit of the first aspect mentioned above.

[0032] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the operational amplifier circuit of the first aspect described above.

[0033] The technical effects of the second and third aspects mentioned above can refer to the relevant description of the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 According to some embodiments of the present application, a structural schematic diagram of a first operational amplifier circuit is shown;

[0035] Figure 2A According to some embodiments of the present application, a structural schematic diagram of a second operational amplifier circuit is shown;

[0036] Figure 2B According to some embodiments of the present application, it is shown Figure 2A Specific structural diagram of the operational amplifier circuit;

[0037] Figure 2C According to some embodiments of the present application, a waveform diagram of a clock signal and an inverted clock signal is shown;

[0038] Figure 3A According to some embodiments of the present application, a schematic diagram of the structure of a third operational amplifier circuit is shown;

[0039] Figure 3B According to some embodiments of the present application, it is shown Figure 3A Specific structural diagram of the operational amplifier circuit;

[0040] Figure 4A According to some embodiments of the present application, a structural schematic diagram of a fourth operational amplifier circuit is shown;

[0041] Figure 4B According to some embodiments of the present application, it is shown Figure 4A Specific structural diagram of the operational amplifier circuit;

[0042] Figure 5A According to some embodiments of the present application, a structural schematic diagram of a fifth operational amplifier circuit is shown;

[0043] Figure 5B According to some embodiments of the present application, it is shown Figure 5A Schematic diagram of the specific structure of the operational amplifier circuit. DETAILED DESCRIPTION

[0044] Illustrative embodiments of the present application include, but are not limited to, operational amplifier circuits, chips, and electronic devices.

[0045] The operational amplifier circuit provided in the embodiment of the present application can be applied to any electronic device, including but not limited to a mobile station (MS), a mobile terminal (MT), etc. For example, the electronic device can be a mobile phone, a smart TV, a wearable device, a tablet computer (Pad), a desktop computer, a laptop computer, a virtual reality (VR) device, an augmented reality (AR) device, a terminal in industrial control, a terminal in autonomous driving, a terminal in remote medical surgery, a terminal in a smart grid, a terminal in transportation safety, a terminal in a smart city, a terminal in a smart home, etc. The embodiment of the present application does not limit the specific form of the electronic device.

[0046] It should be noted that the structure and working principle of the operational amplifier circuit are introduced below by taking the operational amplifier circuit as a folded common-source common-gate operational amplifier circuit as an example.

[0047] refer to Figure 1 , Figure 1 The present invention is a schematic diagram of the structure of an operational amplifier circuit 100a, which can be specifically a schematic diagram of the structure of a folded common source and common gate operational amplifier circuit. The operational amplifier circuit 100a includes an input module 110, a current source module 120, an amplifier module 130 and a current drain module 140, and the amplifier module 130 includes a first amplifier unit 131 and a second amplifier unit 132. The first end of the input module 110 is connected to the positive input terminal INP, the second end is connected to the negative input terminal INN, the third end is connected to the first end of the second amplifier unit 132 and the first end of the current drain module 140, and the fourth end is connected to the first end of the first amplifier unit 131 and the second end of the current drain module 140; the first end and the second end of the current source module 120 are respectively connected to the second end of the first amplifier unit 131 and the second end of the second amplifier unit 132; the third end of the second amplifier unit 132 is connected to the output terminal OUT, and the third end of the first amplifier unit 131 is connected to the third end of the current drain module 140 as the feedback end of the amplifier module 130. It can be seen that the operational amplifier circuit 100a is a circuit with dual-ended (ie, differential) input and single-ended output.

[0048] In the above operational amplifier circuit 100a, the amplification module 130 is used to amplify the difference between the input signal received by the positive input terminal INP and the input signal received by the negative input terminal INN. Specifically, the difference between the two input signals is expressed as a voltage difference at the positive input terminal INP and the negative input terminal INN. When the voltage of the positive input terminal INP is higher than the voltage of the negative input terminal INN, more current will flow through the second amplification unit 132 connected to the positive input terminal INP, and the current of the first amplification unit 131 connected to the negative input terminal INN will decrease. Since the first amplification unit 131 and the second amplification unit 132 are identical transistors in an ideal case, the current change of the first amplification unit 131 and the current change of the second amplification unit 132 will occur in a symmetrical manner, that is, the current of the first amplification unit 131 will decrease as much as the current of the second amplification unit 132 increases, and vice versa. The current change of the first amplification unit 131 or the current change of the second amplification unit 132 in the amplification module 130 will cause a change in the output voltage of the output terminal OUT, and the change in the output voltage corresponds to the amplified difference signal.

[0049] However, as mentioned above, due to process deviation, there are slight differences between the MOS tubes in the first amplifying unit 131 and the second amplifying unit 132, which makes the current change of the first amplifying unit 131 and the current change of the second amplifying unit 132 in the amplifying module 130 no longer occur in a symmetrical manner, that is, when there is no difference in the input signal, the output voltage of the circuit is not zero, and this non-zero output voltage is the offset voltage. Therefore, the voltage change at the output end is mixed with the offset voltage generated by the difference between the MOS tubes, so that the difference between the input signals is not accurate after amplification.

[0050] In order to solve the above problems, an embodiment of the present application provides an operational amplifier circuit, which includes an amplifier module, and the amplifier module includes a first amplifier unit, a second amplifier unit and a modulation unit; wherein the first amplifier unit is used to receive a first differential signal, and the second amplifier unit is used to receive a second differential signal; the first amplifier unit has a first output node, and the first amplifier unit outputs a first difference signal between the first differential signal and the second differential signal through the first output node; the second amplifier unit has a second output node, and the second amplifier unit outputs a second difference signal between the first differential signal and the second differential signal through the second output node; the modulation unit is connected to the first output node and the second output node respectively, and the output end of the modulation unit is the output end of the amplifier module, and the output end of the modulation unit is alternately connected to the first output node and the second output node to periodically alternately output the first difference signal and the second difference signal. Therefore, the modulation unit can offset the difference between the first amplifier unit and the second amplifier unit, thereby reducing the offset voltage generated in the amplifier module.

[0051] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0052] In this document, the reference numeral "100" followed by a letter is used to indicate different examples of operational amplifier circuits provided in the embodiments of the present application, for example, operational amplifier circuit 100b and operational amplifier circuit 100c are different examples of two operational amplifier circuits. In addition, it should be noted that the first end of any transistor (such as a MOS tube) mentioned in the present application refers to one of the source and the drain, and the second end refers to the other of the source and the drain. For example, the first end of the transistor (such as a MOS tube) can be a source, and the second end can be a drain, or the first end can be a drain, and the second end can be a source.

[0053] The following combination Figure 2A and Figure 2B The first embodiment of the operational amplifier circuit provided by the present application is described in detail.

[0054] Figure 2A According to some embodiments of the present application, a schematic diagram of the structure of an operational amplifier circuit 100b is shown. In the operational amplifier circuit 100b, by connecting the modulation unit 153 to the first output node N1 of the first amplifier unit 151 and the second output node N2 of the second amplifier unit 152, and making the output end of the modulation unit 153 alternately connected to the first output node N1 and the second output node N2, the difference between the first amplifier unit 151 and the second amplifier unit 152 is offset, so as to eliminate the offset voltage generated in the amplifier module 150.

[0055] refer to Figure 2A In some embodiments, the operational amplifier circuit 100b includes an input module 110, a current source module 120, a current drain module 140 and an amplifier module 150, and the amplifier module 150 includes a first amplifier unit 151, a second amplifier unit 152 and a modulation unit 153. The current source module 120 is connected to the first amplifier unit 151 and the second amplifier unit 152 respectively, the first end of the input module 110 is connected to the first input end INP of the operational amplifier circuit 100b, the second end of the input module 110 is connected to the second input end INN of the operational amplifier circuit 100b, the first end of the first amplifier unit 151 is connected to the third end of the input module 110 and the current drain module 140, so as to receive the first differential signal sent by the input module 110, and the first end of the second amplifier unit 152 is connected to the fourth end of the input module 110 and the current drain module 140, so as to receive the second differential signal sent by the input module 110.

[0056] In addition, in some embodiments, the first amplifier unit 151 has a first output node N1, and the first amplifier unit 151 outputs a first difference signal between the first differential signal and the second differential signal through the first output node N1, wherein the first difference signal includes both the voltage difference between the first differential signal and the second differential signal and the offset voltage generated in the first amplifier unit 151. The second amplifier unit 152 has a second output node N2, and the second amplifier unit 152 outputs a second difference signal between the first differential signal and the second differential signal through the second output node N2, wherein the second difference signal includes both the voltage difference between the first differential signal and the second differential signal and the offset voltage generated in the second amplifier unit 152. The two input terminals of the modulation unit 153 are respectively connected to the first output node N1 and the second output node N2, and the output terminal of the modulation unit 153 is the output terminal of the amplification module 150, and the output terminal of the modulation unit 153 is alternately connected to the first output node N1 and the second output node N2, so as to periodically and alternately output the first difference signal and the second difference signal. Therefore, when the frequency of the periodically alternating output signal is high (for example, the frequency is higher than the frequencies of the first differential signal and the second differential signal), the output end of the amplification module 150 can output the average value between the first difference signal and the second difference signal, thereby offsetting the difference between the first amplification unit 151 and the second amplification unit 152 and reducing the offset voltage generated in the amplification module 150.

[0057] In some embodiments, the modulation unit 153 also includes a feedback terminal. The feedback terminal of the modulation unit 153 is connected to the current drain module 140, and the feedback terminal of the modulation unit 153 is alternately connected to the first output node N1 and the second output node N2, so as to periodically and alternately connect the first difference signal and the second difference signal to the feedback terminal, so as to realize the function of converting the differential input to the single-ended output in the amplification module 150. Specifically, when receiving the first control signal, the modulation unit 153 connects the first output node N1 and the output terminal of the modulation unit 153, and connects the second output node N2 and the feedback terminal of the modulation unit 153; when receiving the second control signal, the modulation unit 153 connects the second output node N2 and the output terminal of the modulation unit, and connects the first output node N1 and the feedback terminal of the modulation unit 153.

[0058] Figure 2B According to some embodiments of the present application, it is shown Figure 2A Detailed structural diagram of the operational amplifier circuit 100b.

[0059] In some embodiments, reference Figure 2BThe modulation unit 153 includes a first modulation transistor M23, a second modulation transistor M24, a third modulation transistor M25, and a fourth modulation transistor M26, all of which are doped into N-type (NMOS tube). The first end of the first modulation transistor M23 and the first end of the third modulation transistor M25 are connected to the first output node N1, and the first end of the second modulation transistor M24 and the first end of the fourth modulation transistor M26 are connected to the second output node N2; the second end of the first modulation transistor M23 and the second end of the second modulation transistor M24 are connected to the output end of the modulation unit 153, and the second end of the third modulation transistor M25 and the second end of the fourth modulation transistor M26 are connected to the feedback end of the modulation unit 153; the gate of the first modulation transistor M23 and the gate of the fourth modulation transistor M26 are used to receive the inverted clock signal CLKN, and the gate of the second modulation transistor M24 and the gate of the third modulation transistor M25 are used to receive the clock signal CLK.

[0060] In some embodiments, the first end of the first modulation transistor M23, the first end of the second modulation transistor M24, the first end of the third modulation transistor M25, and the first end of the fourth modulation transistor M26 can all be drains, and the second end of the first modulation transistor M23, the second end of the second modulation transistor M24, the second end of the third modulation transistor M25, and the second end of the fourth modulation transistor M26 can all be sources.

[0061] refer to Figure 2C , Figure 2C The waveform diagram of a clock signal CLK and an inverted clock signal CLKN is shown. The clock signal CLK and the inverted clock signal CLKN are both periodic square wave signals with a duty cycle of 50%, that is, t1=t2. The first control signal includes the clock signal CLK at a first level and the inverted clock signal CLKN at a second level. The second control signal includes the clock signal CLK at a second level and the inverted clock signal CLKN at a first level. Of the first level and the second level, one is a high level and the other is a low level.

[0062] In some embodiments, continue to refer to Figure 2B and Figure 2C, the first modulation transistor M23, the second modulation transistor M24, the third modulation transistor M25 and the fourth modulation transistor M26 are all NMOS tubes. At this time, the first level is less than the second level, that is, the first level is a low level and the second level is a high level. For example, in the time period t1, the modulation unit 153 receives the first control signal, the clock signal CLK is the first level, that is, the low level, and the inverted clock signal CLKN is the second level, that is, the high level. Therefore, the first modulation transistor M23 and the fourth modulation transistor M26 are turned on, and the second modulation transistor M24 and the third modulation transistor M25 are turned off. At this time, the first output node N1 is connected to the output end of the modulation unit 153, and the second output node N2 is connected to the feedback end of the modulation unit 153. Similarly, in the time period t2, the modulation unit 153 receives the second control signal, the first modulation transistor M23 and the fourth modulation transistor M26 are turned off, the second modulation transistor M24 and the third modulation transistor M25 are turned on, at this time, the second output node N2 is connected to the output end of the modulation unit 153, and the first output node N1 is connected to the feedback end of the modulation unit 153. Therefore, the output end of the amplification module 150 can alternately output the first difference signal and the second difference signal, so as to offset the difference between the first amplification unit 151 and the second amplification unit 152, and reduce the offset voltage generated in the amplification module 150.

[0063] It can be understood that in some other embodiments (not shown), the first modulation transistor M23, the second modulation transistor M24, the third modulation transistor M25 and the fourth modulation transistor M26 are all PMOS transistors. At this time, the positions of the clock signal CLK and the inverted clock signal CLKN are swapped. At this time, the principle of the modulation unit 153 is similar to the above process and will not be repeated here.

[0064] In some embodiments, continue to refer to Figure 2B The output end of the amplifying module 150 can be directly connected to the output end OUT of the operational amplifier circuit 100b.

[0065] In some embodiments, continue to refer to Figure 2B, the first amplifying unit 151 includes a first amplifying transistor M5 and a second amplifying transistor M7, the second amplifying unit 152 includes a third amplifying transistor M6 and a fourth amplifying transistor M8, the first amplifying transistor M5 and the third amplifying transistor M6 have the same doping type (for example, both are PMOS transistors), the second amplifying transistor M7 and the fourth amplifying transistor M8 have the same doping type (for example, both are NMOS transistors), and the first amplifying transistor and the second amplifying transistor have opposite doping types. Among them, the first end of the first amplifying transistor M5 and the first end of the second amplifying transistor M7 are both connected to the first output node N1, the first end of the third amplifying transistor M6 and the first end of the fourth amplifying transistor M8 are both connected to the second output node N2; the gate of the first amplifying transistor M5 and the gate of the third amplifying transistor M6 are both connected to the first bias voltage VB1, and the gate of the second amplifying transistor M7 and the gate of the fourth amplifying transistor M8 are both connected to the second bias voltage VB2. Therefore, in the above-mentioned first amplifying unit 151 and the second amplifying unit 152, the difference between the first amplifying transistor M5 and the third amplifying transistor M6, and the difference between the second amplifying transistor M7 and the fourth amplifying transistor M8 will both generate an offset voltage. The modulation unit 153 is set on the first output node N1 and the second output node N2 to reduce the above-mentioned offset voltage, thereby improving the amplification accuracy of the amplifying module 150.

[0066] It should be noted that, in some other embodiments, the first amplifying transistor M5, the second amplifying transistor M7, the third amplifying transistor M6 and the fourth amplifying transistor M8 may all be bipolar junction transistors (BJT), which may also be called triodes. Compared with MOS transistors, triodes are more stable in terms of process deviation, especially the base-emitter voltage (VBE) of the triode has a smaller deviation relative to the threshold voltage (Vth) of the MOS transistor, so that the first amplifying transistor M5, the second amplifying transistor M7, the third amplifying transistor M6 and the fourth amplifying transistor M8 can be set as triodes, which can further reduce the offset voltage generated by the amplifying module, so that the offset voltage reaches the μV level.

[0067] In some embodiments, continue to refer to Figure 2B, the current source module 120 includes a first transistor M3 and a second transistor M4, the current drain module 140 includes a third transistor M9 and a fourth transistor M10, the first transistor M3 and the second transistor M4 have the same doping type (for example, both are PMOS tubes), the third transistor and the fourth transistor have the same doping type (for example, both are NMOS tubes), and the first transistor and the third transistor have opposite doping types. Among them, the first end of the first transistor M3 and the first end of the second transistor M4 are both connected to the power supply voltage VDD, the gate of the first transistor M3 and the gate of the second transistor M4 are both connected to the third bias voltage VB3, the second end of the first transistor M3 is connected to the second end of the first amplifying transistor M5, and the second end of the second transistor M4 is connected to the second end of the third amplifying transistor M6. The first end of the third transistor M9 and the first end of the fourth transistor M10 are both grounded, the gate of the third transistor M9 and the gate of the fourth transistor M10 are both connected to the feedback end of the modulation unit 153, the second end of the third transistor M9 is connected to the second end of the second amplifying transistor M7, and the second end of the fourth transistor M10 is connected to the second end of the fourth amplifying transistor M8.

[0068] In some embodiments, continue to refer to Figure 2B , the input module 110 includes a first input transistor M0, a second input transistor M1 and a third input transistor M2, and the first input transistor M0, the second input transistor M1, the third input transistor M2, the first transistor M3 and the second transistor M4 have the same doping type (for example, all are PMOS tubes). Among them, the gate of the first input transistor M0 is connected to the fourth bias voltage VB4, the first end is connected to the power supply voltage VDD, and the second end is connected to the first end of the second input transistor M1 and the first end of the third input transistor M2; the gate of the second input transistor M2 serves as the first end of the input module 110, and the second end is connected to the second end of the second amplifying transistor M7 and the second end of the third transistor M9; the gate of the third input transistor M2 serves as the second end of the input module 110, and the second end is connected to the second end of the fourth amplifying transistor M8 and the second end of the fourth transistor M10. In addition, the feedback end of the modulation unit is connected to the gate of the third transistor M9 and the gate of the fourth transistor M10 to realize the dual-end (differential) input and single-end output functions of the operational amplifier circuit 100b.

[0069] The following combination Figure 3A and Figure 3B The second embodiment of the operational amplifier circuit provided by the present application is described in detail.

[0070] Figure 3AAccording to some embodiments of the present application, a schematic diagram of the structure of an operational amplifier circuit 100c is shown, wherein the operational amplifier circuit 100c differs from the operational amplifier circuit 100b only in that the feedback end of the input module 110 and the modulation unit 153 is connected to the current source module 120 but not to the current drain module 140.

[0071] In some embodiments, reference Figure 3A The third end of the input module 110 is connected to the first amplifying unit 151 and the current source module 120 respectively, and the first amplifying unit 151 is used to receive the first differential signal sent by the input module 110; the fourth end of the input module 110 is connected to the second amplifying unit 152 and the current source module 120 respectively, and the second amplifying unit 152 is used to receive the second differential signal sent by the input module 110.

[0072] Understandably, Figure 3A Other structures and Figure 2A The operational amplifier circuit 100b is similar to the operational amplifier circuit 100b, and the description in the above-mentioned related embodiments can be referred to, which will not be repeated here.

[0073] Figure 3B According to some embodiments of the present application, it is shown Figure 3A Detailed structural diagram of the operational amplifier circuit 100c.

[0074] In some embodiments, reference Figure 3B Specifically, the difference between the operational amplifier circuit 100c and the operational amplifier circuit 100b is that the doping type of the first input transistor M0, the second input transistor M2, the third input transistor M3, the third transistor M9 and the fourth transistor M10 is the same (for example, all are NMOS tubes). Among them, the first end of the first input transistor M0 is grounded, the second end of the second input transistor M1 is connected to the second end of the first amplifying transistor M5 and the second end of the first transistor M3; the second end of the third input transistor M2 is connected to the second end of the third amplifying transistor M6 and the second end of the second transistor M4. In addition, the output end of the modulation unit 153 is connected to the second end of the third modulation transistor M25 and the second end of the fourth modulation transistor M26, and the feedback end of the modulation unit 153 is connected to the second end of the first modulation transistor M23, the second end of the second modulation transistor M24, the gate of the first transistor M3, and the gate of the second transistor M4; the gate of the third transistor M9 and the gate of the fourth transistor M10 are connected to the third bias voltage VB3.

[0075] In some embodiments, continue to refer to Figure 3B and Figure 2C, the first modulation transistor M23, the second modulation transistor M24, the third modulation transistor M25 and the fourth modulation transistor M26 are all NMOS transistors. At this time, the first level is greater than the second level, that is, the first level is a high level and the second level is a low level. For example, in the time period t1, the modulation unit 153 receives the first control signal, the clock signal CLK is the first level, that is, a high level, and the inverted clock signal CLKN is the second level, that is, a low level. Therefore, the first modulation transistor M23 and the fourth modulation transistor M26 are turned off, and the second modulation transistor M24 and the third modulation transistor M25 are turned on. At this time, the first output node N1 is connected to the output end of the modulation unit 153, and the second output node N2 is connected to the feedback end of the modulation unit 153. Similarly, in the time period t2, the modulation unit 153 receives the second control signal, the first modulation transistor M23 and the fourth modulation transistor M26 are turned on, the second modulation transistor M24 and the third modulation transistor M25 are turned off, at this time, the second output node N2 is connected to the output end of the modulation unit 153, and the first output node N1 is connected to the feedback end of the modulation unit 153. Therefore, the output end of the amplification module 150 can alternately output the first difference signal and the second difference signal, so as to offset the difference between the first amplification unit 151 and the second amplification unit 152, and reduce the offset voltage generated in the amplification module 150.

[0076] It can be understood that in some other embodiments (not shown), the first modulation transistor M23, the second modulation transistor M24, the third modulation transistor M25 and the fourth modulation transistor M26 are all PMOS transistors. At this time, the positions of the clock signal CLK and the inverted clock signal CLKN are swapped. At this time, the principle of the modulation unit 153 is similar to the above process and will not be repeated here.

[0077] Understandably, Figure 3B Other structures and Figure 2B The operational amplifier circuit 100b is similar to the operational amplifier circuit 100b, and the description in the above-mentioned related embodiments can be referred to, which will not be repeated here.

[0078] The following combination Figure 4A and Figure 4B The third embodiment of the operational amplifier circuit provided in the present application is described in detail.

[0079] Figure 4A According to some embodiments of the present application, a schematic diagram of the structure of an operational amplifier circuit 100d is shown. The difference between the operational amplifier circuit 100d and the operational amplifier circuit 100b is that a first chopping module 160a, a second chopping module 160b and a third chopping module 160c are added to reduce the offset voltage generated by the input module 110, the current source module 120 and the current drain module 140.

[0080] In some embodiments, reference Figure 4A Specifically, the first chopping module 160a is located between the first input terminal INP and the input module 110, and between the second input terminal INN and the input module 110, the second chopping module 160b is located between the current source module 120 and the amplification module 150, and the third chopping module 160c is located between the current drain module 140 and the amplification module 150.

[0081] Therefore, further, the first chopping module 160a is used to eliminate the interference difference between the input signal of the first input terminal INP and the input signal of the second input terminal INN (that is, between the two input terminals of the input module 110), the second chopping module 160b is used to eliminate the offset voltage generated by the current source module 120, and the second chopping module 160c is used to eliminate the offset voltage generated by the current leakage module 140, thereby further improving the accuracy of the operational amplifier circuit.

[0082] In some embodiments, continue to refer to Figure 4A The operational amplifier circuit may further include a filter module 170, one end of which is connected to the output end of the amplifier module 150, and the other end of which is connected to the output end OUT of the operational amplifier circuit 100d. The filter module 170 can further filter the interference noise in the output signal to stably output a smoother output signal.

[0083] Understandably, Figure 4A Other structures and Figure 2A The operational amplifier circuit 100b is similar to the operational amplifier circuit 100b, and the description in the above-mentioned related embodiments can be referred to, which will not be repeated here.

[0084] Figure 4B According to some embodiments of the present application, it is shown Figure 4A Specific structural diagram of the operational amplifier circuit 100d.

[0085] In some embodiments, reference Figure 4BThe first chopping module 160a includes a first chopping transistor M11, a second chopping transistor M12, a third chopping transistor M13 and a fourth chopping transistor M14, all of which are doped into N-type (NMOS transistor). Among them, the gate of the first chopping transistor M11 and the gate of the fourth chopping transistor M14 are both used to receive the inverted clock signal CLKN, the gate of the second chopping transistor M12 and the gate of the third chopping transistor M13 are both used to receive the clock signal CLK, the first end of the first chopping transistor M11 and the first end of the third chopping transistor M13 are both connected to the first input terminal INP of the operational amplifier circuit, the first end of the second chopping transistor M12 and the first end of the fourth chopping transistor M14 are both connected to the second input terminal INN of the operational amplifier circuit, the second end of the first chopping transistor M11 and the second end of the second chopping transistor M12 are both connected to the first end of the input module 110 (the gate of the second input transistor M1), and the second end of the third chopping transistor M13 and the second end of the fourth chopping transistor M14 are both connected to the second end of the input module 110 (the gate of the third input transistor M2).

[0086] In some embodiments, the clock signal CLK and the inverted clock signal CLKN may refer to Figure 2C Therefore, it can be understood that, when the first chopping module 160a is provided, one of the first input terminal INP and the second input terminal INN can be alternately connected to one of the first terminal and the second terminal of the input module 110, respectively, so as to eliminate the interference difference between the two input terminals of the input module 110.

[0087] In some embodiments, continue to refer to Figure 4B The second chopping module 160b includes a fifth chopping transistor M15, a sixth chopping transistor M16, a seventh chopping transistor M17, and an eighth chopping transistor M18, all of which are doped with P-type (PMOS tube). The gate of the fifth chopping transistor M15 and the gate of the eighth chopping transistor M18 are both used to receive the inverted clock signal CLKN, the gate of the sixth chopping transistor M16 and the gate of the seventh chopping transistor M17 are both used to receive the clock signal CLK, the first end of the fifth chopping transistor M15 and the first end of the seventh chopping transistor M17 are both connected to the second end of the first transistor M3, the first end of the sixth chopping transistor M16 and the first end of the eighth chopping transistor M18 are both connected to the second end of the second transistor M4, the second end of the fifth chopping transistor M15 and the second end of the sixth chopping transistor M16 are both connected to the second end of the first amplifying transistor M5, and the second end of the seventh chopping transistor M17 and the second end of the eighth chopping transistor M18 are both connected to the second end of the third amplifying transistor M6.

[0088] In some embodiments, the clock signal CLK and the inverted clock signal CLKN may refer to Figure 2C Therefore, it can be understood that, when the second chopping module 160b is provided, one of the first transistor M3 and the second transistor M4 can be alternately connected to one of the first amplifying unit 151 and the second amplifying unit 152, respectively, so as to eliminate the interference difference generated in the current source module 120.

[0089] In some embodiments, continue to refer to Figure 4B The third chopping module includes a ninth chopping transistor M19, a tenth chopping transistor M20, an eleventh chopping transistor M21, and a twelfth chopping transistor M22, all of which are doped with N-type (NMOS tube). Among them, the gate of the ninth chopping transistor M19 and the gate of the twelfth chopping transistor M22 are both used to receive the inverted clock signal CLKN, the gate of the tenth chopping transistor M20 and the gate of the eleventh chopping transistor M21 are both used to receive the clock signal CLK, the first end of the ninth chopping transistor M19 and the first end of the eleventh chopping transistor M21 are both connected to the second end of the second amplifying transistor M7, the first end of the tenth chopping transistor M20 and the first end of the twelfth chopping transistor M22 are both connected to the second end of the fourth amplifying transistor M8, the second end of the ninth chopping transistor M19 and the second end of the tenth chopping transistor M20 are both connected to the second end of the third transistor M9, and the second end of the eleventh chopping transistor M21 and the second end of the twelfth chopping transistor M22 are both connected to the second end of the fourth transistor M10.

[0090] In some embodiments, the clock signal CLK and the inverted clock signal CLKN may refer to Figure 2C Therefore, it can be understood that, when the second chopping module 160b is provided, one of the first transistor M3 and the second transistor M4 can be alternately connected to one of the first amplifying unit 151 and the second amplifying unit 152, respectively, so as to eliminate the interference difference generated in the current source module 120.

[0091] In some embodiments, continue to refer to Figure 4B , the filtering module 170 includes a first capacitor C1 and a first resistor R1, one end of the first resistor R1 is connected to the output end of the amplifying module 150 and the output end OUT of the operational amplifier circuit 100d, and the other end is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded. In some other embodiments (not shown), the filtering module includes a first capacitor C1, one end of the first capacitor C1 is connected to the output end of the amplifying module 150 and the output end OUT of the operational amplifier circuit 100d, and the other end is grounded.

[0092] Understandably, Figure 4B Other structures and Figure 2B The operational amplifier circuit 100b is similar to the operational amplifier circuit 100b, and the description in the above-mentioned related embodiments can be referred to, which will not be repeated here.

[0093] In the above operational amplifier circuit 100d, when the modulation unit 153 is not provided, the value of the offset voltage in the signal outputted from the output terminal OUT is about tens to hundreds of microvolts (μV). In contrast, when the modulation unit 153 is provided, that is, Figure 4B In the circuit shown, the value of the offset voltage in the signal output from the output terminal OUT is on the order of several to dozens of microvolts (μV), thereby further reducing the offset voltage, and the modulation unit 153 occupies a smaller area in the operational amplifier circuit 100d, so that the circuit has a higher degree of integration.

[0094] The following combination Figure 5A and Figure 5B A fourth embodiment of the operational amplifier circuit provided in the present application is described in detail.

[0095] Figure 5A According to some embodiments of the present application, a schematic diagram of the structure of an operational amplifier circuit 100e is shown. The difference between the operational amplifier circuit 100e and the operational amplifier circuit 100c is that a first chopping module 160a, a second chopping module 160b and a third chopping module 160c are added to reduce the offset voltage generated by the input module 110, the current source module 120 and the current drain module 140.

[0096] refer to Figure 5A It can be understood that the relevant contents of the first chopping module 160a, the second chopping module 160b and the third chopping module 160c can refer to the above Figure 4A The related embodiments of the operational amplifier circuit 100d are not described in detail here.

[0097] Figure 5B According to some embodiments of the present application, it is shown Figure 5A Detailed structural diagram of the operational amplifier circuit 100e.

[0098] refer to Figure 5B In some embodiments, the difference between the first chopping module 160a in the operational amplifier circuit 100e and the operational amplifier circuit 100d is that the first chopping module 160a in the operational amplifier circuit 100e includes a first chopping transistor M11, a second chopping transistor M12, a third chopping transistor M13 and a fourth chopping transistor M14, all of which are doping types of P type (PMOS tube).

[0099] It is understandable that the specific structures and principles of the first chopping module 160a, the second chopping module 160b and the third chopping module 160c in the operational amplifier circuit 100e can refer to the above Figure 4B In addition, other structures and principles of the operational amplifier circuit 100e can refer to the above Figure 3B The related embodiments will not be described in detail here.

[0100] In some embodiments, the present application also provides a chip, which includes the operational amplifier circuit described in the embodiments of the present application.

[0101] In some embodiments, the present application also provides an electronic device, which includes the operational amplifier circuit described in the embodiments of the present application.

[0102] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0103] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0104] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0105] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0106] The above is an explanation of the implementation mode of the present application by specific specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Although the description of the present application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to the implementation mode. On the contrary, the purpose of introducing the application in conjunction with the implementation mode is to cover other options or modifications that may be extended based on the claims of the present application. The present application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present application, some specific details are omitted in the description. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0107] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An operational amplifier circuit, characterized in that: It includes an amplification module, which includes a first amplification unit, a second amplification unit and a modulation unit; wherein, The first amplifying unit is used to receive a first differential signal, and the second amplifying unit is used to receive a second differential signal; The first amplifying unit has a first output node, and the first amplifying unit outputs a first difference signal between the first differential signal and the second differential signal through the first output node; The second amplifying unit has a second output node, and the second amplifying unit outputs a second difference signal between the first differential signal and the second differential signal through the second output node; The modulation unit is connected to the first output node and the second output node respectively, and the output end of the modulation unit is the output end of the amplification module. The output end of the modulation unit is alternately connected to the first output node and the second output node to periodically and alternately output the first difference signal and the second difference signal.

2. The operational amplifier circuit according to claim 1, characterized in that: The modulation unit is used to connect the first output node and the output end of the modulation unit when receiving a first control signal, and is used to connect the second output node and the output end of the modulation unit when receiving a second control signal.

3. The operational amplifier circuit according to claim 2, characterized in that: The modulation unit includes a first modulation transistor, a second modulation transistor, a third modulation transistor and a fourth modulation transistor of the same doping type; The first end of the first modulation transistor and the first end of the third modulation transistor are both connected to the first output node, and the first end of the second modulation transistor and the first end of the fourth modulation transistor are both connected to the second output node; The second end of the first modulation transistor is connected to the second end of the second modulation transistor, and the second end of the third modulation transistor is connected to the second end of the fourth modulation transistor; The gate of the first modulation transistor and the gate of the fourth modulation transistor are both used to receive an inverted clock signal, and the gate of the second modulation transistor and the gate of the third modulation transistor are both used to receive a clock signal.

4. The operational amplifier circuit according to claim 3, characterized in that: The doping types of the first modulation transistor, the second modulation transistor, the third modulation transistor and the fourth modulation transistor are all N-type; or, The doping types of the first modulation transistor, the second modulation transistor, the third modulation transistor and the fourth modulation transistor are all P-type.

5. The operational amplifier circuit according to claim 3, characterized in that: The first amplifying unit includes a first amplifying transistor and a second amplifying transistor, the second amplifying unit includes a third amplifying transistor and a fourth amplifying transistor, the first amplifying transistor and the third amplifying transistor have the same doping type, the second amplifying transistor and the fourth amplifying transistor have the same doping type, and the first amplifying transistor and the second amplifying transistor have opposite doping types; Wherein, the first end of the first amplifying transistor and the first end of the second amplifying transistor are both connected to the first output node, and the first end of the third amplifying transistor and the first end of the fourth amplifying transistor are both connected to the second output node; The gate of the first amplifying transistor and the gate of the third amplifying transistor are both connected to a first bias voltage, and the gate of the second amplifying transistor and the gate of the fourth amplifying transistor are both connected to a second bias voltage.

6. The operational amplifier circuit according to claim 5, characterized in that: The operational amplifier circuit also includes a current source module and a current drain module; Wherein, the first end of the current source module is connected to the second end of the first amplifying transistor, and the second end of the current source module is connected to the second end of the third amplifying transistor; The first end of the current drain module is connected to the second end of the second amplifying transistor, and the second end of the current drain module is connected to the second end of the fourth amplifying transistor.

7. The operational amplifier circuit according to claim 6, characterized in that: The current source module includes a first transistor and a second transistor, the current drain module includes a third transistor and a fourth transistor, the first transistor and the second transistor have the same doping type, the third transistor and the fourth transistor have the same doping type, and the first transistor and the third transistor have opposite doping types; The first end of the first transistor and the first end of the second transistor are both connected to a power supply voltage, the gate of the first transistor is connected to the gate of the second transistor, the second end of the first transistor is connected to the second end of the first amplifying transistor, and the second end of the second transistor is connected to the second end of the third amplifying transistor; The first end of the third transistor and the first end of the fourth transistor are both grounded, the gate of the third transistor is connected to the gate of the fourth transistor, the second end of the third transistor is connected to the second end of the second amplifying transistor, and the second end of the fourth transistor is connected to the second end of the fourth amplifying transistor.

8. The operational amplifier circuit according to claim 7, characterized in that: The operational amplifier circuit further includes an input module, and the modulation unit further includes a feedback terminal; The input module is connected to the second end of the third transistor and the second end of the fourth transistor, and the feedback end is connected to the gate of the third transistor and the gate of the fourth transistor; or the input module is connected to the second end of the first transistor and the second end of the second transistor, and the feedback end is connected to the gate of the first transistor and the gate of the second transistor.

9. The operational amplifier circuit according to claim 8, characterized in that: The first end of the input module is connected to the first input end of the operational amplifier circuit, and the second end of the input module is connected to the second input end of the operational amplifier circuit; The third end of the input module is connected to the second end of the second amplifying transistor and the second end of the third transistor, and the fourth end of the input module is connected to the second end of the fourth amplifying transistor and the second end of the fourth transistor; The output end of the modulation unit is connected to the second end of the first modulation transistor and the second end of the second modulation transistor, the feedback end of the modulation unit is connected to the second end of the third modulation transistor and the second end of the fourth modulation transistor, the feedback end of the modulation unit is also connected to the gate of the third transistor and the gate of the fourth transistor, and the gate of the first transistor and the gate of the second transistor are connected to a third bias voltage.

10. The operational amplifier circuit according to claim 9, characterized in that: The input module comprises a first input transistor, a second input transistor and a third input transistor, wherein the first input transistor, the second input transistor, the third input transistor, the first transistor and the second transistor have the same doping type; Among them, the gate of the first input transistor is connected to the fourth bias voltage, the first end is connected to the power supply voltage, and the second end is connected to the first end of the second input transistor and the first end of the third input transistor; the gate of the second input transistor serves as the first end of the input module, and the second end is connected to the second end of the second amplifying transistor and the second end of the third transistor; the gate of the third input transistor serves as the second end of the input module, and the second end is connected to the second end of the fourth amplifying transistor and the second end of the fourth transistor.

11. The operational amplifier circuit according to claim 8, characterized in that: The first end of the input module is connected to the first input end of the operational amplifier circuit, and the second end of the input module is connected to the second input end of the operational amplifier circuit; The third end of the input module is connected to the second end of the first amplifying transistor and the second end of the first transistor, and the fourth end of the input module is connected to the second end of the third amplifying transistor and the second end of the second transistor; The output end of the modulation unit is connected to the second end of the third modulation transistor and the second end of the fourth modulation transistor, the feedback end of the modulation unit is connected to the second end of the first modulation transistor and the second end of the second modulation transistor, the feedback end of the modulation unit is also connected to the gate of the first transistor and the gate of the second transistor, and the gate of the third transistor and the gate of the fourth transistor are connected to a third bias voltage.

12. The operational amplifier circuit according to claim 11, characterized in that: The input module comprises a first input transistor, a second input transistor and a third input transistor, wherein the first input transistor, the second input transistor, the third input transistor, the third transistor and the fourth transistor have the same doping type; Among them, the gate of the first input transistor is connected to the fourth bias voltage, the first end is grounded, and the second end is connected to the first end of the second input transistor and the first end of the third input transistor; the gate of the second input transistor serves as the first end of the input module, and the second end is connected to the second end of the first amplifying transistor and the second end of the first transistor; the gate of the third input transistor serves as the second end of the input module, and the second end is connected to the second end of the third amplifying transistor and the second end of the second transistor.

13. The operational amplifier circuit according to claim 10 or 12, characterized in that: The operational amplifier circuit further includes a first chopping module, wherein the first chopping module includes a first chopping transistor, a second chopping transistor, a third chopping transistor and a fourth chopping transistor of the same doping type; Among them, the gate of the first chopper transistor and the gate of the fourth chopper transistor are both used to receive the inverted clock signal, the gate of the second chopper transistor and the gate of the third chopper transistor are both used to receive the clock signal, the first end of the first chopper transistor and the first end of the third chopper transistor are both connected to the first input end of the operational amplifier circuit, the first end of the second chopper transistor and the first end of the fourth chopper transistor are both connected to the second input end of the operational amplifier circuit, the second end of the first chopper transistor and the second end of the second chopper transistor are both connected to the first end of the input module, and the second end of the third chopper transistor and the second end of the fourth chopper transistor are both connected to the second end of the input module.

14. The operational amplifier circuit according to claim 10 or 12, characterized in that: The operational amplifier circuit further includes a second chopping module, wherein the second chopping module includes a fifth chopping transistor, a sixth chopping transistor, a seventh chopping transistor and an eighth chopping transistor of the same doping type; Among them, the gate of the fifth chopper transistor and the gate of the eighth chopper transistor are both used to receive the inverted clock signal, the gate of the sixth chopper transistor and the gate of the seventh chopper transistor are both used to receive the clock signal, the first end of the fifth chopper transistor and the first end of the seventh chopper transistor are both connected to the second end of the first transistor, the first end of the sixth chopper transistor and the first end of the eighth chopper transistor are both connected to the second end of the second transistor, the second end of the fifth chopper transistor and the second end of the sixth chopper transistor are both connected to the second end of the first amplifying transistor, and the second end of the seventh chopper transistor and the second end of the eighth chopper transistor are both connected to the second end of the third amplifying transistor.

15. The operational amplifier circuit according to claim 10 or 12, characterized in that: The operational amplifier circuit further includes a third chopping module, and the third chopping module includes a ninth chopping transistor, a tenth chopping transistor, an eleventh chopping transistor, and a twelfth chopping transistor of the same doping type; Among them, the gate of the ninth chopper transistor and the gate of the twelfth chopper transistor are both used to receive the inverted clock signal, the gate of the tenth chopper transistor and the gate of the eleventh chopper transistor are both used to receive the clock signal, the first end of the ninth chopper transistor and the first end of the eleventh chopper transistor are both connected to the second end of the second amplifying transistor, the first end of the tenth chopper transistor and the first end of the twelfth chopper transistor are both connected to the second end of the fourth amplifying transistor, the second end of the ninth chopper transistor and the second end of the tenth chopper transistor are both connected to the second end of the third transistor, and the second end of the eleventh chopper transistor and the second end of the twelfth chopper transistor are both connected to the second end of the fourth transistor.

16. The operational amplifier circuit according to any one of claims 1 to 12, characterized in that: The operational amplifier circuit further includes a filtering module, the filtering module includes a first capacitor and a first resistor, one end of the first resistor is connected to the output end of the amplifier module, the other end is connected to one end of the first capacitor, and the other end of the first capacitor is grounded; Alternatively, the filtering module includes a first capacitor, one end of which is connected to the output end of the amplifying module, and the other end of which is grounded.

17. A chip, characterized in that: The chip includes the operational amplifier circuit according to any one of claims 1 to 16.

18. An electronic device, characterized in that: The electronic device comprises the operational amplifier circuit according to any one of claims 1 to 16.

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