Random calculation digital filter and configuration method thereof

Abstract

The invention provides a random calculation digital filter and a configuration method thereof. The random calculation digital filter comprises a random source generation unit, a channel number generation unit, a convolution core unit and a reconstruction unit, according to the invention, the problems of large power consumption delay and high circuit hardware cost of a traditional random calculation digital filter design coding continuous signal are solved. By introducing dynamic coding, high-precision coding of continuous signals is realized, and circuit power consumption and operation period are reduced; according to the continuous signal random calculation digital filter, the hardware cost is reduced by inserting the D trigger, and the calculation accuracy of the circuit is improved by applying bit signal selection, rearrangement and inverse signal selection, so that the continuous signal random calculation digital filter with high accuracy and low cost is realized.

Description

Technical Field

[0001] The invention belongs to the field of digital filters, and in particular relates to a random calculation digital filter and a configuration method thereof. Background Art

[0002] Stochastic computing (SC) is an unconventional computing paradigm that significantly reduces the circuit hardware area cost by converting traditional binary sequences into random sequences and using simple logic gates to implement complex logic function operations. Due to its advantages such as simple logical structure, low energy consumption and high fault tolerance, stochastic circuits have received widespread attention in recent years and have been effectively applied in many scenarios.

[0003] Traditional a-order digital filters usually require (a+1) multipliers and a adders to implement convolution operations. The circuit structure is complex and consumes a lot of hardware resources. Combining random calculations with digital filters can effectively solve this problem. With its unique advantages, random calculations show good adaptability in digital filter design. However, random calculations also face some challenges, such as long operation time required for high-precision calculations, large hardware costs for random number conversion modules, and the correlation of random number streams affecting calculation accuracy. In order to obtain a better random calculation digital filter circuit structure, some strategies have been proposed in relevant literature. The literature [Chippa VK, Venkataramani S, Roy K, Raghunathan A. Storm: Astochastic recognition and mining processor [C]. IEEE / ACM International Symposium on Low Power Electronics and Design (ISLPED), La Jolla, CA, 2014: 39-44.] mentions reducing the hardware cost of the random number generator by sharing the random number source, but this approach inevitably causes high correlation between output sequences. In addition, the literature [Y.-N.Chang and KKParhi, "Architectures for digital filters using stochastic computing," 2013IEEEInternational Conference on Acoustics, Speech and Signal Processing, Vancouver, BC, Canada, 2013, pp.2697-2701.] attempts to apply traditional stochastic computing to digital filters. Although the obtained structure is more compact than the traditional digital filter, the generation of random numbers still requires the use of (a+1) random generator circuits, which has a high hardware cost.In the literature [H.Ichihara, T.Sugino, S.Ishii, T.Iwagaki and T.Inoue,"Compact and accurate digital filters based on stochastic computing,"in IEEE Transactions on Emerging Topics in Computing, vol.7, no.1, pp.31-43, 1Jan.-March 2019.], an optimized stochastic computing digital filter design is adopted to obtain a more compact circuit structure while maintaining high circuit accuracy. However, this design requires a longer clock cycle during the encoding process, which limits the computing processing speed to a certain extent and reduces its value in practical use. Summary of the invention

[0004] The purpose of the present invention is to provide a random calculation digital filter and a configuration method thereof to reduce the circuit hardware cost and improve the circuit calculation accuracy in view of the deficiencies in the prior art.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is:

[0006] A random computing digital filter comprises a random source generation unit, a channel number generation unit, a convolution core unit, and a reconstruction unit;

[0007] The convolution core unit includes an XOR gate and a multiplexer;

[0008] The random source generation unit includes a first n-bit random source, a first bit signal selection element, a first n-bit rearrangement element, a first n-bit inverse signal selection element, a first comparator, and a D flip-flops; the random source generation unit is used to generate a+1 random bit streams as the input sequence of the convolution core unit;

[0009] The channel number generating unit includes 1 second n-bit random source, 1 second bit signal selecting element, m second n-bit rearrangement elements, m second n-bit anti-signal selecting elements, and m second comparators; the channel number generating unit is used to generate m random bit streams as channel coefficients of the convolution core unit;

[0010] The reconstruction unit includes a third n-bit random source, a third bit signal selection element, a third n-bit rearrangement element, a third n-bit anti-signal selection element, a third comparator, and a counter; the reconstruction unit is used to integrate the output sequence of the convolution core unit to obtain a filtering result;

[0011] Where n is the bit width of the random source sequence, and a is the order of the random calculation digital filter.

[0012] The present invention overcomes the problems of large power consumption delay and high circuit hardware cost in the design of traditional random calculation digital filter for encoding continuous signals. By introducing dynamic coding to achieve high-precision encoding of continuous signals, the circuit power consumption and operation cycle are reduced; by inserting D flip-flops to reduce hardware costs, and by applying bit signal selection, rearrangement and inverse signal selection, the calculation accuracy of the circuit is improved, thereby realizing a high-accuracy, low-cost continuous signal random calculation digital filter.

[0013] Furthermore, the a+1 random bit streams are Among them, X i , X i-1 , X i-2 , …, X i-a Input to the random computation digital filter.

[0014] Further, the first end of the first-bit signal selection element is connected to the first n-bit random source, the second end of the first-bit signal selection element is connected to the first end of the first n-bit inverse signal selection element, the second end of the first n-bit inverse signal selection element is connected to the first end of the first n-bit rearrangement element, the second end of the first n-bit rearrangement element is connected to the first end of the first comparator, the second end of the first comparator is connected to the first ends of the a D flip-flops, and the second ends of the a D flip-flops are connected to the first end of the convolution core unit.

[0015] Further, the first end of the second bit signal selection element is connected to the second n-bit random source, the first end of the second bit signal selection element is connected to the second n-bit random source, and the second end of the second bit signal selection element is connected to the first ends of the m second n-bit anti-signal selection elements;

[0016] The second end of the second n-bit inverted signal selection element is connected to the first end of the second n-bit rearrangement element, and the second end of the second n-bit rearrangement element is connected to the first end of the second comparator; the m second n-bit inverted signal selection elements are connected in parallel, the m second n-bit rearrangement elements are connected in parallel, and the m second comparators are connected in parallel;

[0017] The second ends of the m second comparators are connected to the second end of the convolution core unit.

[0018] Further, a first end of the third bit signal selection element is connected to the third n-bit random source, a second end of the third bit signal selection element is connected to a first end of the third n-bit inverse signal selection element, a second end of the third n-bit inverse signal selection element is connected to a first end of the third n-bit rearrangement element, and a second end of the third n-bit rearrangement element is connected to a first end of the third comparator;

[0019] The third end of the convolution core unit is connected to the first end of the counter, and the second end of the counter is connected to the second end of the third comparator.

[0020] Based on the same inventive concept, the present invention also provides a configuration method for a random calculation digital filter, comprising the following process:

[0021] S1: Initialize the configuration mode of the random calculation digital filter, the configuration mode includes: the number of bits selected by the bit signal selection element, the number of bits rearranged by the n-bit rearrangement element, and the number of bits inverted by the n-bit inverse signal selection element;

[0022] S2: Based on the initial configuration, simulation is performed to obtain the initial calculation accuracy MAE min ;

[0023] S3: updating the configuration mode of the random calculation digital filter, and obtaining the calculation accuracy MAE of the configuration mode through simulation;

[0024] S4: If MAE <MAE min , update MAE min is MAE;

[0025] S5: Repeat steps S3-S4 until all the configurations of random calculation digital filters are traversed and MAE is selected min The corresponding configuration method is taken as the optimal configuration method.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The present invention overcomes the problems of large power consumption delay and high circuit hardware cost in the design of traditional random calculation digital filter for encoding continuous signals. By introducing dynamic coding to achieve high-precision encoding of continuous signals, the circuit power consumption and operation cycle are reduced; by inserting D flip-flops to reduce hardware costs, and by applying bit signal selection, rearrangement and inverse signal selection, the calculation accuracy of the circuit is improved, thereby realizing a high-accuracy, low-cost continuous signal random calculation digital filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural schematic diagram of the random calculation digital filter of the present invention;

[0029] Figure 2 A schematic diagram of selecting components for a 5-bit inverse signal;

[0030] Figure 3 is a schematic diagram of a 4-bit rearrangement element;

[0031] Figure 4 Schematic diagram of selecting components for bit signals;

[0032] Figure 5 This is a schematic diagram of the structure of a traditional fourth-order random computing digital filter.

[0033] Figure 6 It is a schematic diagram of the structure of the fourth-order random calculation digital filter of the present invention. DETAILED DESCRIPTION

[0034] The present invention will be described in detail below in conjunction with the embodiments. It should be noted that the embodiments and features of the embodiments of the present invention can be combined with each other without conflict. For the convenience of description, if the words "upper", "lower", "left" and "right" appear in the following, they only indicate that the upper, lower, left and right directions are consistent with the drawings themselves, and do not limit the structure.

[0035] Example 1

[0036] like Figure 1-Figure 4 , a continuous signal random calculation digital filter of this embodiment includes an n-bit random source, a bit signal selection element, an n-bit rearrangement element, an n-bit anti-signal selection element, a comparator, and a D flip-flops, which are used to generate a+1 random bit streams as input values ​​of the convolution core circuit. An n-bit random source, a bit signal selection element, m n-bit rearrangement elements, and m n-bit anti-signal selection elements are used to generate m random bit streams as channel coefficients of the convolution core circuit. And an XOR gate and a multiplexer of the convolution core circuit. There is also a reconstruction circuit for integrating the random target sequence calculated by the convolution core circuit, including an n-bit random source, a bit signal selection element, an n-bit rearrangement element, an n-bit anti-signal selection element, a comparator, and an up-down counter.

[0037] The n-bit random number generated by the n-bit random source, the bit signal selection element, the n-bit rearrangement element, the n-bit anti-signal selection element and the n-bit continuous input X i Comparison produces a value of A random bit stream based on the value of The random bit stream is passed through a D flip-flops to generate another a values. A random bit stream; m mutually independent random bit streams are generated by an n-bit random source, a bit signal selection element, an n-bit rearrangement element, and an n-bit anti-signal selection element as channel coefficients of the convolution core circuit, for example, through an a-order filter output function It can be obtained that the channel coefficients of the first-order digital filter have fixed probability values where h i The filter coefficient of the digital filter is usually determined according to the required filtering effect. The convolution core circuit is based on a+1 continuous input values ​​of random bit streams and channel coefficient values ​​of m independent random bit streams. It implements the convolution function through XOR gates and multiplexers to obtain the random sequence calculation results, and then obtains and outputs the final binary calculation results through the reconstruction circuit.

[0038] Preferably, the fourth-order random calculation digital filter includes an 8-bit random source, a bit signal selection element, an 8-bit rearrangement element, an 8-bit anti-signal selection element, a comparator, 4 D flip-flops, used to generate 5 random bit streams as convolution core circuit input values; an 8-bit random source, a bit signal selection element, 3 8-bit rearrangement elements, 3 8-bit anti-signal selection elements, used to generate 3 random bit streams as convolution core circuit channel coefficients; and an XOR gate and a multiplexer for implementing the convolution calculation of the fourth-order digital filter. There is also a reconstruction circuit for integrating the random target sequence calculated by the convolution core circuit, including an 8-bit random source, a bit signal selection element, an 8-bit rearrangement element, an 8-bit anti-signal selection element, a comparator, and an up-down counter;

[0039] An 8-bit random number generated by an 8-bit random source, a bit signal selection element, an 8-bit rearrangement element, an 8-bit anti-signal selection element, and an 8-bit continuous input X i Comparison produces a value of A random bit stream based on the value of The random bit stream passes through 4 D flip-flops to generate another 4 values. A random bit stream; an 8-bit random source, a bit signal selection element, an 8-bit rearrangement element, and an 8-bit anti-signal selection element generate three independent random bit streams as channel coefficients of the convolution circuit, which are The random calculation convolution core circuit is based on 5 continuous input values ​​of random bit streams and the channel coefficient values ​​of 3 independent random bit streams. It realizes the convolution function through XOR gates and multiplexers to obtain random sequence calculation results, and then obtains and outputs the final binary calculation results through reconstruction circuits.

[0040] This embodiment provides a random calculation digital filter design and configuration method. The definitions and assumptions used in the random calculation digital filter design and configuration method are as follows: for a bit signal selection element that selects m bits from n bits, its possible configuration mode set is B, and the i-th configuration mode is B i , then the number of elements in set B is represents all possible combinations of selecting m numbers from n bits, assuming that B1 represents the selection of the 1st to mth bits to output. For a k-bit permutation element that permutes k bits, the set of possible configurations is R k , the i-th configuration is Then R k The number of elements in the set is k!, assuming and Represents inverting k bits and keeping the order of k bits as they are. For the k-bit inverting signal selection element that selects some bits from k bits to be inverted, the set of possible configurations is C k , the i-th configuration is Then C k The number of elements in the set is 2 k , assuming represents that all k bits are inverted. The set of configurations of n-bit random sources is L, and the i-th configuration is L i , assuming that the number of elements in the collection is l.

[0041] The random calculation digital filter design configuration method uses the above definitions and assumptions to optimize the configuration of the bit signal selection element, n-bit rearrangement element, and n-bit anti-signal selection element of the random calculation digital filter design, thereby improving the calculation accuracy of the random calculation digital filter design.

[0042] Preferably, the random computation digital filter design configuration method is an iterative optimization configuration method, comprising the following steps:

[0043] P1, initialization configuration, use L1 to configure n-bit random source, use B1 to configure bit signal selection element, use Configure n-bit inverted signal selection element, use Configure n-bit rearrangement elements, and record it as the optimal configuration of the corresponding elements;

[0044] P2. Based on the optimal configuration, simulation is performed to obtain the initial calculation accuracy MAE min , and assign it to MAE prev , MAE prev The calculation accuracy obtained by simulation for a certain configuration;

[0045] P3, assign i=1;

[0046] P4, assign j = 1;

[0047] P5, assign k=1;

[0048] P6. Randomly generate integers r_1, r_2, r_3, whose range is 1≤r_o≤l, 1≤o≤3; randomly generate integers j_1, j_2, ..., j_p, whose range is 1≤j_p≤2 n ,1≤p≤m+2; randomly generate integers k_1,k_2,...,k_q, whose range is 1≤k_q≤2 n ,1≤q≤m+2; use L r Configure n-bit random source, using B i Configure the bit signal selection component and use Configure n-bit inverted signal selection element, use configuring an n-bit rearrangement element;

[0049] P7. Based on the configuration of step P6, simulate and obtain the calculation accuracy MAE of the configuration mode; if MAE <MAE min , update the optimal configuration of n-bit random source, bit signal selection element, and n-bit anti-signal selection element to L r _o, B i _o, and Update MAE min is MAE; k = k + 1;

[0050] P8, if k≤n!, jump to step P6, otherwise proceed to the next step;

[0051] P9, j = j + 1;

[0052] P10, if j≤2 n , jump to step P5, otherwise proceed to the next step;

[0053] P11, i=i+1;

[0054] P12, if Jump to step P4, otherwise proceed to the next step;

[0055] P13. If MAE min <MAE prev , update MAE prev For MAE min , jump to step S3, otherwise end the whole process and obtain the optimal configuration of all components.

[0056] By calculating the theoretical value of the random digital filter output, the average absolute value error between the theoretical value and the simulation result is selected to measure the accuracy of the calculation result.

[0057] The random calculation digital filter of this embodiment overcomes the problem of high hardware cost of traditional random calculation digital filter circuit design. By introducing a dynamic coding method, variable signals are encoded into random sequences, which achieves high precision while reducing circuit power consumption and operation cycle, and improving calculation processing speed; by inserting a D flip-flop, the number of random sources and comparators is reduced, which greatly reduces the hardware cost of the circuit and can achieve a 58.28% reduction in hardware cost; by adopting bit signal selection, rearrangement and inverse signal selection, and applying a configuration algorithm for configuration, the encoded continuous signal achieves high calculation accuracy, and the circuit calculation accuracy is better.

[0058] Example 2

[0059] Figure 5 This is a schematic diagram of the circuit structure of a traditional fourth-order stochastic computing digital filter. The traditional fourth-order stochastic computing digital filter circuit is obtained from the literature [H.Ichihara, T.Sugino, S.Ishii, T.Iwagaki and T.Inoue, "Compact and accurate digital filters based on stochastic computing," in IEEE Transactions on Emerging Topics in Computing, vol.7, no.1, pp.31-43, 1Jan.-March2019.], which requires 5 values The random bit stream input has three values: The random bit stream channel coefficient has a fixed probability value. To generate 8 random bit streams, the traditional fourth-order random calculation digital filter circuit uses 8 8-bit random sources and 8 comparators. A linear feedback shift register is used as a random source. An 8-bit linear feedback shift register of the random circuit of the traditional fourth-order random calculation digital filter generates an 8-bit random binary number per clock, which is consistent with the continuous input X i Compare in comparator, if the random binary number is less than X i , the comparator outputs 1, otherwise it outputs 0, as the value The signal input circuit of the random bit stream is used, and the channel coefficient is obtained by the comparator to obtain a random sequence with a fixed probability value, and the random sequence output value is obtained by the XOR gate and the multiplexer operation. After 255 clocks, the result of the output random bit stream is summed and divided by 256 to obtain the calculation result of the traditional fourth-order random calculation digital filter circuit.

[0060] Figure 6 1 is a schematic diagram of the structure of a fourth-order random calculation digital filter according to an embodiment of the present invention. The fourth-order random calculation digital filter according to this embodiment uses three 8-bit linear feedback shift registers, three bit signal selection elements, five 8-bit rearrangement elements, five 8-bit inverse signal selection elements, three comparators and four D flip-flops. The output of the linear feedback shift register of the fourth-order random calculation digital filter according to this embodiment is recombined through the 8-bit rearrangement element and the 8-bit inverse signal selection element and is combined with the continuous input X i After comparison, a value is generated This random bit stream passes through 4 D flip-flops, generating 4 other values The four values ​​are input into the random convolution core circuit through the corresponding input ports. The channel coefficients of the random convolution core circuit are generated by an 8-bit random source, a bit signal selection element, three 8-bit rearrangement elements and an 8-bit anti-signal selection element with fixed probability values. In addition, the fourth-order random calculation digital filter of this embodiment reconstructs the random output sequence of the convolution core circuit, and obtains the final binary output result by reconstructing the circuit, and only one operation cycle is required to obtain an output result value. In terms of hardware cost, the fourth-order random calculation digital filter circuit for calculating continuous signals implemented by this embodiment has a circuit area of ​​235.74 square microns for the random number generator, which is much smaller than the circuit area of ​​565.04 square microns of the traditional design, and the area is reduced by 58.28%, and the operation cycle is reduced from 255 to 1. The standard cell library used here is the Nangate Standard 45nm Cell Library. In terms of calculation accuracy, the circuit implemented in this embodiment is configured by the iterative optimization method, and its average absolute value error is 0.0460 under the condition of a sampling rate of 100,000. Increasing the sampling rate can improve the accuracy. The average absolute value error corresponding to a sampling rate of 400,000 is 0.01420. Similarly, increasing the dynamic coding calculation accuracy will also improve the accuracy of the calculation results. The average absolute value error corresponding to the calculation accuracy of 2 bits is 0.0129, which can achieve a higher accuracy.

[0061] As can be seen from the above, after the optimized design and reasonable configuration of the random calculation digital filter and its configuration method of this embodiment, the random calculation digital filter circuit reduces the operation cycle of encoding continuous signals while maintaining high calculation accuracy, and the hardware cost is greatly reduced, achieving high accuracy and low cost. Compared with traditional designs, the random calculation digital filter of this embodiment has a stronger application effect and application prospect.

[0062] The contents explained in the above embodiments should be understood as these embodiments are only used to more clearly illustrate the present invention, and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

Claims

1. A random computation digital filter, characterized in that: It includes a random source generation unit, a channel number generation unit, a convolution core unit, and a reconstruction unit; The convolution core unit includes an XOR gate and a multiplexer; The random source generation unit includes a first n-bit random source, a first bit signal selection element, a first n-bit rearrangement element, a first n-bit inverse signal selection element, a first comparator, and a D flip-flops; the random source generation unit is used to generate a+1 random bit streams as the input sequence of the convolution core unit; The channel number generating unit includes 1 second n-bit random source, 1 second bit signal selecting element, m second n-bit rearrangement elements, m second n-bit anti-signal selecting elements, and m second comparators; the channel number generating unit is used to generate m random bit streams as channel coefficients of the convolution core unit; The reconstruction unit includes a third n-bit random source, a third bit signal selection element, a third n-bit rearrangement element, a third n-bit anti-signal selection element, a third comparator, and a counter; the reconstruction unit is used to integrate the output sequence of the convolution core unit to obtain a filtering result; Where n is the bit width of the random source sequence, and a is the order of the random calculation digital filter.

2. The random computation digital filter according to claim 1, characterized in that: a+1 random bit streams are Among them, X i , X i-1 , X i-2 , …, X i-a Input to the random computation digital filter.

3. The random computation digital filter according to claim 1, characterized in that: The first end of the first-bit signal selection element is connected to the first n-bit random source, the second end of the first-bit signal selection element is connected to the first end of the first n-bit anti-signal selection element, the second end of the first n-bit anti-signal selection element is connected to the first end of the first n-bit rearrangement element, the second end of the first n-bit rearrangement element is connected to the first end of the first comparator, the second end of the first comparator is connected to the first ends of the a D flip-flops, and the second ends of the a D flip-flops are connected to the first end of the convolution core unit.

4. The random computation digital filter according to claim 1, characterized in that: The first end of the second bit signal selection element is connected to the second n-bit random source, and the second end of the second bit signal selection element is connected to the first ends of the m second n-bit anti-signal selection elements; The second end of the second n-bit inverted signal selection element is connected to the first end of the second n-bit rearrangement element, and the second end of the second n-bit rearrangement element is connected to the first end of the second comparator; the m second n-bit inverted signal selection elements are connected in parallel, the m second n-bit rearrangement elements are connected in parallel, and the m second comparators are connected in parallel; The second ends of the m second comparators are connected to the second end of the convolution core unit.

5. The random computation digital filter according to claim 1, characterized in that: The first end of the third bit signal selection element is connected to the third n-bit random source, the second end of the third bit signal selection element is connected to the first end of the third n-bit inverse signal selection element, the second end of the third n-bit inverse signal selection element is connected to the first end of the third n-bit rearrangement element, and the second end of the third n-bit rearrangement element is connected to the first end of the third comparator; The third end of the convolution core unit is connected to the first end of the counter, and the second end of the counter is connected to the second end of the third comparator.

6. A method for configuring a random computation digital filter according to any one of claims 1 to 5, characterized in that: The process includes: S1: Initialize the configuration mode of the random calculation digital filter, the configuration mode includes: the number of bits selected by the bit signal selection element, the number of bits rearranged by the n-bit rearrangement element, and the number of bits inverted by the n-bit inverse signal selection element; S2: Based on the initial configuration, simulation is performed to obtain the initial calculation accuracy MAE min ; S3: updating the configuration mode of the random calculation digital filter, and obtaining the calculation accuracy MAE of the configuration mode through simulation; S4: If MAE <MAE min , update MAE min is MAE; S5: Repeat steps S3-S4 until all the configurations of random calculation digital filters are traversed and MAE is selected min The corresponding configuration method is taken as the optimal configuration method.

Images