Latch

Abstract

The invention discloses a latch, relates to the field of integrated circuit design, and aims to solve the problem that the error rate of circuit output level is relatively high after a plurality of storage nodes of a latch circuit are impacted by particles in the prior art. The latch at least comprises an input module, a clock control module, a storage module and an output module, the first end of an input module is connected with the input end of the latch, and the second end of the input module is connected with the input end of the storage module; the output end of the storage module is connected with the first end of an output module; the second end of the output module is connected with the output end of the latch, and the input end of the clock control module is connected with the clock signal input end; the output end of the clock control module is respectively connected with the input module and the output module; the latch is used for generating an inverse signal of a corresponding level of the target node by using the storage module when particle collision occurs to the target node; therefore, the accuracy of circuit output level after a plurality of storage nodes are impacted by particles at the same time is improved.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit design, in particular to a latch. Background Art

[0002] In integrated circuit design, when particles hit microelectronic devices, the most sensitive area is usually the reverse biased PN junction. This is because the high field in the reverse biased junction depletion region can very effectively collect particle induced charges through the drift process, thereby generating a transient current at the junction contact. Taking a CMOS inverter as an example, when the output is 1, the drain of the N-type transistor is a sensitive area. When hit by a particle, it will collect negative charges, forming a transient current, and a voltage jump from 1 to 0 will occur at the inverter output. Similarly, when the output is 0, the drain of the P-type transistor is a sensitive area. When hit by a particle, it will collect positive charges, forming a transient current, and a voltage jump from 0 to 1 will occur at the inverter output. In the field of radiation-resistant circuit design, in order to improve the radiation resistance of the circuit and reduce the possibility of errors after the circuit is hit by particles, it is a common method to use design methods for radiation hardening (RHBD, Radiation Hardened By Design) to improve the radiation resistance of the circuit and reduce the possibility of errors after the circuit is hit by particles.

[0003] Existing technical means can only resist the impact of particles on a single storage node in the circuit, and the potential of the impacted storage node will be reversed and then restored to the original potential, but it cannot resist the impact of particles on multiple storage nodes, and cannot restore multiple nodes to their original levels, resulting in a high error rate of the level output of the circuit after multiple storage nodes in the latch circuit are impacted by particles, which limits the development of microelectronic devices.

[0004] Based on this, in order to reduce the error rate of the circuit after multiple storage nodes in the storage structure are hit by a single particle, it is urgently necessary to design a latch circuit that can resist particle impacts on multiple storage nodes and recover to the original level, thereby improving the accuracy of the circuit output level and solving the problem of high circuit output level error rate caused by particle impacts on multiple storage nodes in the latch circuit in the prior art. Summary of the invention

[0005] The purpose of the present invention is to provide a latch, which utilizes the circuit structure corresponding to the storage module arranged in the latch to not only ensure that no error occurs in the circuit when a single node in the circuit is hit by a particle, but also can restore the flipped level to the original level after particle impact occurs at multiple storage nodes, thereby improving the accuracy of the circuit output level; and solves the problem in the prior art that the circuit output level error rate is high after multiple storage nodes of the latch circuit are hit by particles.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] The present invention provides a latch, which at least comprises:

[0008] Input module, clock control module, storage module and output module;

[0009] The first end of the input module is connected to the input end of the latch, the second end of the input module is connected to the input end of the storage module, the output end of the storage module is connected to the first end of the output module, the second end of the output module is connected to the output end of the latch, the input end of the clock control module is connected to the clock signal input end, and the output end of the clock control module is respectively connected to the input module and the output module; wherein the transistor in the circuit structure corresponding to the storage module is an NMOS tube;

[0010] The latch is used for generating an inverse signal of a level corresponding to the target node by using the storage module when a particle collision occurs at the target node.

[0011] Preferably, the storage module may include: a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube;

[0012] The drain of the first NMOS tube is connected to the power supply terminal, the gate of the first NMOS tube is connected to the second terminal, and the source of the first NMOS tube is connected to the first terminal; the drain of the second NMOS tube is connected to the first terminal, the gate of the second NMOS tube is connected to the third terminal, and the source of the second NMOS tube is grounded; the drain of the third NMOS tube is connected to the power supply terminal, the gate of the third NMOS tube is connected to the first terminal, and the source of the third NMOS tube is connected to the second terminal; the drain of the fourth NMOS tube is connected to the second terminal, the gate of the fourth NMOS tube is connected to the fourth terminal, and the source of the fourth NMOS tube is grounded.

[0013] Preferably, the storage module may further include: a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube;

[0014] The drain of the fifth NMOS tube is connected to the power supply terminal, the gate of the fifth NMOS tube is connected to the fourth terminal, and the source of the fifth NMOS tube is connected to the third terminal; the drain of the sixth NMOS tube is connected to the third terminal, the gate of the sixth NMOS tube is connected to the first terminal, and the source of the sixth NMOS tube is grounded; the drain of the seventh NMOS tube is connected to the power supply terminal, the gate of the seventh NMOS tube is connected to the third terminal, and the source of the seventh NMOS tube is connected to the fourth terminal; the drain of the eighth NMOS tube is connected to the fourth terminal, the gate of the eighth NMOS tube is connected to the second terminal, and the source of the eighth NMOS tube is grounded.

[0015] Preferably, the input module may include: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube;

[0016] The source of the first PMOS tube is connected to the power supply terminal, the gate of the first PMOS tube is connected to the latch input terminal, the drain of the first PMOS tube is connected to the gate of the second PMOS tube, and the drain of the first PMOS tube is connected to the gate of the sixth PMOS tube; the gate of the ninth NMOS tube is connected to the latch input terminal, the drain of the ninth NMOS tube is connected to the drain of the first PMOS tube, and the source of the ninth NMOS tube is grounded; the source of the second PMOS tube is connected to the power supply terminal, and the drain of the second PMOS tube is connected to the gate of the fourth PMOS tube; the gate of the tenth NMOS tube is connected to the gate of the second PMOS tube, and the tenth NMOS tube is connected to the gate of the second PMOS tube. The drain of the S tube is connected to the drain of the second PMOS tube, and the source of the tenth NMOS tube is grounded; the source of the third PMOS tube is connected to the power supply terminal, the gate of the third PMOS tube is connected to the clock signal terminal, and the drain of the third PMOS tube is connected to the source of the fourth PMOS tube; the drain of the fourth PMOS tube is connected to the first terminal; the gate of the eleventh NMOS tube is connected to the gate of the fourth PMOS tube, the drain of the eleventh NMOS tube is connected to the first terminal, and the source of the eleventh NMOS tube is connected to the drain of the twelfth NMOS tube; the gate of the twelfth NMOS tube is connected to the clock anti-signal terminal, and the source of the twelfth NMOS tube is grounded;

[0017] The source of the fifth PMOS tube is connected to the power supply terminal, the gate of the fifth PMOS tube is connected to the clock signal terminal, the drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube; the drain of the sixth PMOS tube is connected to the third terminal; the gate of the thirteenth NMOS tube is connected to the gate of the sixth PMOS tube, the drain of the thirteenth NMOS tube is connected to the third terminal, the source of the thirteenth NMOS tube is connected to the drain of the fourteenth NMOS tube; the gate of the fourteenth NMOS tube is connected to the clock anti-signal terminal, and the source of the fourteenth NMOS tube is grounded.

[0018] Preferably, the output module may include: a seventh PMOS tube, an eighth PMOS tube, an eleventh PMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube and a nineteenth NMOS tube;

[0019] The source of the seventh PMOS tube is connected to the power supply terminal, the gate of the seventh PMOS tube is connected to the clock inverse signal terminal, and the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube; the drain of the eighth PMOS tube is connected to the gate of the eleventh PMOS tube, and the gate of the eighth PMOS tube is connected to the second terminal; the drain of the fifteenth NMOS tube is connected to the drain of the eighth PMOS tube, the gate of the fifteenth NMOS tube is connected to the second terminal, and the source of the fifteenth NMOS tube is connected to the drain of the sixteenth NMOS tube; the gate of the sixteenth NMOS tube is connected to the clock signal terminal, and the source of the sixteenth NMOS tube is grounded; the source of the eleventh PMOS tube is connected to the power supply terminal, and the drain of the eleventh PMOS tube is connected to the first output terminal of the latch; the gate of the nineteenth NMOS tube is connected to the gate of the eleventh PMOS tube, the drain of the nineteenth NMOS tube is connected to the first output terminal of the latch, and the source of the nineteenth NMOS tube is grounded.

[0020] Preferably, the output module may further include: a ninth PMOS tube, a tenth PMOS tube, a twelfth PMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube and a twentieth NMOS tube;

[0021] The source of the ninth PMOS tube is connected to the power supply terminal, the gate of the ninth PMOS tube is connected to the clock inverse signal terminal, and the drain of the ninth PMOS tube is connected to the source of the tenth PMOS tube; the drain of the tenth PMOS tube is connected to the gate of the twelfth PMOS tube, and the gate of the tenth PMOS tube is connected to the fourth terminal; the drain of the seventeenth NMOS tube is connected to the drain of the tenth PMOS tube, the gate of the seventeenth NMOS tube is connected to the fourth terminal, and the source of the seventeenth NMOS tube is connected to the drain of the eighteenth NMOS tube; the gate of the eighteenth NMOS tube is connected to the clock signal terminal, and the source of the eighteenth NMOS tube is grounded; the source of the twelfth PMOS tube is connected to the power supply terminal, and the drain of the twelfth PMOS tube is connected to the second output terminal of the latch; the gate of the twentieth NMOS tube is connected to the gate of the twelfth PMOS tube, the drain of the twentieth NMOS tube is connected to the second output terminal of the latch, and the source of the twentieth NMOS tube is grounded.

[0022] Preferably, the clock control module may include: a thirteenth PMOS tube, a fourteenth PMOS tube, a twenty-first NMOS tube and a twenty-second NMOS tube;

[0023] The source of the thirteenth PMOS tube is connected to the power supply terminal, the gate of the thirteenth PMOS tube is connected to the clock signal input terminal, and the drain of the thirteenth PMOS tube is connected to the clock anti-signal terminal; the gate of the twenty-first NMOS tube is connected to the clock signal input terminal, the drain of the twenty-first NMOS tube is connected to the drain of the thirteenth PMOS tube, and the source of the twenty-first NMOS tube is grounded; the source of the fourteenth PMOS tube is connected to the power supply terminal, the gate of the fourteenth PMOS tube is connected to the drain of the thirteenth PMOS tube, and the drain of the fourteenth PMOS tube is connected to the clock signal terminal; the gate of the twenty-second NMOS tube is connected to the gate of the fourteenth PMOS tube, the drain of the twenty-second NMOS tube is connected to the clock signal terminal, and the source of the twenty-second NMOS tube is grounded.

[0024] Preferably, when the clock signal is 0, the circuit of the latch is in a write state, and the input data of the input module is 0, the sixth NMOS tube, the third NMOS tube and the eighth NMOS tube in the storage module are turned on; when the clock signal is 0, the circuit of the latch is in a write state and the input data of the input module is 1, the second NMOS tube, the seventh NMOS tube and the fourth NMOS tube in the storage module are turned on.

[0025] Preferably, when the clock signal is 1, the circuit is in a latched state, and the input data of the input module is 0, the information stored in the first terminal is 1, the information stored in the second terminal is 1 including a threshold loss, the information stored in the third terminal is 0, and the information stored in the fourth terminal is 0; the information stored in the second terminal is output through the first output terminal of the latch, and the information stored in the fourth terminal is output through the second output terminal of the latch;

[0026] When the clock signal is 1, the circuit is in a latched state, and the input data of the input module is 1; the information stored in the first terminal is 0, the information stored in the second terminal is 0, the information stored in the third terminal is 1, and the information stored in the fourth terminal is 1 including a threshold loss; the information stored in the second terminal is output through the first output terminal of the latch, and the information stored in the fourth terminal is output through the second output terminal of the latch.

[0027] Preferably, when the clock signal is 1, the circuit is in a latched state, and the input data of the input module is 0;

[0028] If the written data is 0, the information stored in the first terminal X1 is 1, the information stored in the second terminal X2 is 1 (VDD-Vth), the information stored in the third terminal X3 is 0, and the information stored in the fourth terminal X4 is 0;

[0029] When the first terminal is hit by particles, a voltage jump from 1 to 0 occurs, and the third NMOS tube and the sixth NMOS tube are switched from the on state to the off state, and the second terminal and the third terminal are switched from the low resistance state to the high resistance state potential, and remain unchanged, and the potential of the fourth terminal remains unchanged, and the first NMOS tube is switched from the off state to the on state, and the potential of the first terminal is restored to 1;

[0030] When the second terminal is hit by particles, a voltage jump from 1 to 0 occurs, the eighth NMOS tube changes from an on state to a off state, the fourth terminal changes from a low resistance state to a high resistance state, and the potential remains unchanged. The first NMOS tube remains in a closed state, the first terminal remains in a high resistance state, and the potential remains unchanged. The potential of the third terminal remains unchanged, and the third NMOS tube remains in an on state, restoring the potential of the second terminal to 1.

[0031] Compared with the prior art, the latch provided by the present invention is provided with at least an input module, a clock control module, a storage module and an output module; the first end of the input module is connected to the input end of the latch, and the second end of the input module is connected to the input end of the storage module; the output end of the storage module is connected to the first end of the output module, and the second end of the output module is connected to the output end of the latch; the input end of the clock control module is connected to the clock signal input end, and the output end of the clock control module is connected to the input module and the output module respectively; when the latch is used when a particle collision occurs at a target node, the latch uses the storage module to generate an inverse signal of a level corresponding to the target node, so that the target node outputs a correct electrical signal; due to the storage module The circuits corresponding to the blocks are all composed of N-type transistors. When the drain of the N-type transistor is hit by particles, positive charges will be collected, and only a voltage jump from 1 to 0 will occur. For the nodes storing information 0, no jump will occur even if the voltage is hit by the particle. For the nodes storing information 1, after being hit by particles, based on the circuit structure of the new storage structure, the nodes storing information 1 will eventually still output at a high level; that is, after the node storing information 1 is hit by particles, its potential will flip from 1 to 0 and then return to 1, and then output again; thereby improving the accuracy of the circuit output level after multiple storage nodes are hit by particles at the same time, and significantly reducing the error rate of the circuit output level after multiple storage nodes are hit by particles at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0033] Figure 1 A schematic diagram of a storage structure of a double interlocking storage unit structure in the prior art;

[0034] Figure 2 It is a schematic diagram of the storage structure of the Nwise structure in the prior art;

[0035] Figure 3 A schematic diagram of the main structure of a latch provided by the present invention.

[0036] Figure markings: 310 - input module, 320 - clock control module, 330 storage module, 340 - output module, X1 - first terminal, X2 - second terminal, X3 - third terminal, X4 - fourth terminal, D - latch input, CLK - clock signal input, c - clock signal, cn - clock inverse signal, Q - latch first output, QN - latch second output. DETAILED DESCRIPTION

[0037] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0038] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0039] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects in the previous time are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0040] There are two types of latches in the prior art that resist particle flipping. When a single storage node in the latch structure is hit by a particle, the potential of the hit storage node will return to its original potential after flipping. However, if multiple storage nodes in the latch structure are hit by particles, the potential of the hit storage node cannot be flipped back to its original potential. Both of them have the problem of a high error rate of the circuit output level after multiple storage nodes are hit by particles.

[0041] See also Figure 1 to Figure 2 , Figure 1 A schematic diagram of a storage structure of a double interlocking storage unit structure in the prior art; Figure 2 Schematic diagram of the storage structure of the Nwise structure in the prior art.

[0042] Figure 1The storage structure shown is a dual interlocked storage cell structure (DICE), which can achieve that when a single storage node is hit by particles, the potential of the hit storage node will recover to its original potential after flipping; if multiple storage nodes are hit by particles, the storage nodes in the DICE structure may not be able to recover to their original potential.

[0043] Figure 2 The storage structure shown is an Nwise structure, in which two storage nodes are only connected to the drain of the N-type transistor. Since the drain of the N-type transistor will collect negative charges when hit by particles, only a voltage jump of 1→0 will occur. When the potential of the two storage nodes is 0, the potential will not be reversed even if hit by particles; however, when the potential of the two storage nodes is 1, the potential will be reversed when hit by particles. Therefore, even if only a single storage node is hit by particles, errors may occur in the Nwise structure.

[0044] In view of this, in order to solve the problem that the error rate of the circuit output level is high after the multiple storage nodes of the latch circuit are hit by particles, the present invention provides a latch, which is used to generate an anti-signal of the corresponding level of the target node using a storage module when a particle collision occurs at the target node; thereby improving the accuracy of the circuit output level after multiple storage nodes are hit by particles at the same time.

[0045] Next, the technical solution of the present invention is described in detail with reference to the accompanying drawings:

[0046] See also Figure 3 , Figure 3 A schematic diagram of the main structure of a latch provided by the present invention.

[0047] exist Figure 3 In the embodiment, the latch 300 may include at least:

[0048] An input module 310, a clock control module 320, a storage module 330 and an output module 340; a first end of the input module 310 is connected to an input end of the latch 300, a second end of the input module 310 is connected to an input end of the storage module 330, an output end of the storage module 330 is connected to a first end of the output module 340, a second end of the output module 340 is connected to an output end of the latch 300, an input end of the clock control module 320 is connected to a clock signal input end, and an output end of the clock control module 320 is respectively connected to the input module 310 and the output module 340; wherein the transistor in the circuit structure corresponding to the storage module 330 is an NMOS tube; since the drain of the N-type transistor will collect positive charges when hit by particles, only a voltage jump of 1→0 will occur.

[0049] The latch 300 is used for generating an inverse signal of a level corresponding to the target node by using the storage module 330 when a particle collision occurs at the target node.

[0050] Based on this, the present invention provides a latch having a storage module with a novel storage structure, which utilizes the storage module to ensure that nodes with storage information of 0 will not jump even if they receive a particle impact voltage; for nodes with storage information of 1, after being impacted by particles, based on the circuit structure of the novel storage structure, the nodes with storage information of 1 that are impacted by particles will eventually still be output as a high level, that is, after being impacted by particles, the potential of the nodes with storage information of 1 will flip from 1 to 0 and then return to 1, and then be output again; the accuracy of the circuit output level after multiple storage nodes in the latch are simultaneously impacted by particles is improved, and the error rate of the circuit output level after multiple storage nodes are simultaneously impacted by particles is significantly reduced.

[0051] Please continue reading Figure 3 ,exist Figure 3 The storage module shown in is a storage module with a novel storage structure designed by the present invention; the storage module 330 may include: a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube.

[0052] Specifically, the drain of the first NMOS tube can be connected to the power supply terminal, the gate of the first NMOS tube can be connected to the second terminal, and the source of the first NMOS tube can be connected to the first terminal; the drain of the second NMOS tube can be connected to the first terminal, the gate of the second NMOS tube can be connected to the third terminal, and the source of the second NMOS tube can be grounded; the drain of the third NMOS tube can be connected to the power supply terminal, the gate of the third NMOS tube can be connected to the first terminal, and the source of the third NMOS tube can be connected to the second terminal; the drain of the fourth NMOS tube can be connected to the second terminal, the gate of the fourth NMOS tube can be connected to the fourth terminal, and the source of the fourth NMOS tube can be grounded.

[0053] Furthermore, the storage module 330 may further include: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor and an eighth NMOS transistor.

[0054] Specifically, the drain of the fifth NMOS tube can be connected to the power supply end, the gate of the fifth NMOS tube can be connected to the fourth terminal, and the source of the fifth NMOS tube can be connected to the third terminal; the drain of the sixth NMOS tube can be connected to the third terminal, the gate of the sixth NMOS tube can be connected to the first terminal, and the source of the sixth NMOS tube can be grounded; the drain of the seventh NMOS tube can be connected to the power supply end, the gate of the seventh NMOS tube can be connected to the third terminal, and the source of the seventh NMOS tube can be connected to the fourth terminal; the drain of the eighth NMOS tube can be connected to the fourth terminal, the gate of the eighth NMOS tube can be connected to the second terminal, and the source of the eighth NMOS tube can be grounded.

[0055] Based on this, a storage module with a novel storage structure provided by the present invention is obtained, and the storage structure is composed of 8 N-type transistors and includes 4 storage nodes. When the latch is in a latched state, due to the particle impact on the drain of the N-type transistor, only a voltage jump of 1→0 will occur, among which 2 storage nodes with storage information of 0 will not undergo voltage flipping even if they are impacted by particles, and the other 2 nodes with storage information of 1 will be in an open state after a voltage jump of 1→0 occurs, because the potential of the adjacent storage nodes is not affected, and the potential of the node where the voltage jump of 1→0 occurs is pulled back to a high level. Therefore, when only a single storage node is impacted by particles, the circuit of the present invention will not fail; compared with other storage structures, the present invention can significantly reduce the possibility of circuit errors when multiple storage nodes are impacted by particles. Compared with the prior art, the accuracy of the circuit output level after multiple storage nodes are simultaneously impacted by particles is improved.

[0056] It should be noted that, since the NMOS tube has a threshold voltage loss when transmitting a signal, the potential of the MN1 transistor gate (second terminal X2) is VDD-Vth, and the potential of the MN1 transistor source (first terminal X1) can only be restored to VDD-Vth; Vth represents the threshold voltage.

[0057] Preferably, the input module 310 may include: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube.

[0058] Specifically, the source of the first PMOS tube can be connected to the power supply terminal, the gate of the first PMOS tube can be connected to the latch input terminal D, the drain of the first PMOS tube can be connected to the gate of the second PMOS tube, and the drain of the first PMOS tube can be connected to the gate of the sixth PMOS tube; the gate of the ninth NMOS tube can be connected to the latch input terminal D, the drain of the ninth NMOS tube can be connected to the drain of the first PMOS tube, and the source of the ninth NMOS tube can be grounded; the source of the second PMOS tube can be connected to the power supply terminal, and the drain of the second PMOS tube can be connected to the gate of the fourth PMOS tube; the gate of the tenth NMOS tube can be connected to the gate of the second PMOS tube, and the gate of the tenth NMOS tube can be connected to the gate of the second NMOS tube. The drain of the MOS tube is connected to the drain of the second PMOS tube, and the source of the tenth NMOS tube is grounded; the source of the third PMOS tube is connected to the power supply terminal, the gate of the third PMOS tube is connected to the clock signal terminal, and the drain of the third PMOS tube is connected to the source of the fourth PMOS tube; the drain of the fourth PMOS tube is connected to the first terminal; the gate of the eleventh NMOS tube is connected to the gate of the fourth PMOS tube, the drain of the eleventh NMOS tube is connected to the first terminal, and the source of the eleventh NMOS tube is connected to the drain of the twelfth NMOS tube; the gate of the twelfth NMOS tube is connected to the clock negative signal terminal cn, and the source of the twelfth NMOS tube is grounded.

[0059] Further, the source of the fifth PMOS tube is connected to the power supply terminal, the gate of the fifth PMOS tube is connected to the clock signal terminal, and the drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube; the drain of the sixth PMOS tube is connected to the third terminal; the gate of the thirteenth NMOS tube is connected to the gate of the sixth PMOS tube, the drain of the thirteenth NMOS tube is connected to the third terminal, and the source of the thirteenth NMOS tube is connected to the drain of the fourteenth NMOS tube; the gate of the fourteenth NMOS tube is connected to the clock negative signal terminal cn, and the source of the fourteenth NMOS tube is grounded.

[0060] Based on this, an input module with a novel structure in a latch provided by the present invention is obtained, and the input module is used to receive data to be written into the storage module.

[0061] Preferably, the output module 340 may include: a seventh PMOS transistor, an eighth PMOS transistor, an eleventh PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor and a nineteenth NMOS transistor.

[0062] Specifically, the source of the seventh PMOS tube can be connected to the power supply terminal, the gate of the seventh PMOS tube is connected to the clock inverse signal terminal cn, and the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube; the drain of the eighth PMOS tube is connected to the gate of the eleventh PMOS tube, and the gate of the eighth PMOS tube is connected to the second terminal; the drain of the fifteenth NMOS tube is connected to the drain of the eighth PMOS tube, the gate of the fifteenth NMOS tube is connected to the second terminal, and the source of the fifteenth NMOS tube is connected to the drain of the sixteenth NMOS tube; the gate of the sixteenth NMOS tube is connected to the clock signal terminal, and the source of the sixteenth NMOS tube is grounded; the source of the eleventh PMOS tube is connected to the power supply terminal, and the drain of the eleventh PMOS tube is connected to the first output terminal Q of the latch; the gate of the nineteenth NMOS tube is connected to the gate of the eleventh PMOS tube, the drain of the nineteenth NMOS tube is connected to the first output terminal Q of the latch, and the source of the nineteenth NMOS tube is grounded.

[0063] Furthermore, the output module 340 may further include: a ninth PMOS transistor, a tenth PMOS transistor, a twelfth PMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor and a twentieth NMOS transistor.

[0064] Specifically, the source of the ninth PMOS tube can be connected to the power supply terminal, the gate of the ninth PMOS tube can be connected to the clock inverse signal terminal cn, and the drain of the ninth PMOS tube can be connected to the source of the tenth PMOS tube; the drain of the tenth PMOS tube can be connected to the gate of the twelfth PMOS tube, and the gate of the tenth PMOS tube can be connected to the fourth terminal; the drain of the seventeenth NMOS tube can be connected to the drain of the tenth PMOS tube, the gate of the seventeenth NMOS tube can be connected to the fourth terminal, and the source of the seventeenth NMOS tube can be connected to the drain of the eighteenth NMOS tube; the gate of the eighteenth NMOS tube can be connected to the clock signal terminal, and the source of the eighteenth NMOS tube can be grounded; the source of the twelfth PMOS tube can be connected to the power supply terminal, and the drain of the twelfth PMOS tube can be connected to the second output terminal QN of the latch; the gate of the twentieth NMOS tube can be connected to the gate of the twelfth PMOS tube, the drain of the twentieth NMOS tube can be connected to the second output terminal QN of the latch, and the source of the twentieth NMOS tube can be grounded.

[0065] Based on this, an output module of a novel structure in a latch provided by the present invention is obtained, and the output module is used to receive data read out from the storage module.

[0066] Preferably, the clock control module 320 may include: a thirteenth PMOS transistor, a fourteenth PMOS transistor, a twenty-first NMOS transistor and a twenty-second NMOS transistor.

[0067] Specifically, the source of the thirteenth PMOS tube can be connected to the power supply terminal, the gate of the thirteenth PMOS tube is connected to the clock signal input terminal CLK, and the drain of the thirteenth PMOS tube is connected to the clock anti-signal terminal cn; the gate of the twenty-first NMOS tube is connected to the clock signal input terminal CLK, the drain of the twenty-first NMOS tube is connected to the drain of the thirteenth PMOS tube, and the source of the twenty-first NMOS tube is grounded; the source of the fourteenth PMOS tube is connected to the power supply terminal, the gate of the fourteenth PMOS tube is connected to the drain of the thirteenth PMOS tube, and the drain of the fourteenth PMOS tube is connected to the clock signal terminal c; the gate of the twenty-second NMOS tube is connected to the gate of the fourteenth PMOS tube, the drain of the twenty-second NMOS tube is connected to the clock signal terminal c, and the source of the twenty-second NMOS tube is grounded.

[0068] Based on this, a clock control module in a latch provided by the present invention is obtained, and the clock control module is used to generate a clock signal and a clock inverse signal to an input module and an output module to realize the latching function of the latch.

[0069] Preferably, a latch provided by the present invention can realize the following functions:

[0070] 1. When the clock signal is 0, the circuit of the latch is in the write state, and the input data of the input module is 0, the sixth NMOS tube, the third NMOS tube and the eighth NMOS tube in the storage module are turned on; when the clock signal is 0, the circuit of the latch is in the write state, and the input data of the input module is 1, the second NMOS tube, the seventh NMOS tube and the fourth NMOS tube in the storage module are turned on.

[0071] 2. When the clock signal is 1, the circuit is in a latched state, and the input data of the input module is 0; the information stored in the first terminal is 1, the information stored in the second terminal is 1 including a threshold loss, the information stored in the third terminal is 0, and the information stored in the fourth terminal is 0; the information stored in the second terminal is output through the first output terminal Q of the latch, and the information stored in the fourth terminal is output through the second output terminal QN of the latch.

[0072] When the clock signal is 1, the circuit is in a latched state, and the input data of the input module is 1; the information stored in the first terminal is 0, the information stored in the second terminal is 0, the information stored in the third terminal is 1, and the information stored in the fourth terminal is 1 including a threshold loss; the information stored in the second terminal is output through the first output terminal Q of the latch, and the information stored in the fourth terminal is output through the second output terminal QN of the latch.

[0073] 3. When the clock signal is 1, the circuit is in latched state, and the input data of the input module is 0.

[0074] If the written data is 0, the information stored in the first terminal X1 is 1, the information stored in the second terminal X2 is 1 (VDD-Vth), the information stored in the third terminal X3 is 0, and the information stored in the fourth terminal X4 is 0;

[0075] When the first terminal X1 is hit by particles, a voltage jump from 1 to 0 occurs, and the third NMOS tube and the sixth NMOS tube are switched from the on state to the off state, and the second terminal X2 and the third terminal X3 are switched from the low resistance state to the high resistance state potential, and remain unchanged, and the potential of the fourth terminal X4 remains unchanged, and the first NMOS tube is switched from the off state to the on state, and the potential of the first terminal X1 is restored to 1;

[0076] When the second terminal X2 is hit by particles, a voltage jump from 1 to 0 occurs, the eighth NMOS tube changes from an on state to a off state, the fourth terminal X4 changes from a low resistance state to a high resistance state, and the potential remains unchanged, the first NMOS tube remains in a closed state, the first terminal X1 remains in a high resistance state, and the potential remains unchanged, the potential of the third terminal X3 remains unchanged, the third NMOS tube remains in an on state, and the potential of the second terminal X4 is restored to 1.

[0077] Specifically, the working principle of a latch provided by the present invention is:

[0078] 1. When the clock signal is 0, the circuit is in the write state, and the latch circuit is written through the input module.

[0079] When the input data is 0, 1 is written to X1, the 1 potential of X1 turns on the MN6 transistor, 0 is written to X3, and at the same time, the 1 potential of X1 turns on the MN3 transistor, 1 is written to X2 (due to the threshold voltage loss when the NMOS tube transmits the 1 signal, the potential of X2 is VDD-Vth), the 1 potential of X2 (VDD-Vth) turns on the MN8 transistor, and 0 is written to X4.

[0080] When the input data is 1, 1 is written to X3, the 1 potential of X3 turns on the MN2 transistor, and 0 is written to X1. At the same time, the 1 potential of X3 turns on the MN7 transistor, and 1 is written to X4 (due to the threshold voltage loss when the NMOS tube transmits the 1 signal, the potential of X4 is VDD-Vth). The 1 potential of X4 (VDD-Vth) turns on the MN4 transistor and writes 0 to X2.

[0081] 2. When the clock signal is 1, the circuit is in a latched state, and the information stored in the latch circuit is output through the output module.

[0082] When the written data is 0, the information stored in X1 is 1, the information stored in X2 is 1 (VDD-Vth), the information stored in X3 is 0, and the information stored in X4 is 0. The information 1 (VDD-Vth) stored in X2 is restored to a 1 signal without threshold loss through two inverters and output from the Q end; the information 0 stored in X4 is output from QN after passing through two inverters.

[0083] When the written data is 1, the information stored in X1 is 0, the information stored in X2 is 0, the information stored in X3 is 1, and the information stored in X4 is 1 (VDD-Vth). The information 0 stored in X2 is output from the Q end as an output signal after passing through two inverters; the information 1 (VDD-Vth) stored in X4 is restored to a 1 signal without threshold loss through two inverters and output from the QN end.

[0084] 3. The working principle of the latch's resistance to multi-node single-particle upset is: when the clock signal is 1, the circuit is in the latched state.

[0085] If the written data is 0, the information stored in X1 is 1, the information stored in X2 is 1 (VDD-Vth), the information stored in X3 is 0, and the information stored in X4 is 0. Since the drain of the N-type transistor will collect negative charges when hit by particles, only a voltage jump from 1 to 0 will occur. At this time, the two storage nodes X3 and X4 will not flip even if they are hit by particles.

[0086] When X1 is hit by particles, a voltage jump from 1 to 0 occurs, MN3 and MN6 transistors change from on to off, X2 and X3 become high impedance states, and the potential remains unchanged. X4 is not affected and the potential remains unchanged. MN1 transistor changes from off to on, restoring X1 to 1 (due to the threshold voltage loss when the NMOS tube transmits the 1 signal, the gate potential X2 of the MN1 transistor is VDD-Vth, and the potential of X1 can only be restored to VDD-2Vth).

[0087] When X2 is hit by particles, a voltage jump from 1 to 0 occurs, the MN8 transistor changes from on to off, X4 becomes high impedance and the potential remains unchanged, the MN1 transistor remains off, X1 remains high impedance and the potential remains unchanged, X3 is not affected and the potential remains unchanged, the MN3 transistor remains on, and X2 is restored to 1 (due to the threshold voltage loss when the NMOS tube transmits the 1 signal, the gate potential of the MN3 transistor X1 is VDD, and the potential of X2 can only be restored to VDD-Vth).

[0088] Similarly, the analysis when the written data is 1 is similar to that when the written data is 0; thus, it can be concluded that the latch proposed in the present invention has the following characteristics:

[0089] 1) When in the latched state, no matter which node is hit by a particle, it will not affect the output signal.

[0090] 2) Since the drain of an N-type transistor will collect negative charges when hit by particles, only a voltage jump of 1→0 will occur. Even if two nodes storing information of 0 are hit by particles, their own potentials will not be reversed, which can significantly reduce the possibility of circuit output errors after multiple storage nodes are hit by particles at the same time.

[0091] In order to more fully reflect the advantage of a latch provided by the present invention in improving the accuracy of the circuit output level after multiple storage nodes in a storage module are simultaneously hit by particles, the test data of two storage structures DICE and Nwise in the prior art and the latch with a new storage structure provided by the present invention are shown in Table 1. It should be noted that since the three storage structures all have 4 storage nodes, it can be considered that the possibility of each node being hit by particles is the same. On this basis, the possibility of failure of the three structures after different numbers of nodes are hit by particles is analyzed and calculated.

[0092] Table 1 is a comparison result of the single-particle upset resistance performance of the DICE and Nwise storage structures in the prior art and a latch provided by the present invention.

[0093]

[0094]

[0095] From Table 1, it can be clearly seen that: for a latch provided by the present invention, when there is a particle collision on one storage node, the possibility of an error is 0; when there are particle collisions on two storage nodes, the possibility of an error is 1 / 6; when there are particle collisions on three storage nodes, the possibility of an error is 1 / 2; and when there are particle collisions on four storage nodes, an error is likely to occur. Compared with the two storage structures of DICE and Nwise, the latch structure proposed by the present invention can not only ensure that the circuit does not have an error when a single node is hit by a particle, but also significantly reduce the possibility of circuit errors when multiple nodes are hit by particles; it improves the accuracy of the circuit output level after multiple storage nodes are hit by particles at the same time, and significantly reduces the error rate of the circuit output level after multiple storage nodes are hit by particles at the same time.

[0096] In practical applications, a trigger can be composed of multiple latches with the same latch circuit structure as the one provided by the present invention; for example, a trigger can be composed of one master latch and one slave latch, and the circuit structure corresponding to the trigger is: the input end of the master latch is connected to the input end of the trigger, the output end of the master latch is connected to the input end of the slave latch, and the output end of the slave latch is connected to the output end of the trigger. Among them, the circuit structure corresponding to the master latch and the slave latch is the same as the latch circuit structure provided by the present invention; the connection method of the clock signal in the master latch is the same as the connection method of the clock signal in the latch circuit provided by the present invention, and the connection method of the clock signal in the slave latch is opposite to the connection method of the clock signal in the latch circuit provided by the present invention; that is, the clock input signals of the master latch and the slave latch are opposite. For example: please refer to Figure 3 , because in practical applications, the circuit structure and clock signal of the main latch in the trigger are Figure 3 The circuit structure and clock signal shown in the figure are consistent, while the circuit structure of the slave latch in the trigger is the same as Figure 3 The circuit structure shown is the same, the difference is that the clock signal is opposite; for example, in the master-level latch, the gate of the input module MP11 is connected to the clock signal terminal c, and the gate of MN4 is connected to the clock anti-signal terminal cn; then in the slave-level latch, the gate of the transistor corresponding to MP11 in its input module is connected to the clock anti-signal terminal cn, and the gate of the transistor corresponding to MN4 is connected to the clock signal terminal c. Based on this, a trigger composed of multiple latches with the same latch circuit structure as the present invention also has the ability to resist particle impact in the latch structure, and improves the accuracy of the circuit output level after multiple storage nodes in the trigger are simultaneously impacted by particles.

[0097] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0098] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A latch, characterized in that: The latch includes at least: Input module, clock control module, storage module and output module; The first end of the input module is connected to the input end of the latch, the second end of the input module is connected to the input end of the storage module, the output end of the storage module is connected to the first end of the output module, the second end of the output module is connected to the output end of the latch, the input end of the clock control module is connected to the clock signal input end, and the output end of the clock control module is respectively connected to the input module and the output module; wherein the transistor in the circuit structure corresponding to the storage module is an NMOS tube; The latch is used for generating an inverse signal of a level corresponding to the target node by using the storage module when a particle collision occurs at the target node.

2. The latch according to claim 1, wherein: The storage module includes: a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; The drain of the first NMOS tube is connected to the power supply terminal, the gate of the first NMOS tube is connected to the second terminal, and the source of the first NMOS tube is connected to the first terminal; the drain of the second NMOS tube is connected to the first terminal, the gate of the second NMOS tube is connected to the third terminal, and the source of the second NMOS tube is grounded; the drain of the third NMOS tube is connected to the power supply terminal, the gate of the third NMOS tube is connected to the first terminal, and the source of the third NMOS tube is connected to the second terminal; the drain of the fourth NMOS tube is connected to the second terminal, the gate of the fourth NMOS tube is connected to the fourth terminal, and the source of the fourth NMOS tube is grounded.

3. The latch according to claim 2, wherein: The storage module further includes: a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube; The drain of the fifth NMOS tube is connected to the power supply terminal, the gate of the fifth NMOS tube is connected to the fourth terminal, and the source of the fifth NMOS tube is connected to the third terminal; the drain of the sixth NMOS tube is connected to the third terminal, the gate of the sixth NMOS tube is connected to the first terminal, and the source of the sixth NMOS tube is grounded; the drain of the seventh NMOS tube is connected to the power supply terminal, the gate of the seventh NMOS tube is connected to the third terminal, and the source of the seventh NMOS tube is connected to the fourth terminal; the drain of the eighth NMOS tube is connected to the fourth terminal, the gate of the eighth NMOS tube is connected to the second terminal, and the source of the eighth NMOS tube is grounded.

4. The latch according to claim 1, wherein: The input module includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube; The source of the first PMOS tube is connected to the power supply terminal, the gate of the first PMOS tube is connected to the latch input terminal, the drain of the first PMOS tube is connected to the gate of the second PMOS tube, and the drain of the first PMOS tube is connected to the gate of the sixth PMOS tube; the gate of the ninth NMOS tube is connected to the latch input terminal, the drain of the ninth NMOS tube is connected to the drain of the first PMOS tube, and the source of the ninth NMOS tube is grounded; the source of the second PMOS tube is connected to the power supply terminal, and the drain of the second PMOS tube is connected to the gate of the fourth PMOS tube; the gate of the tenth NMOS tube is connected to the gate of the second PMOS tube, and the tenth NMOS tube is connected to the gate of the second PMOS tube. The drain of the S tube is connected to the drain of the second PMOS tube, and the source of the tenth NMOS tube is grounded; the source of the third PMOS tube is connected to the power supply terminal, the gate of the third PMOS tube is connected to the clock signal terminal, and the drain of the third PMOS tube is connected to the source of the fourth PMOS tube; the drain of the fourth PMOS tube is connected to the first terminal; the gate of the eleventh NMOS tube is connected to the gate of the fourth PMOS tube, the drain of the eleventh NMOS tube is connected to the first terminal, and the source of the eleventh NMOS tube is connected to the drain of the twelfth NMOS tube; the gate of the twelfth NMOS tube is connected to the clock anti-signal terminal, and the source of the twelfth NMOS tube is grounded; The source of the fifth PMOS tube is connected to the power supply terminal, the gate of the fifth PMOS tube is connected to the clock signal terminal, the drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube; the drain of the sixth PMOS tube is connected to the third terminal; the gate of the thirteenth NMOS tube is connected to the gate of the sixth PMOS tube, the drain of the thirteenth NMOS tube is connected to the third terminal, the source of the thirteenth NMOS tube is connected to the drain of the fourteenth NMOS tube; the gate of the fourteenth NMOS tube is connected to the clock anti-signal terminal, and the source of the fourteenth NMOS tube is grounded.

5. The latch according to claim 1, wherein: The output module includes: a seventh PMOS tube, an eighth PMOS tube, an eleventh PMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube and a nineteenth NMOS tube; The source of the seventh PMOS tube is connected to the power supply terminal, the gate of the seventh PMOS tube is connected to the clock inverse signal terminal, and the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube; the drain of the eighth PMOS tube is connected to the gate of the eleventh PMOS tube, and the gate of the eighth PMOS tube is connected to the second terminal; the drain of the fifteenth NMOS tube is connected to the drain of the eighth PMOS tube, the gate of the fifteenth NMOS tube is connected to the second terminal, and the source of the fifteenth NMOS tube is connected to the drain of the sixteenth NMOS tube; the gate of the sixteenth NMOS tube is connected to the clock signal terminal, and the source of the sixteenth NMOS tube is grounded; the source of the eleventh PMOS tube is connected to the power supply terminal, and the drain of the eleventh PMOS tube is connected to the first output terminal of the latch; the gate of the nineteenth NMOS tube is connected to the gate of the eleventh PMOS tube, the drain of the nineteenth NMOS tube is connected to the first output terminal of the latch, and the source of the nineteenth NMOS tube is grounded.

6. The latch according to claim 5, wherein: The output module further includes: a ninth PMOS tube, a tenth PMOS tube, a twelfth PMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube and a twentieth NMOS tube; The source of the ninth PMOS tube is connected to the power supply terminal, the gate of the ninth PMOS tube is connected to the clock inverse signal terminal, and the drain of the ninth PMOS tube is connected to the source of the tenth PMOS tube; the drain of the tenth PMOS tube is connected to the gate of the twelfth PMOS tube, and the gate of the tenth PMOS tube is connected to the fourth terminal; the drain of the seventeenth NMOS tube is connected to the drain of the tenth PMOS tube, the gate of the seventeenth NMOS tube is connected to the fourth terminal, and the source of the seventeenth NMOS tube is connected to the drain of the eighteenth NMOS tube; the gate of the eighteenth NMOS tube is connected to the clock signal terminal, and the source of the eighteenth NMOS tube is grounded; the source of the twelfth PMOS tube is connected to the power supply terminal, and the drain of the twelfth PMOS tube is connected to the second output terminal of the latch; the gate of the twentieth NMOS tube is connected to the gate of the twelfth PMOS tube, the drain of the twentieth NMOS tube is connected to the second output terminal of the latch, and the source of the twentieth NMOS tube is grounded.

7. The latch according to claim 1, wherein: The clock control module includes: a thirteenth PMOS tube, a fourteenth PMOS tube, a twenty-first NMOS tube and a twenty-second NMOS tube; The source of the thirteenth PMOS tube is connected to the power supply terminal, the gate of the thirteenth PMOS tube is connected to the clock signal input terminal, and the drain of the thirteenth PMOS tube is connected to the clock anti-signal terminal; the gate of the twenty-first NMOS tube is connected to the clock signal input terminal, the drain of the twenty-first NMOS tube is connected to the drain of the thirteenth PMOS tube, and the source of the twenty-first NMOS tube is grounded; the source of the fourteenth PMOS tube is connected to the power supply terminal, the gate of the fourteenth PMOS tube is connected to the drain of the thirteenth PMOS tube, and the drain of the fourteenth PMOS tube is connected to the clock signal terminal; the gate of the twenty-second NMOS tube is connected to the gate of the fourteenth PMOS tube, the drain of the twenty-second NMOS tube is connected to the clock signal terminal, and the source of the twenty-second NMOS tube is grounded.

8. The latch according to claim 1, wherein: When the clock signal is 0, the circuit of the latch is in a write state, and the input data of the input module is 0, the sixth NMOS tube, the third NMOS tube and the eighth NMOS tube in the storage module are turned on; when the clock signal is 0, the circuit of the latch is in a write state, and the input data of the input module is 1, the second NMOS tube, the seventh NMOS tube and the fourth NMOS tube in the storage module are turned on.

9. The latch according to claim 1, wherein: When the clock signal is 1, the circuit is in a latched state, and the input data of the input module is 0, the information stored in the first terminal is 1, the information stored in the second terminal is 1 including a threshold loss, the information stored in the third terminal is 0, and the information stored in the fourth terminal is 0; the information stored in the second terminal is output through the first output terminal of the latch, and the information stored in the fourth terminal is output through the second output terminal of the latch; When the clock signal is 1, the circuit is in the latched state, and the input data of the input module is 1; The information stored in the first terminal is 0, the information stored in the second terminal is 0, the information stored in the third terminal is 1, and the information stored in the fourth terminal is 1 including threshold loss; the information stored in the second terminal is output through the first output terminal of the latch, and the information stored in the fourth terminal is output through the second output terminal of the latch.

10. The latch according to claim 9, wherein: When the clock signal is 1, the circuit is in the latched state, and the input data of the input module is 0; If the written data is 0, the information stored in the first terminal X1 is 1, the information stored in the second terminal X2 is 1 (VDD-Vth), the information stored in the third terminal X3 is 0, and the information stored in the fourth terminal X4 is 0; When the first terminal is hit by particles, a voltage jump from 1 to 0 occurs, and the third NMOS tube and the sixth NMOS tube are switched from the on state to the off state, and the second terminal and the third terminal are switched from the low resistance state to the high resistance state potential, and remain unchanged, and the potential of the fourth terminal remains unchanged, and the first NMOS tube is switched from the off state to the on state, and the potential of the first terminal is restored to 1; When the second terminal is hit by particles, a voltage jump from 1 to 0 occurs, the eighth NMOS tube changes from an on state to a off state, the fourth terminal changes from a low resistance state to a high resistance state, and the potential remains unchanged. The first NMOS tube remains in a closed state, the first terminal remains in a high resistance state, and the potential remains unchanged. The potential of the third terminal remains unchanged, and the third NMOS tube remains in an on state, restoring the potential of the second terminal to 1.

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