High-low level conversion circuit with wide threshold value

Abstract

A high-low level conversion circuit with a wide threshold value relates to the technical field of integrated circuits, and is mainly structurally characterized in that the drain end of a twelfth PMOS (P-channel Metal Oxide Semiconductor) tube is connected with the drain end of a ninth NMOS (N-channel Metal Oxide Semiconductor) tube through a first resistor and a second resistor which are connected in series; the connection point of the first resistor and the second resistor serves as a first reference point A to be connected with input voltage VIN. The source end of the ninth NMOS tube is connected with the source end of the fourth PMOS tube; the drain end of the fourth PMOS tube is connected with the drain end of the fifth NMOS tube to serve as a fourth reference point D; the drain end of the fifth NMOS tube is sequentially connected with the first phase inverter and the second phase inverter; when the potential of the point A is reduced to be near VE + VTH4 under the driving of a VIN end, the fourth PMOS tube enters a saturation region, a small fluctuation of the level of the point A causes a huge change of the level of the point D, and the level of the point D enters a level overturning threshold value of a post-stage inverter more quickly. According to the invention, the conversion of high and low voltage control signals is realized, the flip voltage is accurately controlled, the high and low level threshold values are increased, and the punch-through current during level flip is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a high-low level conversion circuit with a wide threshold value. Background Art

[0002] In standard TTL (transistor-transistor logic) digital circuits, the threshold value of logic high level is about 2.0V to 5V, and the threshold value of logic low level is about 0V to 0.8V. In CMOS (complementary metal oxide semiconductor) digital circuits, the threshold value of logic level usually depends on the power supply voltage. The threshold value of logic high level is about the power supply voltage minus 0.8V to the power supply voltage, and the threshold value of logic low level is about 0V to 0.8V. In high-voltage chips, the control signal input to the port can reach up to tens of volts or hundreds of volts, while the voltage that the internal digital circuit can withstand is only a few volts or even a few volts. At this time, it is necessary to convert the high-voltage control signal into a low-voltage control signal that the internal digital circuit can withstand.

[0003] At present, there are some existing technologies related to high-low level conversion, such as "A level conversion circuit for high voltage to low voltage" with application number CN202310275240.1, which uses multiple MOS tubes for cross-coupling structure, mainly to solve the problem that the traditional level conversion circuit cannot achieve reliable level conversion due to the large transmission delay. For another example, "A level conversion circuit" with application number CN202010260150.1 adjusts the pull-down ability of the level conversion circuit by controlling the conduction or disconnection of the first adjustment circuit and the second adjustment circuit, solving the technical problem that the output end of the level conversion circuit in the related technology cannot successfully achieve the high and low level flip when the voltage at the power supply end is small or large and the input signal flips quickly.

[0004] However, how to accurately control the flipping voltage, increase the high and low level threshold values, and reduce the through-current during level flipping during the conversion of high and low voltage control signals, and how to ensure compatibility with the previous-stage logic control signal when the process drifts or at different temperatures and different application power supplies are still issues that cannot be ignored in high-voltage chip design. Summary of the invention

[0005] The purpose of the present invention is to provide a circuit for high-low level conversion of control signals in high-voltage circuits, which can realize the conversion of high- and low-voltage control signals through fewer devices, accurately control the flipping voltage, increase the high and low level threshold values, reduce the through current during level flipping, and ensure compatibility with the previous stage logic control signal when process drift occurs or at different temperatures and different application power supplies.

[0006] In order to achieve the above purpose, the technical solution adopted by the present invention is: a high-low level conversion circuit with a wide threshold value, whose structure is:

[0007] The gate terminal of the first PMOS tube is connected to the gate terminal of the second PMOS tube and the gate terminal of the third PMOS tube, the source terminal is connected to the high voltage power supply voltage, and the drain terminal is connected to the source terminal of the tenth PMOS tube; the gate terminal of the first PMOS tube is also connected to its drain terminal;

[0008] The source terminal of the second PMOS tube is connected to the high voltage power supply voltage, and the drain terminal is connected to the source terminal of the eleventh PMOS tube;

[0009] The source terminal of the third PMOS tube is connected to the high voltage power supply voltage, and the drain terminal is connected to the source terminal of the twelfth PMOS tube;

[0010] The gate terminal of the tenth PMOS tube is connected to the gate terminal of the eleventh PMOS tube, and the gate terminal and drain terminal of the twelfth PMOS tube are connected to the ground level through a current source; the gate terminal of the tenth PMOS tube is also connected to its drain terminal;

[0011] The drain terminal of the eleventh PMOS tube is connected to the drain terminal of the eighth NMOS tube;

[0012] The drain end of the twelfth PMOS tube is connected to the drain end of the ninth NMOS tube through the first resistor and the second resistor connected in series; the connection point of the first resistor and the second resistor is connected to the input voltage;

[0013] The gate terminal of the eighth NMOS tube is connected to the drain terminal thereof and the gate terminal of the ninth NMOS tube, and the source terminal is connected to the drain terminal of the seventh NMOS tube;

[0014] The source terminal of the ninth NMOS tube is connected to the source terminal of the fourth PMOS tube;

[0015] The gate terminal of the seventh NMOS tube is connected to the drain terminal thereof, and the source terminal is connected to the drain terminal of the sixth NMOS tube;

[0016] The gate terminal of the sixth NMOS tube is connected to the gate terminal of the fourth PMOS tube and the gate terminal and source terminal of the fifth NMOS tube are grounded; the gate terminal of the sixth NMOS tube is also connected to the drain terminal thereof;

[0017] The drain terminal of the fourth PMOS tube is connected to the drain terminal of the fifth NMOS tube;

[0018] The source terminal of the fifth NMOS tube is connected to the ground level, and the drain terminal is connected to the input terminal of the first inverter;

[0019] The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the output pin;

[0020] The power supply voltage of the first inverter and the second inverter is a low voltage power supply voltage, and the ground voltage is a ground level;

[0021] The ninth NMOS tube, the tenth PMOS tube, the eleventh PMOS tube, and the twelfth PMOS tube are high-voltage tubes.

[0022] As a preference, the ninth NMOS tube is a high-voltage NMOS tube with a drain end capable of withstanding high voltage, and the tenth PMOS tube, the eleventh PMOS tube, and the twelfth PMOS tube are high-voltage PMOS tubes with a drain end capable of withstanding high voltage.

[0023] As another preferred embodiment, the ninth NMOS tube is an NLDMOS tube, and the tenth PMOS tube, the eleventh PMOS tube, and the twelfth PMOS tube are PLDMOS tubes.

[0024] Preferably, the width-to-length ratio of the first PMOS tube, the second PMOS tube, and the third PMOS tube is

[0025]

[0026] The width-to-length ratio of the tenth PMOS tube, the eleventh PMOS tube, and the twelfth PMOS tube is

[0027]

[0028] The width-to-length ratio of the sixth NMOS tube and the fifth NMOS tube is and m>n;

[0029] The width-to-length ratio of the fourth PMOS tube is greater than the width-to-length ratio of the seventh NMOS tube, and the width-to-length ratio of the ninth NMOS tube is greater than the width-to-length ratio of the eighth NMOS tube.

[0030] The beneficial effects of the present invention are:

[0031] The present invention realizes the conversion of high and low voltage control signals through fewer devices, can accurately control the flip voltage, increase the high and low level threshold values, reduce the through current during level flipping, and can ensure compatibility with the previous stage logic control signal when process drift occurs or at different temperatures and different application power supplies. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the circuit structure of an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] Figure 1 A specific embodiment of the present invention is a high-low level conversion circuit with a wide threshold value, and its structure is as follows:

[0035] The gate terminal of the first PMOS tube M1 is connected to the gate terminal of the second PMOS tube M2 and the gate terminal of the third PMOS tube M3, the source terminal is connected to the high voltage power supply voltage PVDD, and the drain terminal is connected to the source terminal of the tenth PMOS tube M10; the gate terminal of the first PMOS tube M1 is also connected to its drain terminal;

[0036] The source terminal of the second PMOS tube M2 is connected to the high voltage power supply voltage PVDD, and the drain terminal is connected to the source terminal of the eleventh PMOS tube M11;

[0037] The source terminal of the third PMOS tube M3 is connected to the high voltage power supply voltage PVDD, and the drain terminal is connected to the source terminal of the twelfth PMOS tube M12;

[0038] The gate terminal of the tenth PMOS tube M10 is connected to the gate terminal of the eleventh PMOS tube M11 and the gate terminal and drain terminal of the twelfth PMOS tube M12 are connected to the ground level VSS through the current source I0; the gate terminal of the tenth PMOS tube M10 is also connected to its drain terminal;

[0039] The drain terminal of the eleventh PMOS tube M11 is connected to the drain terminal of the eighth NMOS tube M8;

[0040] The drain end of the twelfth PMOS transistor M12 is connected to the drain end of the ninth NMOS transistor M9 through the first resistor R1 and the second resistor R2 connected in series; the connection point of the first resistor R1 and the second resistor R2 is used as a first reference point A to connect the input voltage VIN;

[0041] The gate terminal of the eighth NMOS transistor M8 is connected to the drain terminal thereof and the gate terminal of the ninth NMOS transistor M9 as the second reference point B, and the source terminal is connected to the drain terminal of the seventh NMOS transistor M7;

[0042] The source terminal of the ninth NMOS transistor M9 is connected to the source terminal of the fourth PMOS transistor M4 as a third reference point C;

[0043] The gate terminal of the seventh NMOS transistor M7 is connected to its drain terminal, and the source terminal is connected to the drain terminal of the sixth NMOS transistor M6;

[0044] The gate terminal of the sixth NMOS tube M6 is connected to the gate terminal of the fourth PMOS tube M4 and the gate terminal of the fifth NMOS tube M5 as the fifth reference point E and the source ground level VSS; the gate terminal of the sixth NMOS tube M6 is also connected to its drain terminal;

[0045] The drain terminal of the fourth PMOS tube M4 is connected to the drain terminal of the fifth NMOS tube M5 as a fourth reference point D;

[0046] The source terminal of the fifth NMOS tube M5 is connected to the ground level VSS, and the drain terminal is connected to the input terminal of the first inverter I1;

[0047] The output terminal of the first inverter I1 is connected to the input terminal of the second inverter I2, and the output terminal of the second inverter I2 is connected to the output pin VOUT;

[0048] The power supply voltage of the first inverter I1 and the second inverter I2 is a low voltage power supply voltage VDD, and the ground voltage is a ground level VSS;

[0049] The ninth NMOS tube M9 , the tenth PMOS tube M10 , the eleventh PMOS tube M11 , and the twelfth PMOS tube M12 are high-voltage tubes.

[0050] In this embodiment, the ninth NMOS tube M9 is a high-voltage NMOS tube with a drain end capable of withstanding high voltage, and the tenth PMOS tube M10 , the eleventh PMOS tube M11 , and the twelfth PMOS tube M12 are high-voltage PMOS tubes with a drain end capable of withstanding high voltage.

[0051] Of course, in other embodiments, the ninth NMOS tube M9 may also be an NLDMOS tube, and the tenth PMOS tube M10 , the eleventh PMOS tube M11 , and the twelfth PMOS tube M12 may be PLDMOS tubes.

[0052] In this embodiment, the width-to-length ratio of the first PMOS tube M1, the second PMOS tube M2, and the third PMOS tube M3 is:

[0053] The width-to-length ratios of the tenth PMOS tube M10, the eleventh PMOS tube M11, and the twelfth PMOS tube M12 are:

[0054] The width-to-length ratio of the sixth NMOS transistor M6 and the fifth NMOS transistor M5 is: and m>n;

[0055] The width-to-length ratio of the fourth PMOS tube M4 is greater than that of the seventh NMOS tube M7 , and the width-to-length ratio of the ninth NMOS tube M9 is greater than that of the eighth NMOS tube M8 .

[0056] In this case, when there is no input signal at the VIN terminal, because the third PMOS tube M3 does not have enough current flowing through, the potential at point A is pulled to the vicinity of PVDD, and the ninth NMOS tube M9 works in the subthreshold region. The potential at point C is the potential at point B minus the threshold voltage of the M9 tube, that is, V C =V B -V TH9 The fourth PMOS tube M4 works in the linear region, and the potential at point D is approximately equal to the potential at point C, that is, V D =V C =V B -V TH9 .

[0057] When the VIN input level gradually decreases from the PVDD potential, the potential at point A decreases accordingly. When the potential at point A approaches the potential at point C, the M9 tube enters the linear region, and the potentials at points C and D approach the potential at point A, and decrease as the potential at point A decreases. When the potentials at points A, C, and D decrease synchronously until the M4 tube enters the saturation region, the potential at point D will no longer change with the potentials at points A and C. A small change in the potential at point A will cause a huge change in the potential at point D. The potential at point A continues to change downward, the M4 tube is turned off, and the potential at point D becomes 0.

[0058] When the potential at point A rises from 0 to the PVDD potential, the potential change at point D is the reverse change of the above process.

[0059] In the above process, when the potential at point D rises / falls beyond the flip voltage of the subsequent inverter (approximately VDD / 2), the output logic of the inverter flips. The level conversion threshold voltage of the high-low level conversion circuit in this embodiment is approximately the potential at point E plus the threshold voltage of the M4 tube, that is, V E +V TH4 , the logic high threshold is about V E +V TH4 +δV / 2 to PVDD, logic low threshold is approximately 0V to V E +V TH4 -δV / 2, where δV is related to the gain G4 when the M4 tube is in the saturation region, which is approximately VDD / G4.

[0060] From the working process of the above embodiment, the currents generated by the mirror images of the first PMOS tube M1, the second PMOS tube M2, and the third PMOS tube M3 are asymmetric with the currents generated by the mirror images of the sixth NMOS tube M6 and the fifth NMOS tube M5, so that when there is no external current driving the VIN terminal, the potential at point A is pulled up to near the PVDD level, the M9 tube works in the subthreshold region, the M4 tube works in the linear region, and the potential at point D is approximately equal to the potential at point C. When the potential at point A drops to V E +V TH4 When the voltage is close to 0, the M4 tube enters the saturation zone, the gain of the M4 tube increases, and the level change at point C will be amplified by the M4 tube, that is, a small fluctuation of the level at point C or point A will cause a huge change in the level at point D, and the level at point D enters the level flip threshold value of the subsequent inverter more quickly, avoiding the large voltage difference between the control signal level and the power rail, which causes the inverter P tube and N tube to be turned on at the same time and flow a large through current. Therefore, the level conversion threshold voltage of the high-low level conversion circuit of the present invention is controlled at V E +V TH4 In a very small area nearby.

[0061] Therefore, the present invention realizes the conversion of high and low voltage control signals through fewer devices, accurately controls the flipping voltage, increases the high and low level threshold values, reduces the through current during level flipping, and can ensure compatibility with the previous stage logic control signal when process drift occurs or at different temperatures and different application power supplies.

Claims

1. A high-low level conversion circuit with a wide threshold, characterized in that: The gate end of the first PMOS tube (M1) is connected to the gate end of the second PMOS tube (M2) and the gate end of the third PMOS tube (M3), the source end is connected to the high voltage power supply voltage (PVDD), and the drain end is connected to the source end of the tenth PMOS tube (M10); the gate end of the first PMOS tube (M1) is also connected to its drain end; The source terminal of the second PMOS tube (M2) is connected to the high voltage power supply voltage (PVDD), and the drain terminal is connected to the source terminal of the eleventh PMOS tube (M11); The source terminal of the third PMOS tube (M3) is connected to the high voltage power supply voltage (PVDD), and the drain terminal is connected to the source terminal of the twelfth PMOS tube (M12); The gate terminal of the tenth PMOS tube (M10) is connected to the gate terminal of the eleventh PMOS tube (M11) and the gate terminal of the twelfth PMOS tube (M12), and the drain terminal is connected to the ground level (VSS) through the current source (I0); the gate terminal of the tenth PMOS tube (M10) is also connected to its drain terminal; The drain terminal of the eleventh PMOS tube (M11) is connected to the drain terminal of the eighth NMOS tube (M8); The drain end of the twelfth PMOS tube (M12) is connected to the drain end of the ninth NMOS tube (M9) through a first resistor (R1) and a second resistor (R2) connected in series; the connection point of the first resistor (R1) and the second resistor (R2) is connected to an input voltage (VIN); The gate end of the eighth NMOS tube (M8) is connected to its drain end and the gate end of the ninth NMOS tube (M9), and the source end is connected to the drain end of the seventh NMOS tube (M7); The source terminal of the ninth NMOS tube (M9) is connected to the source terminal of the fourth PMOS tube (M4); The gate terminal of the seventh NMOS transistor (M7) is connected to the drain terminal thereof, and the source terminal is connected to the drain terminal of the sixth NMOS transistor (M6); The gate terminal of the sixth NMOS tube (M6) is connected to the gate terminal of the fourth PMOS tube (M4) and the gate terminal and source terminal of the fifth NMOS tube (M5) and the ground level (VSS); the gate terminal of the sixth NMOS tube (M6) is also connected to its drain terminal; The drain terminal of the fourth PMOS tube (M4) is connected to the drain terminal of the fifth NMOS tube (M5); The source end of the fifth NMOS tube (M5) is connected to the ground level (VSS), and the drain end is connected to the input end of the first inverter (I1); The output end of the first inverter (I1) is connected to the input end of the second inverter (I2), and the output end of the second inverter (I2) is connected to the output pin (VOUT); The power supply voltage of the first inverter (I1) and the second inverter (I2) is a low voltage power supply voltage (VDD), and the ground voltage is a ground level (VSS); The ninth NMOS tube (M9), the tenth PMOS tube (M10), the eleventh PMOS tube (M11), and the twelfth PMOS tube (M12) are high-voltage tubes.

2. A high-low level conversion circuit with a wide threshold value according to claim 1, characterized in that: The ninth NMOS tube (M9) is a high-voltage NMOS tube with a drain end that can withstand high voltage, and the tenth PMOS tube (M10), the eleventh PMOS tube (M11), and the twelfth PMOS tube (M12) are high-voltage PMOS tubes with a drain end that can withstand high voltage.

3. A high-low level conversion circuit with a wide threshold value according to claim 1, characterized in that: The ninth NMOS tube (M9) is an NLDMOS tube, and the tenth PMOS tube (M10), the eleventh PMOS tube (M11), and the twelfth PMOS tube (M12) are PLDMOS tubes.

4. A high-low level conversion circuit with a wide threshold value according to claim 1, characterized in that: The width-to-length ratio of the first PMOS tube (M1), the second PMOS tube (M2), and the third PMOS tube (M3) is The width-to-length ratio of the tenth PMOS tube (M10), the eleventh PMOS tube (M11), and the twelfth PMOS tube (M12) is The width-to-length ratio of the sixth NMOS transistor (M6) and the fifth NMOS transistor (M5) is and m>n; The width-to-length ratio of the fourth PMOS tube (M4) is greater than the width-to-length ratio of the seventh NMOS tube (M7), and the width-to-length ratio of the ninth NMOS tube (M9) is greater than the width-to-length ratio of the eighth NMOS tube (M8).

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