Semiconductor device and preparation method thereof, and storage system

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method and a memory system. The semiconductor device includes a semiconductor pillar, an isolation structure, and a gate structure. The semiconductor column extends along a first direction and comprises at least one side surface; the isolation structure extends along a second direction, the isolation structure is opposite to a part of the side surface of the semiconductor column in a third direction, and the first direction, the second direction and the third direction intersect with one another; the gate structures surround other side surfaces of the semiconductor column, wherein the plurality of gate structures adjacent to the same isolation structure are symmetrically distributed on two opposite sides of the same isolation structure in the third direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and preparation, and more specifically, to a semiconductor device, a method for preparing a semiconductor device, and a storage system. Background Art

[0002] The semiconductor device may include a memory cell composed of a capacitor and a transistor, wherein a plurality of memory cells may be arranged in a two-dimensional array. In order to further reduce the size of the two-dimensional array, the transistor may include a vertical gate transistor (VGT). In this structure, the transistor may include a semiconductor column, a source and a drain located at both ends of the semiconductor column in the extension direction, and a gate structure located on the sidewall of the semiconductor column.

[0003] The gate control capability of a transistor refers to the ability of the transistor to form a channel of the transistor between the source and the drain along the extension direction of the semiconductor column by relying on the gate voltage applied to the gate structure. The above channel can be formed when the gate voltage is higher than the threshold voltage of the vertical transistor.

[0004] How to further reduce the size of semiconductor devices while enhancing the gate control capability of the gate structure and improving the switching speed of the gate structure and the reliability of semiconductor devices is one of the important research directions in the industry. Summary of the invention

[0005] The present application provides a method for preparing a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0006] On the one hand, the present application provides a semiconductor device, which includes: a semiconductor column extending along a first direction and including at least one side; an isolation structure extending along a second direction, wherein the isolation structure is opposite to a portion of the side of the semiconductor column in a third direction, and the first direction, the second direction and the third direction intersect with each other; a gate structure surrounding the remaining side of the semiconductor column, wherein a plurality of gate structures adjacent to the same isolation structure are symmetrically distributed on opposite sides of the same isolation structure in the third direction.

[0007] In one embodiment of the present application, the plurality of gate structures adjacent to the same isolation structure are distributed on both sides of the same isolation structure in a mirror-symmetrical manner.

[0008] In one embodiment of the present application, the isolation structure includes an isolation dielectric layer and an air gap surrounded by the isolation dielectric layer.

[0009] In one embodiment of the present application, the isolation structure includes an isolation dielectric layer and a conductive layer surrounded by the isolation dielectric layer.

[0010] In one embodiment of the present application, the gate structure includes a gate dielectric layer and a gate conductor layer, wherein the gate dielectric layer is located between a side surface of the semiconductor pillar and the gate conductor layer.

[0011] In one embodiment of the present application, the gate conductor layer and the conductive layer include conductive material layers of the same material.

[0012] In one embodiment of the present application, the gate structure includes a plurality of first portions and a plurality of second portions, wherein at least one of the plurality of first portions surrounds the side surface of the semiconductor column, and at least one of the plurality of second portions extends along the second direction and connects the first portions adjacent to the second direction.

[0013] In one embodiment of the present application, at least one of the multiple first parts includes multiple sub-parts connected to each other, wherein the number of the sub-parts is the same as the number of the remaining side surfaces of the semiconductor column; and the sub-part is located on one of the remaining side surfaces of the semiconductor column.

[0014] In one embodiment of the present application, in a plane perpendicular to the first direction, a projection of the semiconductor column is located within a projection of the first portion.

[0015] In one embodiment of the present application, a cross-sectional shape of the semiconductor pillar in a plane perpendicular to the first direction includes at least one of a rectangular shape, a trapezoidal shape, a circular shape, and an elliptical shape.

[0016] In one embodiment of the present application, the semiconductor column is hexahedral and includes four side surfaces, wherein the isolation structure is opposite to one side surface of the semiconductor column in the third direction; and the gate structure surrounds the remaining three side surfaces of the semiconductor column.

[0017] On the other hand, the present application provides a method for preparing a semiconductor device, the method comprising: forming a semiconductor column, wherein the semiconductor column extends along a first direction and includes at least one side; forming an isolation sacrificial layer, wherein the isolation sacrificial layer extends along a second direction and is opposite to a portion of the side of the semiconductor column in a third direction, and the first direction, the second direction and the third direction intersect with each other; forming a gate structure surrounding the remaining side of the semiconductor column, wherein a second portion of the gate structure contacts the isolation sacrificial layer, and the second portion is a portion of the gate structure located between semiconductor columns adjacent to each other in the second direction; and removing the isolation sacrificial layer, and forming an isolation structure in the first gap formed after removing the isolation sacrificial layer.

[0018] In one embodiment of the present application, forming the semiconductor pillar includes: forming a base structure, wherein the base structure includes semiconductor layers and spacer layers alternately distributed along the second direction; forming first grooves and second grooves extending along the second direction respectively in the base structure, wherein a plurality of the first grooves and a plurality of the second grooves are alternately distributed along the third direction to divide the semiconductor layer into a plurality of the semiconductor pillars.

[0019] In one embodiment of the present application, forming an isolation sacrificial layer includes: forming an initial first isolation dielectric layer, wherein the initial first isolation dielectric layer is at least located on the sidewalls and bottom of the second trench; and filling the remaining space of the second trench with the isolation sacrificial layer.

[0020] In one embodiment of the present application, forming a gate structure surrounding the remaining sides of the semiconductor column includes: removing the spacer layer and a portion of the initial first isolation dielectric layer to form a second gap and exposing a portion of the isolation sacrificial layer, wherein the removed portion of the initial first isolation dielectric layer is located between semiconductor columns adjacent to each other in the second direction; and forming the gate structure on the side of the semiconductor column exposed in the second gap and the exposed portion of the isolation sacrificial layer.

[0021] In one embodiment of the present application, removing the isolation sacrificial layer and forming an isolation structure in the first gap formed after removing the isolation sacrificial layer includes: removing the isolation sacrificial layer to form the first gap; forming a first portion of an isolation dielectric layer in the first gap, wherein the first portion at least covers the initial first isolation dielectric layer; forming a conductive layer in the remaining space of the first gap; and covering the second portion of the isolation dielectric layer on the surface of the conductive layer to form the isolation structure, wherein the isolation structure includes the first portion, the second portion and the conductive layer.

[0022] In one embodiment of the present application, removing the isolation sacrificial layer and forming an isolation structure in the first gap formed after removing the isolation sacrificial layer includes: removing the isolation sacrificial layer to form the first gap; and using a deposition process to form an isolation dielectric layer in the first gap that at least covers the initial first isolation dielectric layer, wherein the isolation dielectric layer includes a first part and a second part; forming the first part and the second part by using two deposition rates of different sizes to form an air gap in the first gap; and the isolation structure includes the first part, the second part and the air gap.

[0023] Another aspect of the present application provides a storage system, which includes the semiconductor device provided in one aspect of the present application and a controller coupled to the semiconductor device, wherein the controller is used to store data in the semiconductor device.

[0024] According to the semiconductor device, preparation method and memory system provided by at least one embodiment of the present application, the semiconductor device may include a semiconductor column, an isolation structure and a gate structure, wherein the semiconductor column includes at least one side, the isolation structure is opposite to part of the side of the semiconductor column in a direction intersecting the extension direction of the semiconductor column and its own extension direction, and the gate structure surrounds the remaining side of the semiconductor column. In addition, multiple gate structures adjacent to the same isolation structure can be symmetrically distributed on two opposite sides of the same isolation structure. Thus, the gate control capability of the gate structure can be improved by increasing the contact area between the gate structure and the semiconductor column. On this basis, the isolation structure can reduce the interference between adjacent gate structures in the semiconductor device, improve the switching speed of the gate structure and the reliability of the semiconductor device; symmetrically distributing multiple gate structures adjacent to the same isolation structure on two opposite sides of the same isolation structure can effectively reduce the size of the semiconductor device and improve the impact of structural differences on the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0026] Figure 1A is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present application;

[0027] Figure 1B is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present application;

[0028] Figure 1C yes Figure 1A An enlarged schematic diagram of a semiconductor device at position M is shown;

[0029] Figure 1D yes Figure 1B An enlarged schematic diagram of a semiconductor device at position N is shown;

[0030] Figure 2 yes Figure 1C A schematic top view of the semiconductor device shown is taken along line AA';

[0031] Figure 3 yes Figure 1C A schematic top view of the semiconductor device shown is taken along line BB';

[0032] Figure 4 is a flow chart of a method for preparing a semiconductor device according to an exemplary embodiment of the present application;

[0033] Figure 5 is a schematic cross-sectional view of a structure formed after a semiconductor layer is formed according to a preparation method in one embodiment of the present application;

[0034] Figure 6 yes Figure 5 A schematic top view of the intermediate body shown along line AA' or line BB';

[0035] Figure 7 is a schematic cross-sectional view of a structure formed after a semiconductor column is formed according to a preparation method in one embodiment of the present application;

[0036] Figure 8 yes Figure 7 A schematic top view of the intermediate body shown along line AA' or line BB';

[0037] Fig. 9 is a schematic cross-sectional view of a structure formed after forming an initial first isolation dielectric layer according to a preparation method in one embodiment of the present application;

[0038] Fig.10 yes Fig. 9 A schematic top view of the intermediate body shown along line AA' or line BB';

[0039] Fig.11 is a schematic cross-sectional view of a structure formed after forming an isolation sacrificial layer according to a preparation method in one embodiment of the present application;

[0040] Fig.12 yes Fig.11 A schematic top view of the intermediate body shown along line AA' or line BB';

[0041] Fig.13 is a cross-sectional schematic diagram of a structure formed after removing a portion of an initial first isolation dielectric layer according to a preparation method in one embodiment of the present application;

[0042] Fig.14 yes Fig.13 The intermediate body is shown as a top view taken along line AA' or line BB'

[0043] Fig.15 is a schematic cross-sectional view of a structure formed after a gate structure is formed according to a preparation method in one embodiment of the present application;

[0044] Fig.16 yes Fig.15 A schematic top view of the intermediate body shown along line AA';

[0045] Fig.17 yes Fig.15 A schematic top view of the intermediate body shown along line BB';

[0046] Fig.18 is a cross-sectional schematic diagram of a structure formed after forming a first gap according to a preparation method in one embodiment of the present application;

[0047] Fig.19 yes Fig.18 A schematic top view of the intermediate body shown along line AA';

[0048] Fig. 20 yes Fig.18 A schematic top view of the intermediate body shown along line BB'; and

[0049] Fig.21 It is a schematic diagram of the storage system structure according to one embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature area, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first side discussed in this application may also be referred to as the second side, and vice versa.

[0052] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0053] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0054] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0055] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0056] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0057] The present application will be described in detail below with reference to the accompanying drawings and in combination with implementation modes.

[0058] Some embodiments of the present application provide a semiconductor device. Figure 1A is a cross-sectional view of a semiconductor device 1000 according to an exemplary embodiment of the present application. Figure 1B is a cross-sectional view of a semiconductor device 1000 according to an exemplary embodiment of the present application. Figure 1C yes Figure 1AFIG. 1 is an enlarged schematic diagram of the semiconductor device 1000 at point M. FIG. Figure 1D yes Figure 1B FIG. 1 is an enlarged schematic diagram of the semiconductor device 1000 at position N. FIG. Figure 2 yes Figure 1C The semiconductor device 1000 is shown in a schematic top view taken along line AA′. Figure 3 yes Figure 1C The semiconductor device 1000 is shown in a schematic top view taken along line BB′.

[0059] like Figures 1A to 3 As shown, the semiconductor device 1000 includes a semiconductor column 100, a gate structure 200 and an isolation structure 300. The semiconductor column 100 extends along a first direction (z direction) and includes at least one side 130, for example, the semiconductor column 100 includes a first side 131, a second side 132, a third side 133 and a fourth side 134. The isolation structure 300, for example, the first isolation structure 301, extends along a second direction (x direction), wherein the isolation structure 300 is opposite to a part of the side of the semiconductor column 100 in a third direction (y direction), and the x direction, the y direction and the z direction intersect with each other; the gate structure 200 surrounds the remaining side of the semiconductor column 100. In addition, multiple gate structures adjacent to the same isolation structure are symmetrically distributed on two opposite sides of the same isolation structure in the y direction. For example, multiple gate structures adjacent to the first isolation structure 301, the first gate structure 201, the second gate structure 202, the third gate structure 203, and the fourth gate structure 204, are symmetrically distributed on two opposite sides of the first isolation structure 301 in the y direction.

[0060] According to a semiconductor device provided by at least one embodiment of the present application, the semiconductor device may include a semiconductor column, an isolation structure and a gate structure, wherein the semiconductor column includes at least one side, the isolation structure is opposite to a part of the side of the semiconductor column in a direction intersecting both the extension direction of the semiconductor column and its own extension direction, and the gate structure surrounds the remaining side of the semiconductor column. In addition, multiple gate structures adjacent to the same isolation structure may be symmetrically distributed on two opposite sides of the same isolation structure. Thus, the gate control capability of the gate structure can be improved by increasing the contact area between the gate structure and the semiconductor column. On this basis, the isolation structure can reduce the interference between adjacent gate structures in the semiconductor device, improve the switching speed of the gate structure and the reliability of the semiconductor device; symmetrically distributing multiple gate structures adjacent to the same isolation structure on two opposite sides of the same isolation structure can effectively reduce the size of the semiconductor device and improve the impact of structural differences on the performance of the semiconductor device.

[0061] Optionally, in order to enhance the above effect, multiple gate structures adjacent to the same isolation structure are distributed in mirror symmetry on two opposite sides of the same isolation structure in the y direction. For example, multiple gate structures adjacent to the first isolation structure 301, the first gate structure 201, the second gate structure 202, the third gate structure 203, and the fourth gate structure 204 are distributed in mirror symmetry on two opposite sides of the first isolation structure 301 in the y direction.

[0062] Specifically, Figure 1A and Figure 1B As shown, in some embodiments of the present application, the semiconductor device 1000 may include a plurality of memory cells (e.g., a memory array) and a peripheral circuit structure connected to the plurality of memory cells, wherein the plurality of memory cells may be located in a first semiconductor structure 1001 (which may be understood as a memory array wafer), and the peripheral circuit structure may be located in a second semiconductor structure 1002 (which may be understood as a peripheral circuit wafer). Through processes such as wafer bonding, the peripheral circuit wafer may be bonded to the memory array wafer, and the connection between the peripheral circuit wafer and the memory array wafer may be achieved through, for example, connecting wires. In addition, optionally, the plurality of memory cells and the peripheral circuit structure of the semiconductor device 1000 may also be arranged on the same wafer, which is not limited in the present application.

[0063] Alternatively, the memory cell may include a transistor 1001-1 and a memory cell 1001-2 coupled to the transistor 1001-1, wherein the plurality of memory cells may be formed into a memory cell array. Taking DRAM (Dynamic Random Access Memory) as an example, the semiconductor device 1000 may include a memory cell composed of a capacitor (memory cell 1001-2) and a transistor 1001-1, and the plurality of memory cells may be arranged in the form of a two-dimensional array. In other words, in some embodiments, the memory cell 1001-2 may include a capacitor for storing charge as binary information stored by a corresponding DRAM cell.

[0064] Furthermore, in some embodiments, the memory cell 1001-2 may include a Phase Change Memory (PCM) element (eg, including a chalcogenide alloy) for storing binary information of a corresponding PCM cell based on different resistivities of the PCM element in an amorphous phase and a crystalline phase.

[0065] Additionally, in some embodiments, the memory cell 1001 - 2 may include a ferroelectric capacitor for storing binary information of a corresponding FRAM (Ferroelectric Random Access Memory) cell based on switching between two polarization states of a ferroelectric material under an external electric field.

[0066] As an option, the transistor 1001-1 is closer to the second semiconductor structure 1002 along the z direction relative to the storage unit 1001-2, so as to shorten the length of the connecting line between the transistor and the peripheral circuit structure in the second semiconductor structure 1002; as another option, the storage unit 1001-2 is closer to the second semiconductor structure 1002 along the z direction relative to the transistor 1001-1, which is not limited in the present application.

[0067] In addition, in order to further reduce the size of the two-dimensional array, the transistor 1001-1 may include a vertical gate transistor. In this structure, the extension direction of the channel of the transistor 1001-1 is perpendicular to the substrate surface, and the source 110 and the drain 120 of the transistor 1001-1 can be formed at both ends of the channel extension direction, and the gate structure 200 of the transistor 1001-1 can be formed on at least one side of the channel.

[0068] In one embodiment of the present application, vertical transistors such as vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) can replace conventional planar transistors as transfer transistors of memory cells to reduce the area occupied by the transfer transistors, coupling capacitance, and interconnection wiring complexity.

[0069] refer to Figure 1C-Figure 3 ,in Figure 1C For the general Figure 1A The enlarged schematic diagram of the structure at M after flipping 180°, Figure 1D For the general Figure 1B FIG. 1 is an enlarged schematic diagram of a structure of FIG. 1 at N after the structure of FIG. 1 is flipped 180°. In some embodiments, unlike a planar transistor in which an active region is formed in a substrate, a vertical transistor may include a semiconductor pillar 100 extending vertically in the z direction above a substrate (not shown). The semiconductor pillar 100 may extend above the top surface of the substrate, exposing not only the top surface of the semiconductor pillar 100 but also one or more side surfaces 130 of the semiconductor pillar 100, such as a first side surface 131 and a second side surface 132.

[0070] Alternatively, the cross-sectional shape of the semiconductor pillar 100 in a plane perpendicular to the z-direction may include at least one of a rectangular shape, a trapezoidal shape, a circular shape, and an elliptical shape. For example, the semiconductor pillar 100 may be a hexahedral shape and include four side surfaces 130, a first side surface 131, a second side surface 132, a third side surface 133, and a fourth side surface 134.

[0071] In other words, the semiconductor column 100 may have a cubic shape to expose its four sides 130. However, it should be understood by those skilled in the art that the semiconductor column 100 may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. In other words, the cross-section of the semiconductor column 100 in a plane perpendicular to the z-direction may have a square shape, a rectangular shape, a trapezoidal shape, a circular shape, an elliptical shape, or any other suitable shape. It should be understood that, consistent with the scope of the present application, for a semiconductor column having a circular or elliptical cross-section in the above plane, the semiconductor column may still be considered to have multiple sides so that the gate structure contacts more than one side of the semiconductor column. As described below with respect to the preparation process, the semiconductor column 100 may be formed from a substrate by, for example, etching or epitaxial processes, and therefore may have the same semiconductor material as the substrate.

[0072] As an option, the material of the substrate may include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable semiconductor material. For example, the substrate may be a silicon substrate. Accordingly, the semiconductor pillar 100 may include at least one of the above materials.

[0073] The vertical transistor may include a gate structure 200 in contact with one or more side surfaces 130 of the semiconductor column 100. For example, in the case where the semiconductor column 100 includes four side surfaces 130, the isolation structure 300 is opposite to the first side surface 131 in the y direction, and the gate structure 200 surrounds the remaining side surfaces of the semiconductor column 100, the second side surface 132, the third side surface 133, and the fourth side surface 134. In other words, in the case where the semiconductor column includes four side surfaces, the isolation structure is opposite to one side surface of the semiconductor column, the gate structure surrounds the remaining side surfaces of the semiconductor column, and the vertical transistor is formed as a three-sided ring gate structure. In some embodiments, the vertical transistor may also include a source 110 and a drain 120 formed at two ends of the semiconductor column 100 in the z direction, respectively, which may be understood as doped regions of the semiconductor column 100, and may also be referred to as source electrodes and drain electrodes. It should be noted that in Figure 1C In the embodiment, the source 110 is disposed below the semiconductor column 100, and the drain 120 is disposed above the semiconductor column 100. However, according to actual needs, the source 110 can be disposed above the semiconductor column 100, and the drain 120 can be disposed below the semiconductor column 100, which is not limited in the present application.

[0074] As an option, the source 110 and the drain 120 may be doped with any suitable P-type dopant, and the P-type dopant may include any one or a combination of boron (B) or gallium (Ga). As another option, the source 110 and the drain 120 may be doped with any suitable N-type dopant, and the N-type dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb). The source 110 and the drain 120 may be separated by the gate structure 200 in the z direction. In other words, the gate structure 200 is formed between the source 110 and the drain 120 along the z direction. Therefore, when the gate voltage applied to the gate structure 200 is higher than the threshold voltage of the vertical transistor, one or more channels of the vertical transistor may be formed in the semiconductor pillar 100 along the z direction between the source 110 and the drain 120 (which can be understood as the gate control capability of the gate structure).

[0075] In some embodiments, the vertical transistor is a multi-gate transistor. In other words, the gate structure 200 may contact more than one side surface of the semiconductor pillar 100 to form more than one gate, so that more than one channel may be formed between the source 110 and the drain 120 during operation. For example, the gate structure 200 may be located on one of the two side walls of the semiconductor pillar 100 opposite to each other in the x-direction, and on this basis, may also be located on the remaining side walls of the semiconductor pillar 100 except the two side walls opposite to each other in the x-direction.

[0076] Unlike a planar transistor including only a single planar gate, due to the 3D structure of the semiconductor pillar 100 and the gate structure 200 surrounding multiple sides of the semiconductor pillar 100, the multi-gate vertical transistor has a larger gate control area compared to the planar transistor to achieve better channel control with a smaller subthreshold swing.

[0077] refer to Figure 1C In one embodiment of the present application, the gate structure 200 includes a gate dielectric layer 230 and a gate conductor layer 12, wherein the gate dielectric layer 230 is located between the side surface 130 of the semiconductor pillar 100 and the gate conductor layer 12. Optionally, the gate conductor layer 12 may further include a gate adhesion layer 210 and a gate metal layer 220.

[0078] For example, the gate structure 200 may include a gate dielectric 230 on one or more sides 130 of the semiconductor pillar 100. In addition, the gate structure 200 may further include a gate adhesion layer 210 on and in contact with the gate dielectric 230, and a gate metal layer 220 on and in contact with the gate adhesion layer 210. In other words, the gate adhesion layer 210 is located between the side 130 of the semiconductor pillar 100 and the gate metal layer 220.

[0079] The gate dielectric 230 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 230 may include silicon oxide. In addition, the gate adhesion layer 210 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the gate metal layer 220 may include any suitable conductive material, such as the gate metal layer 220 may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The gate adhesion layer 210 is used to block the diffusion of metal materials in the gate metal layer 220, and is also used to improve the adhesion between the gate metal layer 220 and the gate dielectric 230.

[0080] In addition, refer to Figure 3 In one embodiment of the present application, the gate structure 200 includes a plurality of first portions 200-1 and a plurality of second portions 200-2, wherein at least one of the plurality of first portions 200-1 surrounds the side surface 130 of the semiconductor pillar 100, and at least one of the plurality of second portions 200-2 extends along the x-direction and connects the first portions 200-1 adjacent to each other in the x-direction. Optionally, at least one of the plurality of second portions 200-2 contacts the isolation structure 300.

[0081] In addition, at least one of the plurality of first portions 200-1 includes a plurality of sub-portions connected to each other, such as a first sub-portion 200-11 and a second sub-portion 200-12, wherein the number of sub-portions is the same as the number of the remaining side surfaces of the semiconductor column 100; and the sub-portion is located on one of the remaining side surfaces of the semiconductor column 100. For example, Figure 3 The semiconductor column 100 shown includes a first side 131, a second side 132, a third side 133 and a fourth side 134. The isolation structure 300 is opposite to the first side 131 in the y direction, and the remaining sides of the semiconductor column 100 are the second side 132, the third side 133 and the fourth side 134. At least one of the plurality of first portions 200-1 includes a plurality of sub-portions connected to each other, such as a first sub-portion 200-11, a second sub-portion 200-12 and a third sub-portion 200-13. The first sub-portion 200-11, the second sub-portion 200-12 and the third sub-portion 200-13 are located on the second side 132, the third side 133 and the fourth side 134, respectively.

[0082] Optionally, in a plane perpendicular to the z direction, the projection of the semiconductor column 100 is located within the projection of the first portion 200-1 of the gate structure 200. In other words, in a plane perpendicular to the z direction, the semiconductor column 100 is enclosed in a region enclosed by the first portion 200-1 of the gate structure 200 and the isolation structure 300; or, in a direction perpendicular to the z direction, such as the x direction or the y direction, the extension dimension of the semiconductor column 100 is smaller than the extension dimension of the first portion 200-1 of the gate structure 200.

[0083] In other words, in at least one embodiment of the present application, the gate structure 200 extends continuously in a plane perpendicular to the z-direction and surrounds the side surfaces 130 of the plurality of semiconductor pillars 100 that are not opposite to the isolation structure 300, thereby increasing the contact area between the gate structure and the semiconductor pillars to improve the gate control capability of the gate structure, and on this basis, improve the switching speed of the gate structure and the reliability of the semiconductor device.

[0084] In addition, reference Figure 1C-Figure 3 The semiconductor 1000 may further include a dielectric filling layer 400, which is at least filled between adjacent gate structures 200, between adjacent isolation structures 300 and gate structures 200, between adjacent isolation structures 300 and semiconductor pillars 100, between adjacent gate structures 200 and semiconductor pillars 100, and between adjacent semiconductor pillars 100.

[0085] Alternatively, the dielectric filling layer 400 may be a composite structure having multiple layers and include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. Alternatively, the gate dielectric 230 and the dielectric filling layer 400 may be made of the same material. In this case, there is no clear boundary between the portions where the gate dielectric 230 and the dielectric filling layer 400 contact each other.

[0086] In addition, reference Figure 1D and Figure 3 As an option, the isolation structure 300 may include an isolation dielectric layer 320 and an air gap 310-1 surrounded by the isolation dielectric layer to reduce interference between adjacent gate structures 200 in the semiconductor device 1000; Figure 1C and Figure 3 Alternatively, the isolation structure 300 may include an isolation dielectric layer 320 and a conductive layer 310-2 surrounded by the isolation dielectric layer 310. By applying a reference voltage (eg, a ground voltage) to the conductive layer 310-2, interference between adjacent gate structures 200 in the semiconductor device 1000 may be reduced.

[0087] Alternatively, the isolation dielectric layer 320 may be a composite structure having multiple layers and include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the isolation dielectric layer 320 may include silicon oxide. In addition, the conductive layer 310-2 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, and the like.

[0088] In order to simplify the manufacturing process and save production costs, the isolation dielectric layer 320 can be formed in the process of forming the gate dielectric 230, and the gate dielectric 230 and the isolation dielectric layer 320 can be made of the same material. In other words, the gate dielectric 230 and the isolation dielectric layer 320 can include insulating material layers made of the same material.

[0089] Similarly, to simplify the manufacturing process and save production costs, the same material may be used to manufacture the conductive layer 310-2 and the gate adhesive layer 210. In other words, the gate adhesive layer 210 and the conductive layer 310-2 may include conductive material layers of the same material.

[0090] As an option, the gate dielectric 230, the isolation dielectric layer 320 and the dielectric filling layer 400 may be made of the same material. In this case, there is no obvious boundary between the portions where the gate dielectric 230, the isolation dielectric layer 320 and the dielectric filling layer 400 contact each other.

[0091] In addition, if Figure 1C and 1B As shown, in some embodiments of the present application, the semiconductor device 1000 further includes a bit line structure 500 , which extends in the x direction and contacts the end portions 1 of the plurality of semiconductor pillars 100 , so that the plurality of semiconductor pillars 100 are connected to each other through the bit line structure 500 .

[0092] Optionally, the bit line structure 500 may be a composite structure, for example, including a first bit line layer (not shown) and a second bit line layer (not shown) stacked in sequence in the z direction. Optionally, the first bit line layer may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The second bit line layer may include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable semiconductor material. Optionally, the second bit line layer is located above the first bit line layer and contacts the ends of the plurality of semiconductor pillars 100.

[0093] In addition, in some embodiments of the present application, the gate structure 200 includes an upper surface and a lower surface relative to each other in the z direction, and the isolation structure 300 includes a top surface and a bottom surface relative to each other in the z direction. Among them, the upper surface of the gate structure 200 and the top surface of the isolation structure 300 may be located at different heights in the z direction. For example, the upper surface of the gate structure 200 is higher than the top surface of the isolation structure 300 in the z direction. The lower surface of the gate structure 200 and the bottom surface of the isolation structure 300 may be located at different heights in the z direction. For example, the lower surface of the gate structure 200 is higher than the bottom surface of the isolation structure 300 in the z direction. As a result, the gate control capability of the gate structure can be enhanced, and the anti-interference capability of the gate structure 200 can be improved.

[0094] Some embodiments of the present application provide a method for manufacturing a semiconductor device. Figure 4 is a flow chart of a method 2000 for fabricating a semiconductor device according to an exemplary embodiment of the present application. Figure 5-Figure 20 They are respectively process schematic diagrams of a method 2000 for preparing a semiconductor device according to an embodiment of the present application.

[0095] like Figure 4 As shown, the present application provides a method 2000 for preparing a semiconductor device, comprising:

[0096] S1, forming a semiconductor column, wherein the semiconductor column extends along a first direction and includes at least one side surface.

[0097] S2, forming an isolation sacrificial layer, wherein the isolation sacrificial layer extends along the second direction and is opposite to a portion of the side surface of the semiconductor pillar in the third direction, and the first direction, the second direction and the third direction intersect each other.

[0098] S3, forming a gate structure surrounding the remaining side surfaces of the semiconductor pillar, wherein a second portion of the gate structure contacts the isolation sacrificial layer, and the second portion is a portion of the gate structure located between the semiconductor pillars adjacent to each other in the second direction.

[0099] S4, removing the isolation sacrificial layer, and forming an isolation structure in the first gap formed after removing the isolation sacrificial layer.

[0100] The following will be combined Figures 4 to 20 The specific process in each step of the above-mentioned preparation method 2000 is described in detail.

[0101] Step S1

[0102] Figure 5 It is a schematic cross-sectional view of a structure formed after forming a semiconductor layer 100 ′ according to a preparation method in one embodiment of the present application. Figure 6 yes Figure 5 The intermediate body is shown as a schematic top view taken along line AA' or line BB'. Figure 7 It is a schematic cross-sectional view of a structure formed after a semiconductor column 100 is formed according to a preparation method in one embodiment of the present application. Figure 8 yes Figure 7 The intermediate body is shown as a schematic top view taken along line AA' or line BB'.

[0103] like Figures 4 to 8As shown, step S1 forms a semiconductor column, wherein the semiconductor column extends along a first direction and includes at least one side, which may, for example, include: forming a base structure, wherein the base structure includes a semiconductor layer 100' and a spacer layer 101 alternately distributed along a second direction (x direction); forming a first trench 01 and a second trench 02 extending along the x direction respectively in the base structure, wherein a plurality of first trenches 01 and a plurality of second trenches 02 are alternately distributed along a third direction (y direction) to divide the semiconductor layer 100' into a plurality of semiconductor columns 100.

[0104] Specifically, in one embodiment of the present application, the semiconductor layer 100' may be formed by a substrate (not shown). The material for preparing the substrate may be any suitable semiconductor material, such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or III-V compounds such as gallium arsenide. As an option, the substrate may be single crystal silicon.

[0105] In one embodiment of the present application, the substrate may be, for example, a composite substrate for supporting a device structure thereon. The substrate may be formed by sequentially arranging a plurality of layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0106] In one embodiment of the present application, the substrate may include a substrate sacrificial layer. Optionally, the substrate sacrificial layer may include a single layer, a multilayer or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. As an option, the substrate sacrificial layer may be a high dielectric constant dielectric layer. As another option, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer and a dielectric layer arranged in sequence, wherein the dielectric layer may be a silicon nitride layer and the sacrificial layer may be a silicon oxide layer. As another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material and a conductive material. For example, the sacrificial layer may be silicon nitride.

[0107] In addition, a part of the substrate may also form a well region formed by doping with an N-type or P-type dopant via an ion implantation or diffusion process. The dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb); or any one or a combination of boron (B), gallium (Ga) or indium (In). In some embodiments of the present application, the well region may be prepared with the same dopant or with different dopants. Furthermore, the doping concentration of the well region may be the same or different, which is not limited in the present application.

[0108] After forming the substrate, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed to remove part of the substrate to form a plurality of openings (not shown) spaced apart along the x direction, wherein the remaining part of the substrate is also spaced apart in the x direction to form a plurality of semiconductor layers 100'. Then, as Figure 5-Figure 6 As shown, the plurality of openings may be filled by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof to form a spacer layer 101. Any suitable dielectric material may be used to form the spacer layer 101. Optionally, the spacer layer 101 may include at least one of silicon oxide, silicon nitride, silicon oxynitride or a high-k dielectric.

[0109] like Figure 5-Figure 8 As shown, after the base structure is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., to form a first groove 01 and a second groove 02 extending in the base structure along a first direction (z direction) respectively in the contact structure, wherein a plurality of first grooves 01 and a plurality of second grooves 02 are alternately distributed in the y direction to divide the semiconductor layer 100' into a plurality of semiconductor pillars 100.

[0110] Optionally, the extension lengths of the multiple first trenches 01 in the z direction may be the same. Similarly, the extension lengths of the multiple second trenches 02 in the z direction may be the same. As described above, a gate structure and an isolation structure will be formed in the first trench and the second trench later, so that the extension lengths of the multiple gate structures in the z direction may be the same, and the extension lengths of the multiple isolation structures in the z direction may be the same, thereby improving the structural consistency of the storage unit in the semiconductor device and improving the impact of structural differences on the performance of the semiconductor device.

[0111] Step S2

[0112] Fig. 9 It is a schematic cross-sectional view of a structure formed after forming an initial first isolation dielectric layer 102 according to a preparation method in one embodiment of the present application. Fig.10 yes Fig. 9 The intermediate body is shown as a schematic top view taken along line AA' or line BB'. Fig.11 It is a schematic cross-sectional view of a structure formed after forming an isolation sacrificial layer 103 according to a preparation method in one embodiment of the present application. Fig.12 yes Fig.11 The intermediate body is shown as a schematic top view taken along line AA' or line BB'.

[0113] like Figure 7-Figure 12 As shown, step S2 forms an isolation sacrificial layer, wherein the isolation sacrificial layer extends along the second direction and is opposite to a portion of the side surface of the semiconductor column in the third direction, and the first direction, the second direction and the third direction intersect with each other, which may for example include: forming an initial first isolation dielectric layer 102, wherein the initial first isolation dielectric layer 102 is at least located on the sidewalls and the bottom surface of the second trench 02; and filling the isolation sacrificial layer 103 in the remaining space 02' of the second trench.

[0114] Alternatively, if Figure 7-10 As shown, in one embodiment of the present application, the initial first isolation dielectric layer 102 may be formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The initial first isolation dielectric layer 102 may be located on the sidewalls and bottom surface of the second trench 02, the sidewalls and bottom surface of the first trench 0, and the top surface of the semiconductor pillar 100. The initial first isolation dielectric layer 102 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the initial first isolation dielectric layer 102 may include silicon oxide.

[0115] Optionally, the initial first isolation dielectric layer 102 may be made of the same material as the spacer layer 101 , so as to be removed in the same step later.

[0116] like Figure 9-11 As shown, after forming the initial first isolation dielectric layer 102, the isolation sacrificial layer 103 can be filled in the remaining space 02' of the second groove by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0117] As an option, the isolation sacrificial layer 103 may be formed of a material with a high deposition rate to facilitate rapid filling of the remaining space 02' of the second trench, and the isolation sacrificial layer 103 should be any material with a high dry etching selectivity relative to the initial first isolation dielectric layer 102 to facilitate removal in subsequent steps. In one embodiment of the present application, the isolation sacrificial layer 103 may include a silicon nitride layer, etc. In addition, during the filling process, multiple gaps may be formed in the isolation sacrificial layer 103 by controlling the trench filling process to relieve structural stress.

[0118] Step S3

[0119] Fig.13 It is a cross-sectional schematic diagram of a structure formed after a portion of the initial first isolation dielectric layer 102 is removed according to a preparation method in one embodiment of the present application. Fig.14 yes Fig.13 The intermediate body is shown as a schematic top view taken along line AA' or line BB'. Fig.15 It is a schematic cross-sectional view of a structure formed after forming a gate structure 200 according to a preparation method in one embodiment of the present application. Fig.16 yes Fig.15 The intermediate body is shown in a schematic top view taken along line AA'. Fig.17 yes Fig.15 The intermediate body is shown in a schematic top view taken along line BB'.

[0120] like Figure 11-Figure 17 As shown, step S3 forms a gate structure around the remaining side surfaces of the semiconductor pillar, wherein the second portion of the gate structure contacts the isolation sacrificial layer, and the second portion is the portion of the gate structure located between the semiconductor pillars adjacent in the second direction, which may include, for example: removing the spacer layer 101 and a portion of the initial first isolation dielectric layer 102 to form a second gap 03 and exposing a portion of the isolation sacrificial layer 103, wherein the removed portion of the initial first isolation dielectric layer 102 is located between the semiconductor pillars 100 adjacent in the x direction; forming a gate structure 200 on the side surfaces of the semiconductor pillars 100 exposed in the second gap 03 and on the exposed portion of the isolation sacrificial layer 103.

[0121] Specifically, refer to Figure 11-Figure 14 In one embodiment of the present application, the first isolation dielectric layer 102 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, to remove the spacer layer 101 and a portion of the initial first isolation dielectric layer 102. After this operation, the remaining portion of the initial first isolation dielectric layer 102 is formed into a first isolation dielectric layer 102', and the first isolation dielectric layer 102' is located between the isolation sacrificial layer 103 and the semiconductor pillar 100.

[0122] like Fig.14 As shown in the dotted oval box, the removed portion of the initial first isolation dielectric layer 102 is located between the semiconductor pillars 100 adjacent to each other in the x direction, so after the above operation, a portion of the isolation sacrificial layer 103 may be exposed.

[0123] Afterwards, if Figure 13-Figure 17 As shown, a gate structure 200 can be formed on the side of the semiconductor pillar 100 exposed in the second gap 03 and on the exposed portion of the isolation sacrificial layer 103 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0124] Optionally, the gate structure 200 includes a gate dielectric layer 230 and a gate conductor layer 12, wherein the gate dielectric layer 230 is located between the side surface 130 of the semiconductor pillar 100 and the gate conductor layer 12. Optionally, the gate conductor layer 12 may further include a gate adhesion layer 210 and a gate metal layer 220.

[0125] A gate dielectric layer 230 is formed on the side surface 130 of the semiconductor pillar 100 exposed in the second gap 03 and on the surface of the exposed portion of the isolation sacrificial layer 103 ; and a gate adhesion layer 210 and a gate metal layer 220 are sequentially formed on the surface of the gate dielectric layer 230 .

[0126] Optionally, the gate dielectric layer 230 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 230 may include silicon oxide. In addition, the gate adhesion layer 210 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the gate metal layer 220 may include any suitable conductive material, such as the gate metal layer 220 may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The gate adhesion layer 210 is used to block the diffusion of metal materials in the gate metal layer 220, and is also used to improve the adhesion between the gate metal layer 220 and the gate dielectric layer 230.

[0127] like Fig.15 and Fig.17 As shown, the gate structure 200 extends continuously in a plane perpendicular to the z-direction (e.g., the xy plane) and surrounds the side surfaces 130 of multiple semiconductor pillars 100 that are not opposite to the isolation sacrificial layer 103, such as the second side surface 132, the third side surface 133, and the fourth side surface 134, thereby increasing the contact area between the gate structure and the semiconductor pillar to improve the gate control capability of the gate structure, and on this basis, improve the switching speed of the gate structure and the reliability of the semiconductor device.

[0128] In addition, if Fig.17 As shown, multiple gate structures adjacent to the same isolation sacrificial layer 103 are symmetrically distributed on two opposite sides of the same isolation structure in the y direction. For example, the first gate structure 201, the second gate structure 202, the third gate structure 203, and the fourth gate structure 204 are symmetrically distributed on two opposite sides of the isolation sacrificial layer 103 in the y direction.

[0129] In addition, in one embodiment of the present application, the gate structure 200 includes a plurality of first portions 200-1 and a plurality of second portions 200-2, wherein at least one of the plurality of first portions 200-1 surrounds the side surface 130 of the semiconductor pillar 100, and at least one of the plurality of second portions 200-2 extends along the x-direction, contacts the isolation sacrificial layer 103, and connects the first portions 200-1 adjacent to each other in the x-direction.

[0130] In addition, at least one of the plurality of first portions 200-1 includes a plurality of sub-portions connected to each other, such as a first sub-portion 200-11 and a second sub-portion 200-12, wherein the number of sub-portions is the same as the number of the remaining side surfaces of the semiconductor column 100; and the sub-portion is located on one of the remaining side surfaces of the semiconductor column 100. For example, Fig.17 The semiconductor pillar 100 shown includes a first side 131, a second side 132, a third side 133 and a fourth side 134. The isolation sacrificial layer 103 is opposite to the first side 131 in the y direction, and the remaining sides of the semiconductor pillar 100 are the second side 132, the third side 133 and the fourth side 134. At least one of the plurality of first portions 200-1 includes a plurality of sub-portions connected to each other, such as a first sub-portion 200-11, a second sub-portion 200-12 and a third sub-portion 200-13. The first sub-portion 200-11, the second sub-portion 200-12 and the third sub-portion 200-13 are located on the second side 132, the third side 133 and the fourth side 134, respectively.

[0131] Optionally, in a plane perpendicular to the z-direction, a projection of the semiconductor pillar 100 is located within a projection of the first portion 200 - 1 of the gate structure 200 .

[0132] In addition, after forming the gate structure 200, a first dielectric filling layer 104 may be formed by one or more thin film deposition processes. The first dielectric filling layer 104 is at least filled between adjacent gate structures 200, between adjacent semiconductor pillars 100, and on the top surface of the isolation sacrificial layer 103. The thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0133] Optionally, the first dielectric filling layer 104 and the initial first isolation dielectric layer 102 may be made of the same material. In this case, there is no obvious boundary between the contacting portions of the first dielectric filling layer 104 and the initial first isolation dielectric layer 102 .

[0134] Step S4

[0135] Fig.18 It is a schematic cross-sectional view of a structure formed after forming the first gap 04 according to a preparation method in one embodiment of the present application. Fig.19 yes Fig.18 The intermediate body is shown in a schematic top view taken along line AA'. Fig. 20 yes Fig.18 The intermediate body is shown in a schematic top view taken along line BB'.

[0136] As an option, Figure 1C-Figure 3 , Figure 15-Figure 20 As shown, step S4 removes the isolation sacrificial layer 103, and forms an isolation structure 300 in the first gap 04 formed after removing the isolation sacrificial layer 103, which may, for example, include: removing the isolation sacrificial layer 103 to form the first gap 04; forming a first portion 321 of an isolation dielectric layer 320 in the first gap 04, wherein the first portion 321 at least covers the initial first isolation dielectric layer 102; forming a conductive layer 310-2 in the remaining space of the first gap 04; and covering the second portion 322 of the isolation dielectric layer 320 on the surface of the conductive layer to form an isolation structure 300, wherein the isolation structure 300 includes the first portion 321 of the isolation dielectric layer 320, the second portion 322 of the isolation dielectric layer 320, and the conductive layer 310-2.

[0137] Specifically, Figure 15-Figure 20 As shown, in one embodiment of the present application, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove the isolation sacrificial layer 103 to form the first gap 04.

[0138] refer to Figure 1C-Figure 3 , Figure 15-Figure 20After forming the first gap 04, a first portion 321 of the isolation dielectric layer 320 may be formed on the surface of the initial first isolation dielectric layer 102 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The first portion 321 of the isolation dielectric layer 320 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the first portion 321 may include silicon oxide.

[0139] After forming the first portion 321 of the isolation dielectric layer 320, a conductive layer 310-2 may be formed in the remaining space of the first gap 04 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The conductive layer 310-2 may include but is not limited to titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0140] After forming the conductive layer 310-2, the second portion 322 of the isolation dielectric layer 320 may be covered on the surface of the conductive layer by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The second portion 322 of the isolation dielectric layer 320 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the isolation dielectric layer 320 may include silicon oxide.

[0141] Optionally, the first portion 321 of the isolation dielectric layer 320 and the second portion 322 of the isolation dielectric layer 320 may be made of the same material, in which case there is no obvious boundary between the contacting portions of the first portion 321 of the isolation dielectric layer 320 and the second portion 322 of the isolation dielectric layer 320 .

[0142] As another option, Figure 1D-Figure 3 , Figure 15-Figure 20As shown, step S4 of removing the isolation sacrificial layer 103 and forming the isolation structure 300 in the first gap 04 formed after removing the isolation sacrificial layer 103 may include, for example: removing the isolation sacrificial layer 103 to form the first gap 04; using a deposition process to form an isolation dielectric layer 320 at least covering the initial first isolation dielectric layer 102 in the first gap 04, wherein the isolation dielectric layer 320 includes a first portion 321 and a second portion 322; forming the first portion 321 and the second portion 322 of the isolation dielectric layer 320 by using two different deposition rates, and forming an air gap 310-1 in the first gap 04. The isolation structure 300 includes the first portion 321 and the second portion 322 of the isolation dielectric layer 320 and the air gap 310-1.

[0143] Specifically, Figure 15-Figure 20 As shown, in one embodiment of the present application, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove the isolation sacrificial layer 103 to form the first gap 04.

[0144] refer to Figure 1D-Figure 3 , Figure 15-Figure 20 After forming the first gap 04, an isolation dielectric layer 320 may be formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0145] The isolation dielectric layer 320 includes a first portion 321 and a second portion 322. The first portion 321 and the second portion 322 may each include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the first portion 321 and the second portion 322 may include silicon oxide. Optionally, the first portion 321 of the isolation dielectric layer 320 and the second portion 322 of the isolation dielectric layer 320 may be made of the same material, in which case there is no obvious boundary between the portions where the first portion 321 of the isolation dielectric layer 320 and the second portion 322 of the isolation dielectric layer 320 contact each other.

[0146] The deposition process used to form the first portion 321 and the second portion 322 of the isolation dielectric layer 320 may include two deposition rates of different sizes to form the air gap 310-1. As an option, the first deposition rate and the second deposition rate may be used simultaneously to form the first portion 321 and the second portion 322 of the isolation dielectric layer 320 on the surface of the initial first isolation dielectric layer 102, wherein the first portion 321 is located above the second portion 322, and the first deposition rate for forming the first portion 321 is greater than the second deposition rate for forming the second portion 322, so that the surface of the first portion 321 located above, which is formed by the faster first deposition rate, can correspondingly seal part of the space, thereby affecting the second portion 322 located below, which is formed by the slower first deposition rate, to form the air gap 310-1. In this option, the isolation structure 300 includes the first portion 321 and the second portion 322 of the isolation dielectric layer 320, and the air gap 310-1.

[0147] According to the semiconductor device preparation method provided by at least one embodiment of the present application, the semiconductor device may include a semiconductor column, an isolation structure and a gate structure, wherein the semiconductor column includes at least one side, the isolation structure is opposite to part of the side of the semiconductor column in a direction intersecting both the extension direction of the semiconductor column and its own extension direction, and the gate structure surrounds the remaining side of the semiconductor column. In addition, multiple gate structures adjacent to the same isolation structure can be symmetrically distributed on two opposite sides of the same isolation structure. Thus, the gate control capability of the gate structure can be improved by increasing the contact area between the gate structure and the semiconductor column. On this basis, the isolation structure can reduce the interference between adjacent gate structures in the semiconductor device, improve the switching speed of the gate structure and the reliability of the semiconductor device; symmetrically distributing multiple gate structures adjacent to the same isolation structure on two opposite sides of the same isolation structure can effectively reduce the size of the semiconductor device and improve the impact of structural differences on the performance of the semiconductor device.

[0148] in addition, Fig.21 It is a schematic diagram of the structure of a storage system 30000 according to one embodiment of the present application.

[0149] like Fig.21 As shown, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any embodiment above, and the present application will not repeat it. The semiconductor device 20000 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device. The following will be described by taking a three-dimensional semiconductor device as an example.

[0150] As an option, the three-dimensional semiconductor device may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0151] The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the above embodiments, and this application will not repeat them. The controller 32000 may control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 may perform operations based on the control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access an area selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 may perform an internal operation corresponding to the command on the area selected by the address.

[0152] In some embodiments, the three-dimensional storage system can be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system provided in the present application has the same beneficial effects as the semiconductor device provided in the present application because the semiconductor device provided in the present application is provided, and no further description is given here.

[0153] Although an exemplary method and structure of manufacturing a semiconductor device are described herein, it is understood that one or more features may be omitted, replaced or added from the structure of the semiconductor device. In addition, the materials of each layer exemplified are merely exemplary.

[0154] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by the selected combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor column extending along a first direction and comprising at least one side surface; an isolation structure extending along a second direction, wherein the isolation structure is opposite to a portion of a side surface of the semiconductor pillar in a third direction, and the first direction, the second direction and the third direction intersect each other; A gate structure surrounding the remaining sides of the semiconductor column, The plurality of gate structures adjacent to the same isolation structure are symmetrically distributed on two opposite sides of the same isolation structure in the third direction.

2. The semiconductor device according to claim 1, wherein The plurality of gate structures adjacent to the same isolation structure are distributed on the two sides of the same isolation structure in a mirror-symmetrical manner.

3. The semiconductor device according to claim 1, wherein The isolation structure includes an isolation dielectric layer and an air gap surrounded by the isolation dielectric layer.

4. The semiconductor device according to claim 1, wherein: The isolation structure includes an isolation dielectric layer and a conductive layer surrounded by the isolation dielectric layer.

5. The semiconductor device according to claim 4, wherein: The gate structure includes a gate dielectric layer and a gate conductor layer, wherein the gate dielectric layer is located between a side surface of the semiconductor pillar and the gate conductor layer.

6. The semiconductor device according to claim 5, wherein: The gate conductor layer and the conductive layer include a conductive material layer of the same material.

7. The semiconductor device according to claim 1, wherein The gate structure includes a plurality of first portions and a plurality of second portions, wherein at least one of the plurality of first portions surrounds a side surface of the semiconductor pillar, and at least one of the plurality of second portions extends along the second direction and connects adjacent first portions in the second direction.

8. The semiconductor device according to claim 7, wherein: At least one of the plurality of first sections comprises a plurality of subsections connected to each other, wherein the number of the sub-portions is the same as the number of the remaining side surfaces of the semiconductor column; and The sub-portion is located on one of the remaining side surfaces of the semiconductor column.

9. The semiconductor device according to claim 7, wherein: In a plane perpendicular to the first direction, a projection of the semiconductor column is located within a projection of the first portion.

10. The semiconductor device according to claim 1, wherein A cross-sectional shape of the semiconductor pillar in a plane perpendicular to the first direction includes at least one of a rectangular shape, a trapezoidal shape, a circular shape, and an elliptical shape.

11. The semiconductor device according to claim 1, wherein The semiconductor column is in a hexahedral shape and includes four side surfaces. wherein the isolation structure is opposite to a side surface of the semiconductor column in the third direction; and The gate structure surrounds the remaining three sides of the semiconductor column.

12. A method for manufacturing a semiconductor device, characterized in that: include: forming a semiconductor column, wherein the semiconductor column extends along a first direction and includes at least one side surface; forming an isolation sacrificial layer, wherein the isolation sacrificial layer extends along a second direction and is opposite to a portion of a side surface of the semiconductor pillar in a third direction, and the first direction, the second direction and the third direction intersect each other; forming a gate structure surrounding the remaining side surfaces of the semiconductor pillar, wherein a second portion of the gate structure contacts the isolation sacrificial layer, and the second portion is a portion of the gate structure located between semiconductor pillars adjacent to each other in the second direction; as well as The isolation sacrificial layer is removed, and an isolation structure is formed in the first gap formed after the isolation sacrificial layer is removed.

13. The method according to claim 12, wherein: Forming the semiconductor column includes: forming a base structure, wherein the base structure comprises semiconductor layers and spacer layers alternately distributed along the second direction; forming a first groove and a second groove extending in the second direction respectively in the base structure, The plurality of first trenches and the plurality of second trenches are alternately distributed along the third direction to divide the semiconductor layer into a plurality of semiconductor pillars.

14. The method according to claim 13, wherein: Forming the isolation sacrificial layer includes: forming an initial first isolation dielectric layer, wherein the initial first isolation dielectric layer is at least located on the sidewalls and bottom surface of the second trench; and The remaining space of the second trench is filled with the isolation sacrificial layer.

15. The method according to claim 14, wherein: Forming a gate structure surrounding the remaining side surfaces of the semiconductor pillar comprises: Removing the spacer layer and a portion of the initial first isolation dielectric layer to form a second gap and expose a portion of the isolation sacrificial layer, wherein the removed portion of the initial first isolation dielectric layer is located between semiconductor pillars adjacent to each other in the second direction; The gate structure is formed on the side surface of the semiconductor column exposed in the second gap and on the exposed portion of the isolation sacrificial layer.

16. The method according to claim 14, wherein: Removing the isolation sacrificial layer and forming an isolation structure in the first gap formed after removing the isolation sacrificial layer comprises: removing the isolation sacrificial layer to form the first gap; forming a first portion of an isolation dielectric layer in the first gap, wherein the first portion at least covers the initial first isolation dielectric layer; forming a conductive layer in a remaining space of the first gap; and The second portion of the isolation dielectric layer is covered on the surface of the conductive layer to form the isolation structure. The isolation structure includes the first part, the second part and the conductive layer.

17. The method according to claim 14, wherein: Removing the isolation sacrificial layer and forming an isolation structure in the first gap formed after removing the isolation sacrificial layer comprises: removing the isolation sacrificial layer to form the first gap; and By using a deposition process, an isolation dielectric layer is formed in the first gap, at least covering the initial first isolation dielectric layer. Wherein, the isolation dielectric layer includes a first part and a second part; forming the first portion and the second portion by using two deposition rates of different magnitudes, thereby forming an air gap in the first void; and The isolation structure includes the first portion, the second portion, and the air gap.

18. A memory system, characterized in that: include: A controller and a semiconductor device as claimed in any one of claims 1 to 11, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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