An enhanced GaN HEMT device and a method of fabricating the same

Abstract

This invention discloses a method for fabricating an enhancement-mode GaN HEMT device, comprising: growing a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a blocking layer on a substrate; etching away the blocking layer and part of the barrier layer at the middle position; epitaxially growing a capping layer on the etched region and the upper surface of the blocking layer; thinning the capping layer to the blocking layer; removing the blocking layer to expose the barrier layer; performing ion implantation on both sides of the barrier layer, channel layer, and buffer layer to obtain ion implantation isolation regions; plasma treating both sides of the barrier layer to obtain plasma-treated regions, forming source and drain electrodes in the plasma-treated regions; growing a dielectric layer on the upper surface of the barrier layer, source, drain, and capping layer; forming a gate electrode on the dielectric layer; growing a passivation layer on the upper surface of the dielectric layer and gate electrode; etching the dielectric layer and passivation layer to expose the gate, source, and drain electrodes. This invention also discloses an enhancement-mode GaN HEMT device, which can improve device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to an enhancement-mode GaN HEMT device and its fabrication method. Background Technology

[0002] With the development of technology, the performance requirements for power semiconductor materials are becoming increasingly stringent. To improve device performance, gallium nitride (GaN) materials have been discovered and applied. As a third-generation semiconductor, GaN materials have a wider bandgap, a higher critical breakdown electric field, and stronger radiation resistance compared to traditional silicon-based materials and second-generation semiconductors (represented by gallium arsenide). In particular, high electron mobility transistors (GaN HEMTs) composed of gallium nitride (GaN) and aluminum gallium nitride (AlGaN) exhibit very high electron mobility. The principle of GaN HEMTs is based on the formation of a natural conductive channel through spontaneous polarization and piezoelectric polarization effects, making them inherently depletion-mode devices. However, in applications such as power electronics, enhancement-mode devices are required to improve safety. Therefore, enhancement-mode GaN HEMT devices are urgently needed in the industry.

[0003] Currently, there are several main methods for realizing enhancement-mode GaN HEMT devices: cascaded enhancement-mode Si MOS transistors and D-mode depletion-mode GaN HEMTs to form Cascode structures, P-type gate structures, recessed gate structures, and fluorine ion implantation structures. Among these, Cascode, P-type gate, and recessed gate structures have already been commercially applied.

[0004] For a P-type gate GaN HEMT device, its epitaxial structure, from bottom to top, typically consists of: substrate, nucleation layer, buffer layer, channel layer, barrier layer, and p-GaN capping layer. The main principle is to use the p-GaN capping layer to raise the conduction band at the channel interface, increasing it above the Fermi level to deplete the two-dimensional electron gas. The fabrication process for enhancement-mode GaN HEMTs based on this traditional epitaxial structure is typically as follows: patterning the p-GaN gate; etching the p-GaN capping layer outside the gate region to expose the AlGaN barrier layer using photolithography and etching processes; depositing a passivation layer; etching the passivation layer to expose the source and drain regions; growing source and drain electrode metals and rapidly thermally annealing to form ohmic contacts; etching the passivation layer to expose the gate region; and growing gate metal to form a Schottky contact gate.

[0005] The above process has several problems:

[0006] 1. When epitaxially growing AlGaN barrier layer and p-GaN capping layer, the p-GaN capping layer usually needs to be doped with magnesium bis(CP2Mg) as a dopant. However, the temperature is usually high during MOCVD. Mg ions will diffuse downward to the AlGaN barrier layer and even the GaN channel layer. The diffused Mg ions act as acceptor impurities, which will reduce the two-dimensional electron gas concentration, thereby increasing the on-resistance and affecting the device performance.

[0007] 2. In the process of patterning the p-GaN capping layer, the ideal situation is to etch away the entire p-GaN capping layer outside the gate region until the AlGaN barrier layer surface is just exposed. However, in practice, it is impossible to stop exactly at the AlGaN barrier layer surface. Generally, 2nm to 5nm of the AlGaN barrier layer is over-etched, making it difficult to control the etching precision. This reduction in thickness reduces the two-dimensional electron gas concentration, increasing the on-resistance of the device. If the remaining p-GaN capping layer is not completely etched away, the on-resistance and leakage current of the device will increase, degrading device performance.

[0008] 3. To achieve more precise etching, the etching selectivity of GaN / AlGaN needs to be improved. Currently, oxygen-containing gases such as Cl2 / O2 or fluorine-containing gases such as BCl3 / SF6 are commonly used to generate Al2O3 and AlF3 dielectric layers, which are more difficult to etch, during the etching process to AlGaN, thereby improving the etching selectivity. If the subsequent source / drain metals are grown directly on these two dielectric layers, it will increase the contact resistance of the ohmic contacts, resulting in a larger on-resistance and reduced device performance. Summary of the Invention

[0009] In view of this, the purpose of this invention is to provide a method for fabricating an enhanced GaN HEMT device.

[0010] To achieve the above-mentioned technical objectives, the technical solution adopted by this invention is as follows:

[0011] This invention provides a method for fabricating an enhanced GaN HEMT device, comprising the following steps:

[0012] Step 1: Epitaxially grow a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a blocking layer sequentially on the substrate;

[0013] Step 2: Etch away the barrier layer and part of the potential barrier layer in the middle to obtain the etched area;

[0014] Step 3: Epitaxially grow a capping layer on the upper surface of the etched area and the barrier layer;

[0015] Step 4: Thin the cap layer down to the top surface of the barrier layer;

[0016] Step 5: Remove the barrier layer to expose the barrier layer; perform ion implantation on both sides of the barrier layer, both sides of the channel layer, and both sides of the upper surface of part of the buffer layer to obtain the ion implantation isolation region.

[0017] Step 6: Define the source region and drain region on the left and right sides above the barrier layer, respectively. After plasma treatment in the source region and drain region, a plasma treatment region is obtained. The source and drain are formed on the upper surface of the plasma treatment region. After annealing the source and drain, an ohmic contact is formed.

[0018] Step 7: Grow dielectric layers on the upper surfaces of the barrier layer, source, drain, and capping layer;

[0019] Step 8: Define a gate region on the upper surface of the dielectric layer and directly above the capping layer, and form a gate in the gate region;

[0020] Step 9: Grow a passivation layer on the dielectric layer and the upper surface of the gate;

[0021] Step 10: Etch the passivation layer above the gate, as well as the dielectric and passivation layers above the source and drain, to expose the gate, source, and drain.

[0022] Furthermore, in step 1, the thickness of the barrier layer is 15nm to 40nm, and the thickness of the blocking layer is 70nm to 110nm.

[0023] Furthermore, in step 2, the etching depth of the barrier layer is 5nm to 15nm, the remaining depth is 5nm to 25nm, and the sum of the etching depth and the remaining depth of the barrier layer is equal to the thickness of the barrier layer.

[0024] Furthermore, in step 3, the concentration of Mg ions doped in the capping layer is greater than 10. 19 cm -3 Furthermore, the thickness H1 of the capping layer located above the barrier layer is greater than 150 nm.

[0025] Furthermore, in step 4, the remaining cap layer thickness H2 after thinning is equal to the sum of the thickness of the barrier layer and the etching depth of the barrier layer, that is, the upper surface of the remaining cap layer after thinning is flush with the upper surface of the barrier layer.

[0026] Furthermore, the thickness of the dielectric layer is 5 nm to 10 nm.

[0027] Furthermore, the thickness of the passivation layer is 200nm to 500nm.

[0028] Furthermore, the epitaxial growth method in steps 1 and 3 is one of MOCVD, HVPE, and MBE; the removal of the barrier layer in step 5 is a wet removal technique; the plasma treatment in step 6 is hydrogen plasma; the dielectric layer growth method in step 7 is ALD; and the passivation layer growth method in step 9 is one of PECVD, LPCVD, and ALD.

[0029] Furthermore, the substrate material includes one or more of sapphire, Si, GaN, SiC, QST, SOI, and diamond;

[0030] The material of the nucleation layer is AlN;

[0031] The material of the buffer layer is one or more of the following: iron- or carbon-doped GaN and AlN / GaN alternating superlattice structures.

[0032] The channel layer is made of GaN;

[0033] The barrier layer is made of Al. x Ga 1-x N, x is 0.18-0.3.

[0034] The material of the barrier layer is Si3N4 or SiO2;

[0035] The capping layer is made of p-GaN;

[0036] The source electrode is made of one or more of Ti, Al, Ni, Au, TiN, and Pt.

[0037] The drain electrode is made of one or more of Ti, Al, Ni, Au, TiN, and Pt.

[0038] The material of the dielectric layer is AlN;

[0039] The gate material is one or more of Ni, Au, and TiN;

[0040] The passivation layer is made of SiO2 or Si3N4.

[0041] This invention also provides an enhancement-mode GaN HEMT device, which is fabricated according to the above-described method for fabricating an enhancement-mode GaN HEMT device. The device includes, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer. An etched region is provided on a portion of the upper surface of the barrier layer at its center, and a capping layer is grown within the etched region. Ion implantation isolation regions are provided on both sides of the barrier layer, both sides of the channel layer, and both sides of a portion of the upper surface of the buffer layer. A source region and a drain region are respectively provided on the upper left and right sides above the barrier layer, and plasma processing regions are provided within the source and drain regions. A source and drain electrode are formed on the upper surface of the plasma processing region. A dielectric layer is grown on the upper surfaces of the barrier layer, source, drain, and capping layer. A gate region is provided on the upper surface of the dielectric layer and directly above the capping layer, and a gate electrode is formed within the gate region. A passivation layer is grown on the upper surfaces of the dielectric layer and the gate electrode. Grooves are etched above the gate, source, and drain electrodes to expose them.

[0042] By adopting the above technical solution, the present invention has the following beneficial effects compared with the prior art:

[0043] 1. After etching the Si3N4 barrier layer and part of the AlGaN barrier layer in the epitaxial structure, the secondary epitaxial p-GaN capping layer can effectively prevent the diffusion of Mg ions doped in the p-GaN capping layer into the lower AlGaN barrier layer, avoiding the problem of increased on-resistance caused by Mg ion diffusion into the AlGaN barrier layer, thus ensuring device performance. Furthermore, the barrier layer will be removed subsequently to further reduce the impact of Mg ion diffusion. At the same time, since the Si3N4 barrier layer is removed by wet etching, the AlGaN barrier layer is directly exposed, avoiding the selective etching problem of the p-GaN capping layer / AlGaN barrier layer and the etching damage problem on the surface of the AlGaN barrier layer in traditional processes.

[0044] 2. The p-GaN capping layer is ground down to the Si3N4 barrier layer using chemical mechanical polishing (CMP), followed by wet removal of the Si3N4 barrier layer to complete the p-GaN capping layer patterning. Currently, some similar techniques directly peel off the p-GaN capping layer above the Si3N4 barrier layer. However, due to the good sidewall adhesion during film growth, the peeling process often results in uneven edges and burrs, affecting subsequent processes and device performance. Since CMP has different polishing speeds for different materials, the p-GaN capping layer can be better fixed to the Si3N4 barrier layer after polishing. Therefore, this invention not only obtains a relatively smooth p-GaN capping layer pattern but also has a larger process window. By removing the Si3N4 barrier layer using a wet process, the p-GaN capping layer can be directly patterned, directly avoiding the problems caused by p-GaN etching in traditional E-mode etching. These problems include reduced on-resistance due to over-etching of the AlGaN barrier layer, increased leakage current due to incomplete etching of the p-GaN capping layer, and reduced two-dimensional electron gas concentration caused by ion implantation during etching. Furthermore, the thickness of the remaining p-GaN capping layer can be better controlled by adjusting the thickness of the Si3N4 barrier layer.

[0045] 3. Since the surface of the p-GaN capping layer is polished, a 5-10nm AlN dielectric layer is grown by ALD. The surface of the p-GaN capping layer and the surface of the AlGaN barrier layer are passivated, which reduces the surface states and the gate leakage current. This improves the gate reliability and reduces the current collapse effect by passivating the surface of the AlGaN barrier layer.

[0046] 4. Hydrogen plasma pretreatment of the AlGaN barrier layer surface is used to reduce the ohmic contact resistance between the source and drain electrodes. Compared with techniques such as etching source / drain grooves and regrowing and doping of source / drain grooves, the process is simpler and fits the process flow of this invention. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 The diagram shows the basic epitaxial structure of a method for fabricating an enhancement-mode GaN HEMT device according to an embodiment of the present invention, in which a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a blocking layer are sequentially epitaxially grown on a substrate (schematic diagram of step 1).

[0049] Figure 2 In order to be in Figure 1The structure diagram of the etched area is shown in step 2.

[0050] Figure 3 In order to be in Figure 2 The structural diagram of the capping layer growing on the structure (schematic diagram of step 3).

[0051] Figure 4 In order to be in Figure 3 The structural diagram shows the reduction of the cap layer to the barrier layer (schematic diagram of step 4).

[0052] Figure 5 In order to be in Figure 4 The structural diagram of removing the barrier layer on the structure (schematic diagram of step 5).

[0053] Figure 6 In order to be in Figure 5 The structure of the ion implantation isolation region is obtained by performing ion implantation on both sides of the barrier layer, both sides of the channel layer, and both sides of the upper surface of part of the buffer layer (schematic diagram of step 5).

[0054] Figure 7 In order to be in Figure 6 The structure of the plasma treatment region is obtained after plasma treatment in the source and drain regions (schematic diagram of step 6).

[0055] Figure 8 In order to be in Figure 7 The structural diagram of the source and drain electrodes formed on the upper surface of the plasma processing region is shown in step 6.

[0056] Figure 9 In order to be in Figure 8 The structural diagram of the growing medium layer on the structure (schematic diagram of step 7).

[0057] Figure 10 In order to be in Figure 9 The structure of the gate is formed on the structure (schematic diagram of step 8).

[0058] Figure 11 In order to be in Figure 10 The structural diagram of the passivation layer grown on the structure (schematic diagram of step 9).

[0059] Figure 12 In order to be in Figure 11 The diagram shows the structure after etching the dielectric layer and passivation layer to expose the gate, source, and drain (schematic diagram of step 10).

[0060] The labels in the figure are as follows: 1-Substrate; 2-Nucleation layer; 3-Buffer layer; 4-Channel layer; 5-Barrier layer; 6-Blocking layer; 7-Capping layer; 8-Ion implantation isolation region; 9-Plasma treatment region; 10-Source; 11-Drain; 12-Dielectric layer; 13-Gate; 14-Passivation layer; 15-Etched region; 16-Source region; 17-Drain region; 18-Gate region; 19-Groove. Detailed Implementation

[0061] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the invention. Similarly, the following embodiments are only some, not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] Please see Figures 1-12 The present invention discloses a method for fabricating an enhanced GaN HEMT device, comprising the following steps:

[0063] Step 1: Epitaxially grow a core layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, and a blocking layer 6 sequentially on substrate 1. The epitaxial growth method is one of MOCVD (Metal-Organic Chemical Vapor Deposition), HVPE (Hydride Vapor Phase Epitaxy), and MBE (Molecular Beam Epitaxy). The thickness of the barrier layer 5 is 15 nm to 40 nm. If the barrier layer 5 is too thin, the two-dimensional electron gas concentration will decrease, increasing the on-resistance; if the barrier layer 5 is too thick, it will reduce crystal quality and generate a large number of defects. The thickness of the blocking layer 6 is 70 nm to 110 nm.

[0064] Step 2: Etch away the barrier layer 6 and part of the barrier layer 5 in the middle position to obtain the etched region 15; wherein the etching depth of the barrier layer 5 is 5nm to 15nm, the remaining depth is 5nm to 25nm, and the sum of the etching depth and the remaining depth of the barrier layer 5 is equal to the thickness of the barrier layer 5. The difference in the remaining depth will affect the threshold voltage; the lower the remaining depth, the higher the threshold voltage.

[0065] Step 3: Epitaxially grow a capping layer 7 on the upper surface of the etched region 15 and the barrier layer 6; wherein the Mg ion concentration doped in the capping layer 7 is greater than 10. 19 cm -3 Furthermore, the thickness H1 of the capping layer 7 located above the barrier layer 6 is greater than 150 nm, providing a certain process window for subsequent thinning processes. The epitaxial growth method employs one of MOCVD, HVPE, and MBE.

[0066] Step 4: Thin the capping layer 7 to the upper surface of the barrier layer 6; at this time, the remaining thickness H2 of the capping layer 7 after thinning is equal to the sum of the thickness of the barrier layer 6 and the etching depth of the barrier layer 5, that is, the upper surface of the remaining capping layer 7 after thinning is flush with the upper surface of the barrier layer 6.

[0067] Step 5: Remove the barrier layer 6 to expose the barrier layer 5. The barrier layer is removed using a wet removal technique, which can quickly and efficiently remove the Si3N4 barrier layer 6 and reduce damage to the surface of the AlGaN barrier layer 5. Ion implantation is performed on both sides of the barrier layer 5, both sides of the channel layer 4, and both sides of the upper surface of part of the buffer layer 3 to obtain the ion implantation isolation region 8.

[0068] Step 6: Define source region 16 and drain region 17 on the upper left and right sides of barrier layer 5, respectively. After plasma treatment of source region 16 and drain region 17, plasma treatment region 9 is obtained. The plasma treatment uses hydrogen plasma, which can generate NH3 and form nitrogen vacancies on the surface of AlGaN barrier layer 5, which is beneficial to reducing ohmic contact resistance. Source 10 and drain 11 are formed on the upper surface of plasma treatment region 9. After annealing, ohmic contact is formed on source 10 and drain 11.

[0069] Step 7: A dielectric layer 12 is grown on the surface of the barrier layer 5, source 10, drain 11 and capping layer 7 to reduce gate leakage current and protect the surface of the barrier layer 5 outside the gate region 18. The dielectric layer 12 has a thickness of 5 nm to 10 nm and is grown using ALD (atomic layer deposition).

[0070] Step 8: Define a gate region 18 on the upper surface of the dielectric layer 12 and directly above the capping layer 7, and form a gate 13 in the gate region 18.

[0071] Step 9: Grow a passivation layer 14 on the upper surface of the dielectric layer 12 and the gate 13 to passivate the device surface; wherein the thickness of the passivation layer 14 is 200nm to 500nm, and it is grown by one of PECVD (plasma-enhanced chemical vapor deposition), LPCVD (low-pressure chemical vapor deposition), and ALD (atomic layer deposition).

[0072] Step 10: Etch the passivation layer 14 above the gate 13 and the dielectric layer 12 and passivation layer 14 above the source 10 and drain 11 to expose the gate 13, source 10 and drain 11.

[0073] The substrate 1 is made of one or more of the following materials: sapphire, Si, GaN, SiC, QST, SOI, and diamond.

[0074] The material of the nucleation layer 2 is AlN;

[0075] The material of the buffer layer 3 is one or more of the following: iron- or carbon-doped GaN and AlN / GaN alternating superlattice structures.

[0076] The material of the channel layer 4 is GaN;

[0077] The material of the barrier layer 5 is Al. x Ga 1-x N, x is 0.18-0.3 (AlGaN mentioned below refers to the content of this component).

[0078] The material of the barrier layer 6 is Si3N4 or SiO2;

[0079] The material of the capping layer 7 is p-GaN;

[0080] The material of the source electrode 10 is one or more of Ti, Al, Ni, Au, TiN and Pt;

[0081] The material of the drain electrode 11 is one or more of Ti, Al, Ni, Au, TiN and Pt;

[0082] The material of the dielectric layer 12 is AlN;

[0083] The gate 13 is made of one or more of Ni, Au and TiN;

[0084] The passivation layer 14 is made of SiO2 or Si3N4.

[0085] Example 1:

[0086] 1) An AlN nucleation layer 2, a GaN buffer layer 3, a GaN channel layer 4, an AlGaN barrier layer 5, and a Si3N4 barrier layer 6 are sequentially deposited on a Si substrate 1 using MOCVD. Here, the thickness of the AlGaN barrier layer 5 is 25 nm, and the thickness of the Si3N4 barrier layer 6 is 70 nm. Figure 1 As shown.

[0087] 2) Using photolithography and etching processes, the Si3N4 barrier layer 6 in the middle position and part of the AlGaN barrier layer 5 (upper half surface) are etched. The Si3N4 barrier layer 6 in this region is completely etched away, and the AlGaN barrier layer 5 is etched to a depth of 15nm, leaving a remaining depth of 10nm. For example... Figure 2 As shown.

[0088] 3) A secondary epitaxial growth of p-GaN capping layer 7 was performed using MOCVD technology, wherein the Mg ion concentration in p-GaN capping layer 7 was greater than 10. 19cm -3 The thickness H1 of the p-GaN capping layer 7 located above the barrier layer 6 is 200 nm. For example... Figure 3 As shown.

[0089] 4) The p-GaN capping layer 7 is thinned to the upper surface of the Si3N4 barrier layer 6 using chemical mechanical polishing. For example... Figure 4 As shown, the remaining p-GaN capping layer 7 thickness H2 is 85 nm at this point. In addition to chemical mechanical polishing, ICP dry etching can also be used, or a combination of chemical mechanical polishing and ICP dry etching can be used. Increasing ICP dry etching can result in a lower surface roughness of the obtained p-GaN capping layer 7.

[0090] 5) Wet removal of the Si3N4 barrier layer 6 exposes the AlGaN barrier layer 5, such as... Figure 5 As shown, ion implantation is performed on both sides of the AlGaN barrier layer 5, both sides of the GaN channel layer 4, and both sides of a portion of the upper surface of the GaN buffer layer 3 to obtain the ion implantation isolation region 8, as shown. Figure 6 As shown;

[0091] 6) Using photolithography, source region 16 and drain region 17 are defined on the upper left and right sides of AlGaN barrier layer 5, respectively. After hydrogen plasma treatment of source region 16 and drain region 17, plasma-treated region 9 is obtained, as shown below. Figure 7 As shown. Source 10 and drain 11 are formed on the upper surface of plasma processing region 9 using electron beam evaporation. Source 10 is located on the left and drain 11 on the right. After RTA annealing (rapid thermal annealing) of source 10 (such as Ti / Al multilayer metal) and drain 11 (such as Ti / Al multilayer metal), an ohmic connection is formed, as shown. Figure 8 As shown, after rapid thermal annealing, the metallic Ti and AlGaN form a TiN alloy, thereby creating nitrogen vacancies in the AlGaN barrier layer 5. These nitrogen vacancies act as donor sites, achieving n-type doping and reducing ohmic contact resistance. Hydrogen plasma treatment can generate NH3 and form nitrogen vacancies on the surface of the AlGaN barrier layer 5, which also helps reduce ohmic contact resistance. Furthermore, since the Mg ions doped in the p-GaN capping layer 7 are blocked by the Si3N4 barrier layer 6 and do not diffuse to the AlGaN barrier layer 5, there is no Mg-H complex reducing the on-resistance. Moreover, compared to techniques such as etching source and drain trenches followed by regrowing doping, the plasma treatment process is simpler.

[0092] 7) An AlN dielectric layer 12 is grown using an ALD process to reduce the leakage current of the gate 13 while protecting the surface of the AlGaN barrier layer 5 outside the gate region 18. The thickness of the AlN dielectric layer 12 is 5 nm. Figure 9 As shown, compared to directly using PECVD or LPCVD to grow Si3N4 or SiO2 to passivate the AlGaN barrier layer 5, the AlN dielectric layer 12 grown using ALD has better density and can better passivate the surface of the AlGaN barrier layer 5. Arranging the growth of the AlN dielectric layer 12 and the subsequent passivation layer 14 after the source 10 and drain 11 RTA annealing can avoid the possibility of the existing AlN dielectric layer 12 cracking due to the metal melting and expansion caused by the high temperature of RTA annealing.

[0093] 8) A gate region 18 is defined on the upper surface of the AlN dielectric layer 12 and directly above the p-GaN capping layer 7 using photolithography. A gate 13 is formed in the gate region 18 using electron beam evaporation, forming a Schottky contact gate 13. Figure 10 As shown.

[0094] 9) A SiO2 passivation layer 14 is grown using PECVD technology to passivate the device surface. The SiO2 passivation layer 14 has a thickness of 200 nm. Figure 11 As shown.

[0095] 10) Using photolithography and etching processes, the SiO2 passivation layer 14 above the gate 13 and the AlN dielectric layer 12 and SiO2 passivation layer 14 above the source 10 and drain 11 are etched to expose the gate 13, source 10, and drain 11. For example... Figure 12 As shown.

[0096] This invention also provides an enhancement-mode GaN HEMT device, which is fabricated according to the above-described method for fabricating an enhancement-mode GaN HEMT device. The device comprises, from bottom to top, a Si substrate 1, an AlN nucleation layer 2, a GaN buffer layer 3, a GaN channel layer 4, and an AlGaN barrier layer 5. An etched region 15 is provided on a portion of the upper surface of the AlGaN barrier layer 5 at its middle position, such that the thickness of the AlGaN barrier layer 5 below the gate region 18 is less than the thickness of the AlGaN barrier layer 5 outside the gate region 18, thereby increasing the threshold voltage. A p-GaN capping layer 7 is grown within the etched region 15. Ion implantation isolation regions 8 are provided on both sides of the AlGaN barrier layer 5, both sides of the GaN channel layer 4, and both sides of a portion of the upper surface of the GaN buffer layer 3. An upper left and right side of the AlGaN barrier layer 5 are respectively provided with… The system includes a source region 16 and a drain region 17, within which a hydrogen plasma treatment region 9 is provided to reduce contact resistance. A source 10 and a drain 11 are formed on the upper surface of the hydrogen plasma treatment region 9. An AlN dielectric layer 12 is grown on the upper surface of the AlGaN barrier layer 5, the source 10, the drain 11, and the p-GaN capping layer 7. A gate region 18 is provided on the upper surface of the AlN dielectric layer 12 and directly above the p-GaN capping layer 7, and a gate 13 is formed within the gate region 18. A SiO2 passivation layer 14 is grown on the upper surface of the AlN dielectric layer 12 and the gate 13. A groove 19 is etched above the gate 13, the source 10, and the drain 11 to expose the gate 13, the source 10, and the drain 11.

[0097] In this embodiment, the AlGaN barrier layer 5 has a thickness of 25 nm, the etching depth at the center of the AlGaN barrier layer 5 is 15 nm, the remaining depth is 10 nm, and the sum of the etching depth and the remaining depth of the AlGaN barrier layer 5 is equal to the thickness of the AlGaN barrier layer 5. The thickness H2 of the p-GaN capping layer 7 (after thinning) is equal to the sum of the thickness of the Si3N4 barrier layer 6 and the etching depth of the AlGaN barrier layer 5, that is, the upper surface of the remaining p-GaN capping layer 7 after thinning is flush with the upper surface of the Si3N4 barrier layer 6. The thickness of the AlN dielectric layer 12 is 5 nm. The thickness of the SiO2 passivation layer 14 is 200 nm.

[0098] The device fabricated using the above method avoids the problem of increased on-resistance caused by Mg ion diffusion into the AlGaN barrier layer 5 due to the blocking effect of the Si3N4 barrier layer 6 on Mg ions. Furthermore, it allows for hydrogen plasma treatment of the AlGaN barrier layer 5 to form more nitrogen vacancies, reducing ohmic contact resistance. Wet removal of the Si3N4 barrier layer 6 replaces the selective etching process for p-GaN / AlGaN, avoiding the impact of over-etching of the AlGaN barrier layer 5 and incomplete p-GaN etching on device performance. Chemical mechanical polishing (CMP) results in smoother sidewalls for the gate 13. The AlN dielectric layer 12 passivates the surface of the AlGaN barrier layer 5 while reducing the leakage current of the gate 13. Devices fabricated using this method exhibit excellent performance.

[0099] The above description is only a part of the embodiments of the present invention and does not limit the scope of protection of the present invention. Any equivalent device or equivalent process transformation made based on the content of the present invention specification and drawings, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method of fabricating an enhanced GaN HEMT device, comprising: The method comprises the following steps: Step 1, sequentially epitaxially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a blocking layer on a substrate; Step 2, etching away the blocking layer and part of the barrier layer at the middle position to obtain an etching area; Step 3, epitaxially growing a cap layer on the etching area and the upper surface of the blocking layer; Step 4, thinning the cap layer to the upper surface of the blocking layer; Step 5, removing the blocking layer to expose the barrier layer, and performing ion implantation on both sides of the barrier layer, both sides of the channel layer and part of the upper surface of the buffer layer to obtain an ion implantation isolation area; Step 6, defining a source region and a drain region on the left side and the right side of the barrier layer respectively, performing plasma treatment on the source region and the drain region to obtain a plasma treatment area, and forming a source and a drain on the upper surface of the plasma treatment area, and performing annealing on the source and the drain to form an ohmic contact; Step 7, growing a medium layer on the upper surface of the barrier layer, the source, the drain and the cap layer; Step 8, defining a gate region on the upper surface of the medium layer and directly above the cap layer, and forming a gate on the gate region; Step 9, growing a passivation layer on the upper surface of the medium layer and the gate; Step 10, etching away the passivation layer above the gate, and the medium layer and the passivation layer above the source and the drain to expose the gate, the source and the drain.

2. The method of fabricating an enhanced GaN HEMT device of claim 1, wherein, The thickness of the barrier layer in step 1 is 15-40 nm, and the thickness of the blocking layer is 70-110 nm.

3. The method of fabricating an enhanced GaN HEMT device of claim 1, wherein, The etching depth of the barrier layer in step 2 is 5-15 nm, the remaining depth is 5-25 nm, and the sum of the etching depth and the remaining depth of the barrier layer is equal to the thickness of the barrier layer.

4. The method of fabricating an enhanced GaN HEMT device of claim 1, wherein, The concentration of the doped Mg ions in the cap layer in step 3 is greater than 10 19 cm -3 , and the thickness H1 of the cap layer above the barrier layer is greater than 150 nm.

5. The method of fabricating an enhanced GaN HEMT device of claim 1, wherein, The thickness H2 of the remaining cap layer after thinning in step 4 is equal to the sum of the thickness of the blocking layer and the etching depth of the barrier layer, that is, the upper surface of the remaining cap layer after thinning is flush with the upper surface of the blocking layer.

6. The method of fabricating an enhanced GaN HEMT device of claim 1, wherein, The thickness of the medium layer is 5-10 nm.

7. The method of fabricating an enhanced GaN HEMT device of claim 1, wherein, The thickness of the passivation layer is 200-500 nm.

8. The method of fabricating an enhanced GaN HEMT device of claim 1, wherein, The epitaxial growth in steps 1 and 3 adopts one of MOCVD, HVPE and MBE; the removal of the blocking layer in step 5 adopts a wet removal technology; the plasma treatment in step 6 adopts hydrogen plasma; the growth of the medium layer in step 7 adopts ALD; and the growth of the passivation layer in step 9 adopts one of PECVD, LPCVD and ALD.

9. The method of fabricating an enhanced GaN HEMT device of claim 1, wherein, The material of the substrate comprises one or more of sapphire, Si, GaN, SiC, QST, SOI and diamond; The material of the nucleation layer is AlN; The material of the buffer layer is one or more of iron-doped or carbon-doped GaN and AlN / GaN superlattice structure; The material of the channel layer is GaN; The material of the barrier layer is Al x Ga 1-x N, x is 0.18-0.3; The material of the blocking layer is Si3N4 or SiO2; The material of the cap layer is p-GaN; The material of the source is one or more of Ti, Al, Ni, Au, TiN and Pt; The material of the drain is one or more of Ti, Al, Ni, Au, TiN and Pt; The material of the medium layer is AlN; The material of the gate is one or more of Ni, Au and TiN; The material of the passivation layer is SiO2 or Si3N4.

10. An enhanced GaN HEMT device, characterized by, The device is prepared according to the preparation method of the enhanced GaN HEMT device in any one of claims 1-9; the device comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer; a part of the upper surface of the barrier layer at the middle position is provided with an etching area, and a cap layer is grown in the etching area; ion implantation isolation areas are arranged on both sides of the barrier layer, both sides of the channel layer and part of the upper surface of the buffer layer; a source region and a drain region are arranged on the left side and the right side of the barrier layer, respectively, and a plasma treatment area is arranged in the source region and the drain region; a source electrode and a drain electrode are formed on the upper surface of the plasma treatment area; a dielectric layer is grown on the upper surface of the barrier layer, the source electrode and the drain electrode and the cap layer; a gate region is arranged on the upper surface of the dielectric layer and directly above the cap layer, and a gate electrode is formed in the gate region; a passivation layer is grown on the upper surface of the dielectric layer and the gate electrode; grooves are etched above the gate electrode, the source electrode and the drain electrode to expose the gate electrode, the source electrode and the drain electrode.

Images