Substrate-biased monolithic structure for transistors using two-dimensional electron gas

Abstract

A monolithic implementation of an integrated circuit including a power transistor and a biasing circuit for biasing a substrate of the power transistor is provided. For example, the integrated circuit includes a semiconductor substrate; and an epitaxial stack epitaxially grown on the semiconductor substrate. The power transistor uses a portion of an epitaxial stack including a portion of a channel semiconductor layer and a portion of a barrier semiconductor layer. Furthermore, the bias circuit includes circuit elements that use respective portions of the epitaxial stack, including respective portions of the channel semiconductor layer and a portion of the barrier semiconductor layer. The bias circuit is configured to bias a portion of the semiconductor substrate under the power transistor.

Description

Background Art

[0001] Electronic circuits often include transistors, which are devices used as electronic switches to regulate or control the flow of current in a portion of a circuit. One type of transistor is a field effect transistor, in which a voltage is applied to a gate terminal to turn the transistor on and off. A semiconductor channel region is disposed between a drain terminal and a source terminal. When the transistor is on, current flows through the semiconductor channel region between the source terminal and the drain terminal. When the transistor is off, less current or no current flows through the semiconductor channel region between the source terminal and the drain terminal. A gate terminal is disposed over the semiconductor channel region between the source terminal and the drain terminal. The voltage on the gate terminal creates a field that affects whether the semiconductor channel region conducts electricity, hence the name "field effect transistor."

[0002] Silicon is traditionally used to make transistors. However, wider bandgap semiconductor materials can be used to make transistors that conduct higher power and operate more efficiently than silicon transistors. Silicon carbide (SiC), aluminum nitride (AlN), zinc oxide (ZnO), and gallium arsenide (GaAs) are all examples of wide bandgap semiconductor materials that can be used in power electronics. One way to use such wider bandgap semiconductor materials is to form two layers of different semiconductor materials with a heterojunction between them.

[0003] The two semiconductor materials may have sufficiently different band gaps so that when brought together, the connected band gap drops below the Fermi level within the channel layer. This means that electrons can flow freely within this region. The depth of this region is thin and forms a plane parallel to the upper surface of the channel region. Therefore, this region is called a "two-dimensional electron gas" (or "2DEG") (emphasis on "two-dimensional") to emphasize its planar form. In addition, due to the high mobility of electrons in this region, this region is also called a "two-dimensional electron gas" (emphasis on "electron gas"). Therefore, 2DEG has high conductivity. 2DEG can form a channel region of a power semiconductor with relatively low resistance to allow large amounts of current to pass through.

[0004] An important characteristic of a transistor is the maximum current it allows when operating in saturation mode. This characteristic is called the saturation current (sometimes abbreviated "Idsat"). The higher the Idsat of a transistor, the more current it allows when operating in saturation mode. This can be particularly desirable in high voltage applications, because the transistor's ability to carry current at high voltages means the transistor can carry power more efficiently.

[0005] Transistors can experience leakage current, which is unwanted or undesirable current that flows when the transistor is off. Over time, leakage current can cause transistor performance to degrade. There are several potential paths for leakage current in a transistor. One example is so-called "substrate leakage" or "vertical leakage," which occurs when current flows through the substrate ground of the transistor at an inopportune time. Substrate leakage can be caused by defects in the substrate, imperfections in the material, or by excessive electric fields causing current to take unintended paths in the substrate.

[0006] The subject matter described herein is not limited to examples that solve any disadvantages or operate only in environments such as those described above. Rather, the background provided herein is merely to illustrate example technology areas in which some embodiments of the invention may be applied. Summary of the invention

[0007] This Summary is intended to introduce in a simplified form some concepts that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0008] Embodiments described herein relate to a monolithic implementation of an integrated circuit that includes a power transistor and a bias circuit for biasing a substrate of the power transistor. For example, the integrated circuit includes a semiconductor substrate; and an epitaxial stack that is epitaxially grown on the semiconductor substrate. The epitaxial stack includes a channel semiconductor layer; and a barrier semiconductor layer epitaxially grown on the channel semiconductor layer. The interface between the channel semiconductor layer and the barrier semiconductor layer induces a two-dimensional electron gas (2DEG) in the channel semiconductor layer. The power transistor uses a portion of the epitaxial stack, including a portion of the channel semiconductor layer and a portion of the barrier semiconductor layer. In addition, the bias circuit includes circuit elements that use corresponding portions of the epitaxial stack, including corresponding portions of the channel semiconductor layer and a portion of the barrier semiconductor layer. The bias circuit is configured to bias a portion of the semiconductor substrate below the power transistor.

[0009] In other words, the integrated circuit contains a four-terminal transistor, the terminals being 1) the source contact; 2) the drain contact; 3) the gate terminal; and 4) the substrate. This is in contrast to a three-terminal device which only includes a source contact, a drain contact, and a gate terminal. In previous transistor structures, the substrate is shorted to the source contact, so the substrate cannot be considered as another terminal. Using the substrate as the fourth terminal has many potential advantages.

[0010] For example, by biasing the substrate, the vertical electric field encountered by the transistor structure can be adjusted. For example, by weakening the vertical electric field, the power driving the vertical leakage is reduced, thereby reducing the vertical leakage itself, thereby preventing damage to the transistor structure, saving power, and extending the service life of the transistor structure. Alternatively or additionally, the weakening of the vertical electric field can reduce the thickness of the transistor structure.

[0011] Furthermore, controlling the substrate bias can control the thickness of the 2DEG. For example, by increasing the thickness of the 2DEG, the saturation current of the transistor structure can be increased, thereby delivering more power. Alternatively or additionally, this improved saturation current can allow the size of the transistor to be smaller. Reducing the size of the transistor means that more transistors can be manufactured on a single wafer. Furthermore, since the area of ​​the transistor is reduced, the chance of manufacturing defects is also reduced, so the yield may be increased accordingly. That is, it is possible to reduce the percentage of unusable or defective transistors on the wafer.

[0012] Additionally, as the transistor ages, the on-resistance of the transistor may increase, which can cause heating and possibly transistor failure. By controlling the thickness of the 2DEG as the transistor ages, the aging of the transistor structure can be counteracted by applying a bias that is used to readjust the on-resistance of the transistor downward.

[0013] Other features and advantages will be introduced in the following description, some of which will be obvious from the description or can be learned by practicing the teachings of the invention. The features and advantages of the invention can be realized and obtained by the instruments and combinations particularly pointed out in the appended claims. The features of the invention will be more obvious from the following description and the appended claims, or can be learned by practicing the invention described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to describe in detail how the above and other advantages and features are achieved, the subject matter briefly described above will now be described in more detail with reference to specific embodiments shown in the accompanying drawings. It should be understood that these drawings depict only typical embodiments and are therefore not to be considered limiting in scope. Additional specific and detailed description and explanation of the embodiments will be provided through the use of the accompanying drawings, in which:

[0015] Figure 1 is an illustration of an embodiment of a transistor structure according to principles described herein.

[0016] Figure 2 shows a transistor structure, which is Figure 1 A specific example of a transistor structure is shown.

[0017] Figure 3A , 3Band 3C respectively show the bias environment, where the drain of the power transistor generates a high voltage V H , the high voltage V H Can be used to bias the substrate of the power transistor.

[0018] Figure 4 An environment is shown in which Figures 3A to 3C Any of the circuits shown is used to generate a dynamically varying bias voltage V B , which is then applied to the substrate of the power transistor.

[0019] Figure 5 shows that it can be used to implement Figure 4 An example inverter circuit of an inverter circuit is shown.

[0020] Figure 6 Shown is a cross-sectional view of each of a transistor, a resistor, and a capacitor, all formed on the same silicon substrate on which the power transistor is formed.

[0021] Figure 7 A package including an integrated circuit is shown in which the power transistor and all bias circuits are formed monolithically (except for the capacitors).

[0022] Figure 8 A diagram is shown which illustrates the effect of biasing a semiconductor substrate on the performance of a transistor structure (eg Figure 1 The influence of leakage current of the semiconductor substrate of the transistor structure shown in FIG.

[0023] Fig. 9 A graph is shown illustrating the effect of biasing the semiconductor substrate on the current of a transistor structure when the transistor structure is operated successively in linear and saturation modes.

[0024] Fig.10 A package structure is shown in which a monolithically implemented die with substrate biasing can be packaged.

[0025] Fig.11 Another package structure that can package a die is shown.

[0026] Fig.12 Yet another package structure that can package a die is shown. DETAILED DESCRIPTION

[0027] Embodiments described herein relate to a monolithic implementation of an integrated circuit that includes a power transistor and a bias circuit for biasing a substrate of the power transistor. For example, the integrated circuit includes: a semiconductor substrate; and an epitaxial stack that is epitaxially grown on the semiconductor substrate. The epitaxial stack includes a channel semiconductor layer; and a barrier semiconductor layer epitaxially grown on the channel semiconductor layer. The interface between the channel semiconductor layer and the barrier semiconductor layer induces a two-dimensional electron gas (2DEG) in the channel semiconductor layer. The power transistor uses a portion of the epitaxial stack, including a portion of the channel semiconductor layer and a portion of the barrier semiconductor layer. In addition, the bias circuit includes circuit elements that use corresponding portions of the epitaxial stack, including corresponding portions of the channel semiconductor layer and a portion of the barrier semiconductor layer. The bias circuit is configured to bias a portion of the semiconductor substrate below the power transistor.

[0028] In other words, the integrated circuit contains a four-terminal transistor, the terminals being 1) the source contact; 2) the drain contact; 3) the gate terminal; and 4) the substrate. This is in contrast to a three-terminal device which only includes a source contact, a drain contact, and a gate terminal. In previous transistor structures, the substrate is shorted to the source contact, so the substrate cannot be considered as another terminal. Using the substrate as the fourth terminal has many potential advantages.

[0029] Figure 1 1 is a diagram of an embodiment of a transistor structure 100 according to the principles described herein. Transistor structure 100 is a simplified diagram used to illustrate the general principles of substrate biasing. Figure 2 A more specific example of .

[0030] The transistor structure 100 can be formed by epitaxially growing an epitaxial stack on a substrate. In this specification and claims, the growth direction of the epitaxial stack will be referred to as the "vertical" direction. Therefore, terms describing relative vertical positions (such as "under", "below", and "above", etc.) are relative to the vertical direction. For example, if a second layer is epitaxially grown on a first layer, the second layer will be "above" the first layer, and the first layer will be "below" the second layer.

[0031] Back to Figure 1 , the transistor structure 100 includes a semiconductor substrate 101, which constitutes a bottom layer on which additional layers are epitaxially grown to form a part of the transistor structure. The semiconductor substrate 101 can be any semiconductor including silicon. The layers epitaxially grown on top of the semiconductor substrate 101 are hereinafter referred to as an "epitaxial stack".

[0032] The epitaxial stack includes a channel semiconductor layer 102 epitaxially grown using a semiconductor substrate 101 as a bottom layer. The channel semiconductor layer 102 can be composed of any suitable semiconductor, including gallium nitride (GaN). The ellipsis 105 indicates that there can be any number of layers in the epitaxial stack between the semiconductor substrate 101 and the channel semiconductor layer 102. By way of example only, a stress relief layer can be formed between the semiconductor substrate and the channel semiconductor layer 102 to improve the mechanical stability and electrical performance of the transistor structure 100. However, the principles described herein are not limited to the layers (if any) between the semiconductor substrate 101 and the channel semiconductor layer 102. In short, the semiconductor substrate 101 is rigidly coupled to the channel semiconductor layer 102 to provide sufficient support for the channel semiconductor layer 102 and the rest of the epitaxial stack, in a sense that all epitaxial layers are coupled to the substrate on which they are grown.

[0033] The barrier semiconductor layer 103 is epitaxially grown on the channel semiconductor layer 102 so that the barrier semiconductor layer 103 is located directly above the channel semiconductor layer 102. There is a heterojunction interface between the channel semiconductor layer 102 and the barrier semiconductor layer 103. The barrier semiconductor layer 103 can be composed of any suitable semiconductor, such as aluminum gallium nitride (AlGaN). The difference in band gap distribution between the channel semiconductor layer 102 (e.g., GaN) and the barrier semiconductor layer 103 (e.g., AlGaN) causes the conduction band edge of the channel semiconductor to be pulled downward near the heterojunction interface, thereby forming an energy potential well in the channel semiconductor layer 102 that vertically drops below the Fermi level. Since the well is below the Fermi level, there are free electrons in the well, forming a highly conductive two-dimensional electron gas ("2DEG") 110.

[0034] The vertical thickness of this region where free electrons exist corresponds to the short vertical span of the well that drops below the Fermi level. Therefore, the 2DEG is thin in the vertical direction. However, the region is flat in the horizontal plane. Therefore, this region is called a "two-dimensional" electron gas to emphasize its planar form. The mention of "electron gas" in this term is to emphasize that the electrons in the 2DEG have high mobility. 2DEG is also called "electron sea", which also emphasizes the mobility of electrons in 2DEG. 2DEG can form the channel region of power semiconductors to allow high current to pass with relatively low resistance. Therefore, 2DEG is indispensable in high-frequency and high-power electronics and can be used in devices such as high electron mobility transistors (HEMTs).

[0035] The source contact 111 is in conductive contact with the 2DEG 110, which means that electrons can flow freely between the source contact 111 and the 2DEG 110 (see the leftmost portion of the 2DEG 110, as shown in FIG. Figure 1This may be because the source contact 111 is in direct contact with the 2DEG 110 (as shown in FIG. Figure 1 110), but may not be in direct contact, but close enough that electrons may still flow between the source contact 111 and the 2DEG 110. Similarly, the drain contact 112 is also in conductive contact with the 2DEG 110 (see the rightmost portion of the 2DEG 110, as shown). Figure 1 If the 2DEG 110 is continuous between the source contact 111 and the drain contact 112 , the 2DEG 110 functions as a channel through which electrons can flow between the source contact 111 and the drain contact 112 .

[0036] The gate terminal 113 is close to the 2DEG 110 so that the voltages applied to the gate terminal 113 (or more specifically, the electric fields caused by these voltages) control whether the 2DEG 110 is continuous between the source contact 111 and the drain contact 112. When the gate terminal 113 is disconnected, the 2DEG 110 is discontinuous under the gate terminal 113; when the gate terminal 113 is turned on, the 2DEG 110 is continuous under the gate terminal 113. If the transistor structure 100 is an enhancement-type transistor, then when no voltage is applied to the gate terminal 113, the transistor structure 100 is turned off, and when a sufficient positive voltage is applied to the gate terminal 113, the transistor structure 100 is turned on. If the transistor structure 100 is a depletion-type transistor, then when no voltage is applied to the gate terminal 113, the transistor structure 100 is turned on, and when a sufficient negative voltage is applied to the gate terminal 113, the transistor structure 100 is turned off.

[0037] Thus, by controlling the continuity of the 2DEG 110 between the source contact 111 and the drain contact 112, the voltage applied to the gate terminal 113 controls whether the transistor represented by the transistor structure 100 is turned on or off. In this specification, all transistors that use a 2DEG to pass current are referred to as "high electron mobility transistors" or "HEMTs". Thus, Figure 1 A transistor structure 100 including a HEMT is shown. A conventional HEMT is a three terminal device, the three terminals being a source contact, a drain contact and a gate terminal.

[0038] According to the principles described herein, a four-terminal HEMT is described. That is, the semiconductor substrate 101 is a fourth terminal that is disconnected or at least can be disconnected from the source contact 111. That is, the voltage applied to the semiconductor substrate 101 (referred to herein as the "bias voltage" or "bias") may be different from the voltage applied to the source contact 111. To this end, the substrate contact 121 is located below the substrate 101 and can be electrically disconnected from the source contact 111. This will allow the bias circuit 120 to apply a bias to the semiconductor substrate 101 through the substrate contact 121 that is independent of the voltage present on the source contact 111. Electrically disconnecting the substrate contact 121 from the source contact 111 can achieve the advantages described herein related to biasing the semiconductor substrate 101.

[0039] For example, by biasing the substrate 101, the vertical electric field encountered by the transistor structure 100 can be adjusted. For example, by weakening the vertical electric field, the power driving the vertical leakage is reduced, thereby reducing the vertical leakage itself, thereby preventing damage to the transistor structure 100, saving power, and extending the service life of the transistor structure 100. Alternatively or additionally, the weakening of the vertical electric field can reduce the thickness of the transistor structure.

[0040] Alternatively, the bias voltage can be adjusted to compensate for the higher drain voltage. Such a high drain voltage generally indicates that the vertical electric field will increase in proportion to the increase in the drain voltage. However, by controlling the bias voltage to be higher to compensate for the higher drain voltage, the size of the vertical electric field can be controlled so that the transistor structure 100 can be a device with a higher voltage. Even if the same transistor structure 100 is used, different voltage application requirements can be met by appropriately controlling the substrate bias voltage. If the transistor structure 100 can withstand a drain voltage of 400 volts when a substrate bias voltage of 200 volts is applied, then the same transistor structure 100 may be able to withstand a drain voltage of 1000 volts when a substrate bias voltage of 800 volts is applied.

[0041] In addition, controlling the substrate bias can also control the charge of the 2DEG 110. For example, by increasing the charge of the 2DEG, the saturation current of the transistor structure can be increased, thereby transmitting more power. Alternatively or additionally, this improved saturation current can make the size of the transistor smaller. Reducing the size of the transistor means that more transistors can be manufactured on a single wafer. In addition, since the area of ​​the transistor is reduced, the chance of manufacturing defects is also reduced, so the yield may be increased accordingly. That is, it is possible to reduce the percentage of unusable or defective transistors on the wafer.

[0042] Furthermore, controlling the substrate bias can improve both the dynamic and static on-resistance of the transistor.Finally, the electrical decoupling between the source contact 111 and the substrate 101 may allow for more use of the transistor structure 100 that would otherwise be prohibited due to the electrical connection between the source contact 111 and the substrate 101.

[0043] To bias the substrate 101, the bias circuit 120 is in conductive contact with the substrate contact 121 and is configured to apply a bias voltage to the semiconductor substrate 101. The bias circuit 120 can be configured to apply a fixed or variable bias to the substrate, and the bias can be positive relative to the source contact 111. The bias circuit 120 can also be configured to selectively apply a bias voltage to the semiconductor substrate 101 depending on the state of the transistor structure 100.

[0044] The bias circuit 120 may include any number of circuits configured to apply a bias to the semiconductor substrate 101. The bias circuit 120 may be epitaxially grown using the same epitaxial stack used to form the barrier semiconductor layer 103 and the channel semiconductor layer 102. This configuration may be referred to as a monolithic implementation of substrate bias. Alternatively, the bias circuit 120 may be provided separately from the epitaxial stack and may be different from each other. Such a configuration may be referred to as a co-packaged implementation of the bias circuit, because the bias circuit in this embodiment is co-packaged with the epitaxial stack to implement biasing of the semiconductor substrate 101.

[0045] Figure 2 A transistor structure 200 is shown. The transistor structure is Figure 1 A specific example of the transistor structure 100 is shown. The P-type (111) substrate 201 is Figure 1 An example of the substrate 101 is shown, and the GaN epitaxial layer 202 is Figure 1 An example of the channel layer 102 is shown, the AlGaN layer 203 is Figure 1 An example of the barrier layer 103 is shown. In addition, the source contact structure 211 (to which the voltage Vsource is applied) is Figure 1 The example of the source contact 111 shown, the drain contact structure 212 (with voltage Vdrain applied) is Figure 1 The example of drain contact 112 shown, gate structure 213 (with voltage Vgate applied) is Figure 1 The example of gate terminal 113 shown, substrate contact 221 (to which voltage Vsub is applied) is Figure 1An example of a substrate contact 121 is shown. The gate structure 223 includes a p-doped GaN layer 231, which causes the 2DEG to be discontinuous under the gate when no voltage is applied to the conductive gate 232, thereby causing the transistor structure 200 to be an enhancement mode transistor. Therefore, four different voltages can be applied to four different terminals of the transistor structure 200, as represented by the voltages Vsource, Vdrain, Vgate, and Vsub. Therefore, the transistor structure 200 is a four-terminal HEMT. A field plate structure 230 (including field plates FP1, FP2, FP3, and FP4) is also shown for managing the electric field distribution in the 2DEG.

[0046] Figure 3A , 3B 3 and 3C respectively show bias environments 300A, 300B and 300C, wherein the drain of the power transistor 301 generates a high voltage V H , the high voltage V H can be used to bias the substrate of the power transistor 301. The power transistor 301 is composed of Figure 1 The transistor structure 100 or Figure 2 The transistor structure 200 shown forms one example of a transistor.

[0047] For example, Figure 3A The bias environment 300A shown includes a circuit 310A that utilizes the drain of the power transistor 301 to generate a high voltage V H ; Figure 3B The bias environment 300B shown includes a circuit 310B that utilizes the drain of the power transistor 301 to generate a high voltage V H ; Figure 3C The bias environment 300C shown includes a circuit 310C that utilizes the drain of the power transistor 301 to generate a high voltage V H . Therefore, in each case, the high voltage V H All are generated from the drain of the power transistor 301 .

[0048] For example, when the power transistor 301 is turned off, the high voltage V H It can be a small fraction (e.g., one-half) of the drain voltage present on the drain terminal of the power transistor 301. For example, if the drain off voltage is 400 volts, the high voltage V H It may be a small fraction of the drain voltage (e.g., 200 volts). Although this value may be any small fraction, the high voltage V H Preferably, it is at least 10% of the drain cut-off voltage of the power transistor 301. For example, if the drain cut-off voltage is 400 volts, the high voltage V H Preferably at least 40 volts.

[0049] Circuits 310A, 310B, and 310C may be collectively referred to as “circuit 310 ,” or any one of the circuits may be simply referred to as “circuit 310 .” Any one of circuits 310 may be used to generate a high voltage V from the drain voltage of power transistor 301 . H Each circuit 310 includes a drain of a power transistor 301 connected in series to a high voltage V H A rectifier, a capacitor to ground and a voltage divider at the output end.

[0050] For example, the circuit 310A includes a drain of the power transistor 301 connected in series to a high voltage V H 310A, a grounded capacitor 312A, and a voltage divider 313A are provided at the output end of the circuit 310B. However, to emphasize that the placement of the voltage divider is flexible, the circuit 310B first includes the rectifier 311B, the voltage divider 313B, and the grounded capacitor 312B connected in series in sequence. In addition, the circuit 310C first includes the voltage divider 313C, then the rectifier 311C, and then the grounded capacitor 312C.

[0051] Rectifiers 311A, 311B, and 311C (collectively, "rectifiers 311") may be any circuit element that outputs a rectified version of its input voltage. As an example, rectifiers 311 may each be a diode. For example, voltage dividers 313A, 313B, and 313C (collectively, "voltage divider 313") may be resistors connected in series between the voltage divider input and ground, where the output of the voltage divider is one of the intermediate nodes between the resistors. Alternatively, voltage dividers 313A, 313B, and 313C may be, for example, capacitors connected in series between the voltage divider input and ground, where the output of the voltage divider is one of the intermediate nodes between the capacitors.

[0052] When the power transistor 301 is turned off, the drain voltage of the power transistor 301 is high, thereby causing charge to flow through the rectifiers 311A, 311B and 311C (at Figures 3A to 3C In the case of rectifier 311A, the charge is directly supplied to the upper end of capacitor 312A, replenishing the charge on capacitor 312A, thereby stabilizing the voltage across capacitor 312A at a high level. The high voltage is then supplied to voltage divider 313A, which then outputs another high voltage V H , the high voltage V H is a fraction of the voltage across capacitor 312A. In the case of rectifier 311B, the charge is indirectly supplied to the upper end of capacitor 312B through voltage divider 313B, thereby replenishing the charge on capacitor 312B to be at high voltage V HIn the case of rectifier 311C, rectifier 311C indirectly receives the charge from the drain of power transistor 301 through voltage divider 313C and transfers the charge to capacitor 312C to charge it at high voltage V H .

[0053] When power transistor 301 is turned on, the drain voltage of power transistor 301 is relatively low, so rectifiers 311 are each reverse biased, allowing capacitors 312A, 312B, and 312C (collectively referred to as "capacitors 312") to retain their charge. H Biasing the substrate contacts of the transistor structure (e.g. Figure 1 The substrate contact 121 of the transistor structure 100 is shown biased, or Figure 2 The substrate contact 221 of the transistor structure 200 shown is biased) to draw current at a lower rate. However, the size of each capacitor 312 is large enough that the capacitor can still substantially maintain its voltage even when a small amount of current biases the substrate.

[0054] In one embodiment, the high voltage V H Directly applied to the substrate contacts (e.g. Figure 1 The substrate contacts 121 shown, or Figure 2 The substrate contact 221 shown in FIG. 2 is a substrate contact 221. In this case, the bias voltage applied to the substrate is a relatively constant positive bias voltage, provided that the capacitor of the circuit 300 is large enough. This is because the amount of current drawn from the circuit 300 is not large, because the drawn current is only used to charge the substrate contact to a sufficient voltage. Therefore, the circuit 300 generates a high voltage V H , but uses only the right amount of current to achieve this. H When applied to the substrate, it may be advantageous to provide some degree of carbon doping in the epitaxial stack, particularly in the GaN channel layer and the AlGaN barrier layer. This may reduce leakage when the transistor is off, but substrate bias is still applied.

[0055] In another embodiment, the high voltage V H For applying a dynamic voltage to the substrate. For example, a positive bias voltage may be selectively applied depending on the state of the transistor structure (eg, whether the transistor is on or off), or the bias may be varied depending on the state of the transistor structure. Figure 4 An environment 400 is shown, wherein Figures 3A to 3C Any of the circuits shown is used to generate a dynamically varying bias voltage V B , which is then applied to the substrate of the power transistor 301.

[0056] For example, environment 400 includes power transistor 301, circuit 310, and bias circuit 410. As previously described, circuit 310 generates a high voltage V from power applied to the drain of power transistor 301. H The combination of circuit 310 and bias circuit 410 is Figure 1 An example of a bias circuit 120 is shown. Figure 4 In the specific example shown, bias circuit 410 includes inverter circuit 411 , transistor 412 , and resistor 413 .

[0057] As an example, the inverter circuit 411 can be an inverter. In any case, when the input terminal level of the inverter circuit 411 is low, the inverter circuit outputs a high signal, and when the input terminal level is high, the inverter circuit outputs a low signal. The inverter circuit 411 has an input terminal connected to the gate terminal of the power transistor 301 and an output terminal connected to the gate terminal of the transistor 412. Therefore, if a high signal is applied to the gate terminal of the power transistor 301, a low signal is applied to the gate terminal of the transistor 412, and vice versa.

[0058] As described above, when a high signal is applied to the gate terminal of the power transistor 301, a low signal is applied to the gate terminal of the other transistor 412, which causes the transistor 412 to turn off. Therefore, even if the drain terminal of the transistor 412 and the high voltage V H There is a resistor 413 between them, through which little or no current flows, so the drain terminal of transistor 412 still substantially bears the high voltage V H Therefore, when the power transistor 301 is turned on, the high voltage V H As the bias voltage V B , so that the substrate of the power transistor 301 is biased. Figure 1 In the embodiment of the present invention, when the 2DEG 110 conducts current from the drain contact 112 to the source contact 111, the bias circuit 120 biases the substrate 101 with a bias voltage. In this specification, an example is often mentioned in which the bias voltage is 200 volts. However, the bias voltage can also be any voltage of at least 40 volts. In other words, any positive bias will reduce vertical leakage. Therefore, the principles described herein are not limited to the exact value of the bias voltage.

[0059] On the other hand, see again Figure 4, when a low signal is applied to the gate terminal of the power transistor 301, a high signal is applied to the gate terminal of another transistor 412, which causes the transistor 412 to turn on. In this state, because the resistor 413 has a high resistance compared to the on-resistance of the transistor 412, the voltage at the drain terminal of the transistor 412 becomes quite low (maybe around a few volts). Therefore, when the power transistor 301 is turned off, a negligible bias voltage is applied to the substrate of the power transistor 301. For example, in Figure 1 In the bias voltage V B The bias circuit 120 biases the substrate 101 with no or negligible bias voltage (e.g., a few volts) when the 2DEG 110 does not conduct current from the drain contact 112 to the source contact 111. At least in this way, the bias circuit 410 selectively applies a positive bias voltage depending on the state of the power transistor 401. Therefore, the bias voltage can be varied to enable the power transistor to reduce leakage current.

[0060] Figure 5 shows that it can be used to implement Figure 4 The example inverter circuit 500 of the inverter circuit 411 shown in FIG. 4 is a schematic diagram of an inverter circuit 500. Of course, there are many ways to implement an inverter, and this is just one of them. The inverter circuit 500 includes a transistor 501, a diode 502, a capacitor 503, and a resistor 504. The input terminal 511 of the inverter circuit 500 is connected to the gate of the power transistor 301 (eg, Figure 4 ). Therefore, the on / off pulse driving the gate of the power transistor 301 is also applied to the input terminal 511 of the inverter circuit 500. Due to the action of the diode 502, the capacitor 503 is charged to a voltage close to the on-state voltage applied to the gate of the power transistor 301. Therefore, the capacitor 503 can be charged to about 5 volts.

[0061] When a high voltage is applied to the gate of the power transistor 301 (and the input terminal 511 of the inverter circuit 500), a high voltage is also applied to the gate of the transistor 501, thereby turning on the transistor 501. Since the resistor 504 controls the on-resistance of the transistor 501, the output terminal 512 of the inverter circuit 500 is at a low level. Therefore, when a high voltage (e.g., 5 or 6 volts) is applied to the input terminal 511 of the inverter circuit 500, the inverter circuit applies a low voltage (e.g., substantially ground) to the output terminal 512 of the inverter circuit.

[0062] On the other hand, when a low voltage is applied to the gate of the power transistor 301 (and the input 511 of the inverter circuit 500), a low voltage is also applied to the gate of the transistor 501, thereby turning off the transistor 501. Since little or no current will pass through the resistor 504, the output 512 of the inverter circuit 500 will assume nearly the same voltage stored on the capacitor 503, which is relatively high, about 5 to 6 volts. Therefore, when the input 511 of the inverter circuit 500 is low, the output 512 of the inverter circuit 500 is high.

[0063] The exact design of the inverter circuit 500 is not important. What is emphasized about the inverter circuit 500 is that the inverter circuit contains only four types of components: 1) transistors; 2) resistors; 3) capacitors; and 4) diodes. Figure 4 In addition to the inverter circuit 411 (of which the inverter circuit 500 is an example), the bias circuit 410 is also composed of only components selected from these four types of components. FIG. 3A to FIG. 3C In the circuit 310, any one of the circuits 310 is also composed of components selected from these four types of components (it should be noted that the voltage divider 313 can be composed of resistors in series or capacitors in series). Therefore, Figure 1 The bias circuit 120 is shown as being constructed from four types of components: 1) transistors; 2) resistors; 3) capacitors; and 4) diodes.

[0064] However, a diode can be constructed using transistors by connecting the gate and source of the transistor. Figure 1 The bias circuit 120 shown can be constructed from as few as three types of components, including: 1) transistors; 2) resistors; and 3) capacitors. Finally, the capacitor can be implemented using a high voltage transistor connected in a diode configuration (with its gate and source connected), where the drain-source parasitic capacitance acts as a capacitor. In this case, Figure 1 The bias circuit 120 shown may be constructed from as few as two components, including: 1) a transistor; and 2) a resistor.

[0065] Figure 6A cross-sectional view 600 of each of a transistor 611, a resistor 612, and a capacitor 613, all formed on the same silicon substrate 620 on which a power transistor 601 is formed, is shown. In addition, the power transistor 601, the transistor 611, and the resistor 612 are each composed of portions of the same epitaxial stack. Specifically, the power transistor 601, the transistor 611, and the resistor 612 are each structured using a common channel layer 621. Further, the power transistor 601 includes a portion 622A of the barrier semiconductor layer 622, the transistor 611 includes another portion 622B of the barrier semiconductor layer 622, and the resistor 612 includes another portion 622C of the barrier semiconductor layer 622.

[0066] Power transistor 601 uses Figure 2 The transistor structure 200 shown is of substantially the same form. The 2DEG is represented by a horizontal dashed line, which is discontinuous under the gate of the power transistor 601, but its selective continuity can be controlled by applying a voltage to the gate of the power transistor 601. Similarly, transistor 611 (which is a low voltage transistor) also uses a 2DEG formed by the same heterojunction, where the continuity of the 2DEG under the gate can be controlled by applying an appropriate voltage to the gate. Resistor 612 takes a similar form to transistors 601 and 602, except that there is no gate structure at all, so the 2DEG is always continuous between the two terminals of the resistor. Capacitor 613 can be formed by two metal layers 631 and 632 separated by an insulator layer. Alternatively, the capacitor can also be implemented using a high voltage transistor, which has a smaller channel width perpendicular to the direction of current flow than the power transistor 601.

[0067] Thus, by forming instances of transistor 611 and resistor 612 in the same epitaxial stack as power transistor 611, and forming capacitor 613 using metal-insulator-metal (MIM) technology (or utilizing the drain-source parasitic capacitance of the high voltage transistor to form a capacitor), and by forming e.g. FIG. 3A to FIG. 3C as well as Figure 4 and Figure 5 With appropriate connections shown, the bias circuit 120 may be formed monolithically with the transistor structure 100 .

[0068] In one embodiment, one or more capacitors may be formed off-chip but still be packaged in the same package as the bias circuitry and other components of the power transistor. Figure 7 A package 700 is shown including an integrated circuit 710 (eg, a chip) in which the power transistors and all bias circuits are monolithically formed (except for the capacitors). Figure 7In the embodiment of the present invention, capacitor 720 is a discrete component located off-chip, but co-packaged with the integrated circuit. Alternatively, the capacitor can even be formed monolithically with the rest of the power transistor and bias circuit.

[0069] The monolithic construction of the bias circuit and the power transistor allows for a more streamlined manufacturing process for implementing substrate bias. Because the components used in the implementation of the bias circuit 120 may be relatively small compared to the power transistor, the implementation size of the bias circuit 120 may be small compared to the power transistor 301. Therefore, the implementation of the bias circuit 310 may only slightly (if at all) affect the die area in the monolithic implementation of the embodiments described herein. Die area plays a vital role in determining manufacturing costs because the die area directly affects the number of chips that can be produced on a single wafer. Typically, a smaller die size can increase the chip yield per wafer, thereby reducing the production cost per unit. In some implementations, a monolithic implementation of substrate bias may have only very low die defects.

[0070] Figure 8 A diagram 800 is shown that illustrates the effect of biasing a semiconductor substrate on the performance of a transistor structure (eg, Figure 1 800). In FIG800, line 801 shows the absolute value of the leakage current at different drain voltage levels without any semiconductor substrate bias. Line 802 shows the absolute value of the leakage current at different drain voltage levels with a 200 volt semiconductor substrate bias. In both cases, the voltage between the gate and the source is zero. Figure 8 As shown by arrow 810 in FIG. 1 , the leakage current is approximately offset by the bias amount. In other words, for a given drain voltage, the transistor structure 100 experiences less leakage current when the semiconductor substrate is biased than when there is no semiconductor substrate bias. In other words, by adjusting the substrate bias voltage, the same leakage current can be encountered at different gate voltages.

[0071] like Figure 8 As shown, the leakage current reduction may help to improve the yield of the manufacturing process, for example, by achieving thinner GaN layers. Figure 1 The transistor structure 100 shown may include a GaN layer epitaxially grown on a silicon layer, which may be cost effective. For example, the GaN layer may be similar to Figure 1 The channel semiconductor layer 102 shown. The epitaxial growth of the GaN layer may be limited by the strength of the silicon support layer. If the GaN layer is too thick, the strength of the silicon layer may not be sufficient to provide support for the GaN layer. As a result, the GaN layer may be deformed and therefore cannot work as a transistor structure. Figure 8As shown, the reduction in leakage current may allow the GaN layer to be thinner due to substrate bias. Manufacturing defects caused by too thick a GaN layer may be reduced, thereby improving the yield of the manufacturing process. Therefore, the transistor structure 100 can improve the yield of the manufacturing process by making the GaN layer thinner.

[0072] Fig. 9 A graph 900 is shown which illustrates the effect of biasing the semiconductor substrate on the current of a transistor structure when the transistor structure is operated successively in linear and saturation modes. Such a transistor structure may be, for example, Figure 1 The transistor structure 100 is shown. A common use of the transistor structure 100 may be continuous use, which may include operating the transistor structure 100 for a long time. For example, the transistor structure 100 may be operated continuously for hours, days, or weeks. When current flows between the source contact 111 and the drain contact 112, the transistor structure 100 may be in operation. In addition, when the output current increases linearly with the applied voltage, the transistor structure 100 may be considered to be in a linear mode (e.g., Fig. 9 When the output current increases little (if any) with the applied voltage, the transistor structure 100 can be considered to be in saturation mode (e.g., Fig. 9 In this mode, the output current may also be referred to as the saturation current of the transistor structure 100.

[0073] Saturation current can be an important characteristic of a transistor. The higher the saturation current of a transistor, the more power the transistor can deliver when operating in saturation mode. Additionally, the higher the saturation current, the more current it can drive at a given voltage, and therefore the more efficient the transistor can be at delivering power. Therefore, for any given transistor, it may be desirable to achieve a higher saturation current, as doing so can increase the power delivery efficiency of the transistor and the power delivery capability of the transistor.

[0074] Back to Fig. 9 , Fig. 9 A graph 900 is included, which includes lines 901 and 902. Line 901 shows the current at different voltages, where the semiconductor substrate 101 of the transistor structure 100 is not biased, but is maintained at the same voltage as the source contact. Line 902 shows the current when the semiconductor substrate 101 is biased to a varying voltage of 200V. As shown by arrow 910, when the transistor structure 100 is continuously operated in the saturation region, biasing the semiconductor substrate 101 can significantly increase the saturation current. In addition, as shown by the slope of the linear region of the IV curve, the substrate bias increases the on-resistance of the transistor.

[0075] like Fig. 9As shown, the embodiments described herein can achieve a higher saturation current when the semiconductor substrate is biased than when the semiconductor substrate is not biased. This shows that, for a given voltage, the semiconductor substrate bias may enable the transistor structure to deliver more current than a transistor structure that does not use the semiconductor substrate bias. Therefore, the embodiments described herein can achieve a higher saturation current, thereby improving the power transfer efficiency of the transistor structure 100 and the power transfer capability of the transistor structure 100.

[0076] Therefore, such as Figure 1 A transistor structure such as the illustrated transistor structure 100 may provide many benefits, including higher saturation current, smaller transistor structure size, and higher manufacturing process yield.

[0077] Now, several packaging structures and techniques will be introduced when the substrate bias is a monolithic structure (on the same die) with the power transistor. Fig.10 A PSOP package 1000 is shown. Fig.11 A TOLL package 1100 is shown, Fig.12 A PQFN package 1200 is shown. In each case, the package includes a die 1001 in which power transistors and bias circuits are implemented (although the die is Fig.12 not described in the ).

[0078] Fig.10 A PSOP package 1000 is shown that includes a bare die 1001. The bare die 1001 is mounted on a conductive base 1010 that represents a portion of a lead frame of the PSOP package 1000. The bare die 1001 includes a source contact 1011 that is wire bonded to a source sense terminal 1021(1) of the lead frame and to a source terminal 1021(2) of the lead frame. The bare die 1001 also includes a drain contact 1012 that is wire bonded to a drain terminal 1022 of the lead frame. The bare die 1001 also includes a gate contact 1013 that is wire bonded to a gate terminal 1123 of the lead frame.

[0079] The die 1001 also includes a substrate bias contact 1014, on which a substrate bias voltage is applied by a bias circuit inside the die 1001. Fig.10 1001, substrate biasing is accomplished by leads 1020 connecting substrate biasing contacts 1014 to conductive pedestals 1010, which are also conductively connected to the substrate of die 1001. In an alternative embodiment, substrate biasing is applied to conductive pedestals 1010 through conductive vias formed in die 1001 itself.

[0080] Fig.11A TOLL package is shown encapsulating a die 1001. The die 1001 is mounted on a conductive base 1110 of a lead frame of the TOLL package. A source contact 1011 of the die 1001 is wire bonded to a source sense terminal 1121(1) of the lead frame and is simultaneously wire bonded to a source terminal 1121(2) of the lead frame. A drain contact 1012 is wire bonded to a drain terminal 1122 of the lead frame. A gate contact 1013 is wire bonded to a gate terminal 1123 of the lead frame. A substrate bias voltage may be applied to the conductive base 1110 via a wire connected to a substrate bias pad 1014, or alternatively applied vias formed in the die 1001 itself. Fig.11 The TOLL package shown has been modified so that the source contact 1121 ( 2 ) is electrically disconnected from the conductive base 1110 , whereas in a conventional Toll package, the source contact and the conductive base are integral.

[0081] Substrate biasing can also be performed using PQFN packages. Fig.12 A conventional PQFN package 1200 is shown, which can be modified to include a die 1001. Pins 1201 and 1202 are not used in conventional applications. However, in this embodiment, pins 1201 and 1202 can be used as source pins, pin 1203 as a gate pin, pin 1204 as a source sense pin, pin 1205 as a drain pin, and plate 1206 as a substrate contact plate.

[0082] Literal support part

[0083] Item 1. An integrated circuit comprising: a semiconductor substrate; an epitaxial stack epitaxially grown on the semiconductor substrate, the epitaxial stack comprising a channel semiconductor layer and a barrier semiconductor layer epitaxially grown on the channel semiconductor layer; an interface between the channel semiconductor layer and the barrier semiconductor layer for inducing a two-dimensional electron gas (2DEG) in the channel semiconductor layer; a power transistor, the power transistor using a portion of the epitaxial stack, including a portion of the channel semiconductor layer and a portion of the barrier semiconductor layer; and a bias circuit, the bias circuit comprising a plurality of circuit elements, each of at least some of the plurality of circuit elements using a corresponding portion of the epitaxial stack, including: a corresponding portion of the channel semiconductor layer and a portion of the barrier semiconductor layer, the bias circuit being configured to bias a portion of the semiconductor substrate beneath the power transistor.

[0084] Clause 2. The integrated circuit of clause 1, wherein the semiconductor substrate is a silicon substrate.

[0085] Item 3. The integrated circuit of Item 1, wherein the barrier semiconductor layer is an AlGaN layer, and the channel semiconductor layer is a GaN layer.

[0086] Item 4. The integrated circuit of Item 1, wherein the bias circuit comprises: a transistor having a drain connected to the substrate contact layer, a gate coupled to an inverter circuit, and a source connected to ground.

[0087] Item 5. The integrated circuit according to Item 1 further includes: a source contact, the source contact being in conductive contact with the 2DEG; a drain contact, the gate terminal being in conductive contact with the 2DEG; a gate terminal, the gate terminal being close to the 2DEG so that a voltage applied to the gate terminal controls whether the 2DEG is continuous between the source contact and the drain contact; a substrate contact layer, the substrate contact layer being disposed directly below the semiconductor substrate, the substrate contact layer being electrically disconnected from the source contact so that a voltage different from that of the source contact is applied to the substrate contact layer; and the bias circuit being configured to bias the portion of the semiconductor substrate below the power transistor by applying a substrate bias voltage to the substrate contact layer.

[0088] Item 6. The integrated circuit of Item 5, wherein the bias circuit is configured to bias the semiconductor substrate by applying a positive bias voltage to the substrate contact layer, the positive bias voltage being positive relative to a source voltage applied to the source terminal.

[0089] Item 7. The integrated circuit of Item 6, wherein the positive bias voltage is a fixed positive voltage relative to the source voltage.

[0090] Clause 8. The integrated circuit of Clause 6, wherein the positive bias voltage is selectively applied based on a state of the transistor structure.

[0091] Clause 9. The integrated circuit of clause 6, wherein the positive bias voltage varies depending on a state of the transistor structure.

[0092] Clause 10. The integrated circuit of Clause 6, wherein the bias circuit is configured such that a maximum voltage of the positive bias voltage to the semiconductor substrate exceeds 100 volts.

[0093] Clause 11. The integrated circuit of Clause 5, wherein the bias circuit is further configured to bias the semiconductor substrate contact layer, the bias circuit being connected to the semiconductor substrate contact layer via a lead.

[0094] Clause 12. The integrated circuit of Clause 5, wherein the bias circuit is further configured to bias the substrate contact layer, the bias circuit being connected to the substrate contact layer through a via that passes through a die of the integrated circuit to reach the substrate contact layer.

[0095] Clause 13. The integrated circuit of Clause 1, wherein the integrated circuit is contained in a package.

[0096] Clause 14. The integrated circuit of Clause 13, wherein the package is a PSOP package.

[0097] Clause 15. The integrated circuit of Clause 13, wherein the package is a TOLL package.

[0098] Clause 16. The integrated circuit of Clause 13, wherein the package is a PQFN package.

[0099] Item 17. An integrated circuit package, the integrated circuit package comprising an integrated circuit, the integrated circuit comprising: a semiconductor substrate; an epitaxial stack, the epitaxial stack epitaxially grown on the semiconductor substrate, the epitaxial stack comprising a channel semiconductor layer and a barrier semiconductor layer epitaxially grown on the channel semiconductor layer; an interface between the channel semiconductor layer and the barrier semiconductor layer, for inducing a two-dimensional electron gas (2DEG) in the channel semiconductor layer; a power transistor, the power transistor using a portion of the epitaxial stack, including a portion of the channel semiconductor layer and a portion of the barrier semiconductor layer; and a bias circuit, the bias circuit comprising a plurality of circuit elements, each of at least some of the plurality of circuit elements using a corresponding portion of the epitaxial stack, including: a corresponding portion of the channel semiconductor layer and a portion of the barrier semiconductor layer, the bias circuit being configured to bias a portion of the semiconductor substrate beneath the power transistor.

[0100] Clause 18. The integrated circuit of Clause 16, wherein the integrated circuit package is a PSOP package.

[0101] Clause 19. The integrated circuit of Clause 16, wherein the integrated circuit package is a TOLL package.

[0102] Clause 20. The integrated circuit of Clause 16, wherein the integrated circuit package is a PQFN package.

[0103] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the features or acts described above, or to the order of acts described above. Rather, the described features and acts are disclosed as example forms of implementing the claims.

[0104] Without departing from its essential features, the present disclosure may be embodied in other specific forms. The described embodiments are to be considered in all respects as illustrative and non-restrictive. All changes that fall within the equivalent meaning and scope of the claims should be included within their scope.

[0105] When introducing elements in the appended claims, articles such as “a,” “an,” “the,” and “said” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements.

Claims

1. An integrated circuit, comprising: Semiconductor substrate; An epitaxial stack, wherein the epitaxial stack is epitaxially grown on the semiconductor substrate, and the epitaxial stack includes a channel semiconductor layer and a barrier semiconductor layer epitaxially grown on the channel semiconductor layer; an interface between the channel semiconductor layer and the barrier semiconductor layer, for inducing a two-dimensional electron gas (2DEG) in the channel semiconductor layer; a power transistor using a portion of the epitaxial stack, including a portion of the channel semiconductor layer and a portion of the barrier semiconductor layer; and A bias circuit, the bias circuit comprising a plurality of circuit elements, each of at least some of the plurality of circuit elements using a corresponding portion of the epitaxial stack, including: a corresponding portion of the channel semiconductor layer and a portion of the barrier semiconductor layer, the bias circuit being configured to bias a portion of the semiconductor substrate beneath the power transistor.

2. The integrated circuit according to claim 1, wherein: The semiconductor substrate is a silicon substrate.

3. The integrated circuit according to claim 1, wherein: The barrier semiconductor layer is an AlGaN layer, and the channel semiconductor layer is a GaN layer.

4. The integrated circuit according to claim 1, wherein: The bias circuit comprises: A transistor, a drain of the transistor is connected to the substrate contact layer, a gate of the transistor is coupled to the inverter circuit, and a source of the transistor is grounded.

5. The integrated circuit of claim 1 , further comprising: a source contact, the source contact being in conductive contact with the 2DEG; a drain contact, the drain contact being in conductive contact with the 2DEG; a gate terminal proximate to the 2DEG such that a voltage applied to the gate terminal controls whether the 2DEG is continuous between the source contact and the drain contact; and a substrate contact layer, the substrate contact layer being disposed directly below the semiconductor substrate and electrically disconnected from the source contact so that a voltage different from that of the source contact is applied to the substrate contact layer; The bias circuit is configured to bias the portion of the semiconductor substrate below the power transistor by applying a substrate bias voltage to the substrate contact layer.

6. The integrated circuit according to claim 5, wherein: The bias circuit is configured to bias the semiconductor substrate by applying a positive bias voltage to the substrate contact layer, the positive bias voltage being positive relative to a source voltage applied to the source terminal.

7. The integrated circuit according to claim 6, wherein: The positive bias voltage is a fixed positive voltage relative to the source voltage.

8. The integrated circuit according to claim 6, wherein: The positive bias voltage is selectively applied according to a state of the transistor structure.

9. The integrated circuit according to claim 6, wherein: The forward bias voltage varies depending on the state of the transistor structure.

10. The integrated circuit of claim 6, wherein: The bias circuit is configured to cause a maximum voltage of the positive bias voltage to the semiconductor substrate to exceed 100 volts.

11. The integrated circuit according to claim 5, wherein: The bias circuit is also configured to bias the semiconductor substrate contact layer, and the bias circuit is connected to the semiconductor substrate contact layer through a lead.

12. The integrated circuit of claim 5, wherein: The bias circuit is also configured to bias the substrate contact layer, the bias circuit being connected to the substrate contact layer through a via that passes through a die of the integrated circuit to reach the substrate contact layer.

13. The integrated circuit of claim 1, wherein: The integrated circuit is contained in a package.

14. The integrated circuit of claim 13, wherein: The package is a PSOP package.

15. The integrated circuit of claim 13, wherein: The package is a TOLL package.

16. The integrated circuit of claim 13, wherein: The package is a PQFN package.

17. An integrated circuit package, the integrated circuit package comprising an integrated circuit, the integrated circuit comprising: Semiconductor substrate; An epitaxial stack, wherein the epitaxial stack is epitaxially grown on the semiconductor substrate, and the epitaxial stack includes a channel semiconductor layer and a barrier semiconductor layer epitaxially grown on the channel semiconductor layer; an interface between the channel semiconductor layer and the barrier semiconductor layer, for inducing a two-dimensional electron gas (2DEG) in the channel semiconductor layer; a power transistor using a portion of the epitaxial stack, including a portion of the channel semiconductor layer and a portion of the barrier semiconductor layer; and A bias circuit, the bias circuit comprising a plurality of circuit elements, each of at least some of the plurality of circuit elements using a corresponding portion of the epitaxial stack, including: a corresponding portion of the channel semiconductor layer and a portion of the barrier semiconductor layer, the bias circuit being configured to bias a portion of the semiconductor substrate beneath the power transistor.

18. The integrated circuit of claim 16, wherein: The integrated circuit package is a PSOP package.

19. The integrated circuit of claim 16, wherein: The integrated circuit package is a TOLL package.

20. The integrated circuit of claim 16, wherein: The integrated circuit package is a PQFN package.

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