Advanced packaging lamination type transient voltage suppression diode and preparation method thereof

Abstract

The invention provides an advanced packaging lamination type transient voltage suppression diode and a preparation method thereof, and belongs to the technical field of semiconductors, the advanced packaging lamination type transient voltage suppression diode comprises a chip stacking body which is formed by stacking and packaging a plurality of chip semi-finished products, each chip semi-finished product comprises a first rewiring layer and a first lead layer which are exposed out of a first packaging body of the chip semi-finished product; the second packaging body wraps the chip stacking body, the first rewiring layer on the front face of the chip stacking body and the back face of the chip stacking body are exposed out of the second packaging body, and a via hole is formed in the second packaging body; the bonding pads are formed on two opposite sides of one surface, coplanar with the back surface of the chip stacking body, of the second packaging body; and the second rewiring layer is formed on the first rewiring layer on the front surface of the chip stack body, and the second rewiring layer is connected with the bonding pad through a via hole. The method has the advantages that the size of a device can be effectively reduced, and meanwhile the original peak pulse current IPP level in the breakdown direction of a chip is kept unchanged.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an advanced packaged stacked transient voltage suppression diode and a preparation method thereof. Background Art

[0002] With the rapid development of integrated circuit technology, the demand for miniaturization and high integration of electronic devices is increasing. Especially in the field of high current surge protection, the market demand for miniaturized devices with high surge tolerance is particularly obvious.

[0003] At present, surge protection devices on the market usually increase the peak pulse current (IPP) by adding copper particles. Although this method effectively improves the surge absorption capacity of the device, it also increases the cost and increases the thickness of the device, ultimately leading to an increase in the size of the device.

[0004] In addition, as the number of integrated components on modern circuit boards continues to increase, the space left for individual components is becoming increasingly limited. Traditional high-current surge protection products are gradually losing their competitiveness and facing the risk of being eliminated due to their large size in today's pursuit of high integration and miniaturization. Therefore, how to achieve the miniaturization of surge protection devices without sacrificing IPP performance has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides an advanced packaged stacked transient voltage suppression diode; on the other hand, it also provides a method for preparing the advanced packaged stacked transient voltage suppression diode.

[0006] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:

[0007] An advanced packaged stacked transient voltage suppression diode, comprising:

[0008] A chip stack, wherein the chip stack is formed by stacking and packaging a plurality of chip semi-finished products, each of the chip semi-finished products comprising a first redistribution layer and a first lead layer exposed from a first package of the chip semi-finished product;

[0009] A second encapsulation body, wherein the second encapsulation body is wrapped around the chip stack, the first redistribution layer on the front side of the chip stack and the back side of the chip stack are exposed to the second encapsulation body, and the second encapsulation body has a via hole;

[0010] pads formed on two opposite sides of a surface of the second encapsulation body coplanar with the back surface of the chip stack body;

[0011] The second redistribution layer is formed on the first redistribution layer on the front side of the chip stack, and the second redistribution layer is connected to the pad through the via hole.

[0012] Preferably, each of the semi-finished chips further comprises:

[0013] A bare chip, a planting ball is formed on the front side of the bare chip, and the bare chip is connected to the first redistribution layer through the planting ball;

[0014] A first lead layer formed on the back side of the die;

[0015] The first encapsulation body is wrapped around the bare chip, the implant ball and the first wiring layer, and the back side of the first redistribution layer and the front side of the first wiring layer are coplanar with two opposite sides of the first encapsulation body.

[0016] Preferably, the back side of the bare chip is coated with a conductive adhesive layer;

[0017] The first lead layer is formed on the back side of the die through the conductive adhesive layer.

[0018] Preferably, an outer lead layer is formed on the back side of the pad;

[0019] The second encapsulation body is coplanar with the back surface of the outer lead layer.

[0020] The present invention also provides a method for preparing an advanced packaged stacked transient voltage suppression diode, which is used to prepare the advanced packaged stacked transient voltage suppression diode as described above, comprising:

[0021] Step S1, preparing a chip semi-finished product, stacking and packaging a plurality of the chip semi-finished products to form a chip stack; wherein each of the chip semi-finished products comprises a first redistribution layer and a first lead layer exposed in a first package of the chip semi-finished product;

[0022] Step S2, wrapping the chip stack outside to form a second encapsulation body, wherein the first redistribution layer on the front side of the chip stack and the back side of the chip stack are exposed to the second encapsulation body, and the second encapsulation body has a via hole;

[0023] Step S3, forming a second redistribution layer on the first redistribution layer on the front side of the chip stack;

[0024] Step S4, forming pads on two opposite sides of a surface coplanar with the back surface of the chip stack, and the second redistribution layer is connected to the pads through the vias.

[0025] Preferably, the preparation of the semi-finished chip comprises the following steps:

[0026] Step S101, forming a ball on the front side of the die, and loading the die onto a carrier after cutting;

[0027] Step S102, performing a first encapsulation outside the bare die and the implant ball, and grinding the encapsulation body until the surface of the implant ball is exposed;

[0028] Step S103, forming the first redistribution layer on a surface of the encapsulation body coplanar with the implant ball;

[0029] Step S104, removing the carrier board and forming a first lead layer on the back side of the die;

[0030] Step S105 , performing a second encapsulation outside the first lead layer, and grinding the encapsulation until the surface of the first lead layer is exposed.

[0031] Preferably, before step S101, the method further includes:

[0032] Step S100, coating the back side of the die to form a conductive adhesive layer; or

[0033] After step S104, the method further includes:

[0034] Step S104.1, coating a conductive adhesive layer on the back side of the die.

[0035] Preferably, in step S1, stacking and packaging a plurality of the semi-finished chips comprises:

[0036] Step S111, applying solder paste on the carrier board, and performing reflow soldering after mounting the semi-finished chip;

[0037] Step S112, stacking and packaging a plurality of the chip semi-finished products according to the steps of applying solder paste and reflow soldering in step S111 to form the chip stack.

[0038] Preferably, step S2 comprises:

[0039] Step S201, encapsulating the chip stack body on a carrier for the first time, and grinding the encapsulation body until the first redistribution layer on the front side of the chip stack body is exposed;

[0040] Step S202 , drilling a hole in the encapsulation body by laser etching to form the via hole, wherein the via hole penetrates the encapsulation body to the carrier board.

[0041] Preferably, the step S3 comprises:

[0042] Step S301, forming the second redistribution layer on the first redistribution layer on the front side of the chip stack and on the surface of the via hole;

[0043] Step S302 , performing a second encapsulation on the second redistribution layer and the via hole to form the second encapsulation body.

[0044] The advantages or beneficial effects of the technical solution of the present invention are:

[0045] The present invention abandons the copper particles in traditional packaging, prepares the chip semi-finished product by adopting the wafer-level plate packaging method, directly makes electrical connections inside and outside the chip, and prepares the finished product by the rewiring layer process while maintaining the same number of stacked sheets, thereby greatly reducing the thickness of the finished product. While effectively reducing the size of the device, the peak pulse current IPP level of the original breakdown direction of the chip is maintained unchanged. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A schematic cross-sectional view of a semi-finished chip in a preferred embodiment of the present invention;

[0047] Figure 2 A top view of a semi-finished chip in a preferred embodiment of the present invention;

[0048] Figure 3 It is a cross-sectional schematic diagram of a finished product of an advanced packaged stacked transient voltage suppression diode in a preferred embodiment of the present invention;

[0049] Figure 4 A top view of the finished product in a preferred embodiment of the present invention;

[0050] Figure 5 A schematic diagram of a preparation method in a preferred embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of the process of preparing a semi-finished chip in step S1 in a preferred embodiment of the present invention;

[0052] Figure 7 This is a schematic diagram of the process of preparing a semi-finished chip in step S1 in another preferred embodiment of the present invention;

[0053] Figure 8 This is a schematic diagram of the process of chip stack packaging in step S1 in a preferred embodiment of the present invention;

[0054] Fig. 9 This is a flow chart of step S2 in a preferred embodiment of the present invention;

[0055] Fig.10 This is a flow chart of step S3 in a preferred embodiment of the present invention;

[0056] Fig.11 A cross-sectional schematic diagram of each step of preparing a chip semi-finished product in a preferred embodiment of the present invention;

[0057] Fig.12 It is a cross-sectional schematic diagram of each step of preparing the finished product in a preferred embodiment of the present invention.

[0058] Description of reference numerals:

[0059] 100, semi-finished chip; 101, bare die; 102, ball implantation; 103, first redistribution layer; 104, first lead layer; 105, first package; 106, conductive adhesive layer; 107, first tin layer; 108, second tin layer; 200, chip stack; 201, via; 202, second redistribution layer; 203, pad; 204, external lead layer; 205, second package; 300, carrier; 400, solder paste. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0062] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0063] See also Figure 1 and Figure 2 In a preferred embodiment of the present invention, based on the above problems existing in the prior art, an advanced packaged stacked transient voltage suppressor diode (TVS) is provided, comprising:

[0064] A chip stack 200, wherein the chip stack 200 is formed by stacking and packaging a plurality of chip semi-finished products 100, each of which includes a first redistribution layer 103 and a first lead layer 104 exposed from a first encapsulation body 105 of the chip semi-finished product 100;

[0065] A second encapsulation body 205, the second encapsulation body 205 is wrapped around the chip stack 200, the first redistribution layer 103 on the front side of the chip stack 200 and the back side of the chip stack 200 are exposed to the second encapsulation body 205, and the second encapsulation body 205 has a via hole 201;

[0066] The pads 203 are formed on two opposite sides of a surface of the second encapsulation body 205 that is coplanar with the back surface of the chip stack body 200;

[0067] The second redistribution layer 202 is formed on the first redistribution layer 103 on the front side of the chip stack 200 . The second redistribution layer 202 is connected to the pad 203 through the via 201 .

[0068] Specifically, the embodiment of the present invention adopts a wafer-level plate-level packaging method to prepare a chip semi-finished product 100, and directly makes internal and external electrical connections to the chip; while maintaining the same number of stacked sheets, a finished product is prepared through a laser drilling and copper deposition redistribution layer (RDL) process, thereby abandoning the copper particles of traditional packaging and avoiding the accumulation of thickness caused by the copper particles, thereby greatly reducing the thickness of the finished product and making the volume of products with large current surges smaller.

[0069] The TVS device of the embodiment of the present invention solves the problem of large volume of large current surge products, and can effectively reduce the volume of the device while maintaining the original peak pulse current IPP level of the chip in the breakdown direction unchanged.

[0070] As a preferred embodiment, wherein Figure 3 and Figure 4 As shown, each semi-finished chip 100 further includes:

[0071] A bare die 101 (DIE), a bump 102 (Bump) is formed on the front side of the bare die 101, and the bare die 101 is connected to the first redistribution layer 103 through the bump 102;

[0072] The first wiring layer 104 is formed on the back side of the die 101;

[0073] The first encapsulation body 105 wraps around the bare chip 101 , the implant balls 102 and the first wiring layer 104 . The back surface of the first redistribution layer 103 and the front surface of the first wiring layer 104 are coplanar with two opposite surfaces of the first encapsulation body 105 .

[0074] Specifically, in this embodiment, the semi-finished chip 100 is composed of a bare chip 101, a planting ball 102, a first redistribution layer 103, a first lead layer 104 and a first encapsulation body 105. The bare chip 101 is the core part of the chip, including all functional circuits of the chip. The planting balls 102 are formed on the front side of the bare chip 101, and these planting balls 102 are used to realize the connection between the bare chip 101 and the external circuit.

[0075] The first redistribution layer 103 is located above the implant ball 102 and is electrically connected to the bare chip 101 through the implant ball 102 to achieve a complex connection between the internal circuit of the chip and the external circuit. The first lead layer 104 is located on the back of the bare chip 101 and is used to connect to an external circuit or packaging structure. The first encapsulation body is made of insulating material to wrap and protect the bare chip 101, the implant ball 102 and the first lead layer 104.

[0076] The chip semi-finished product 100 is prepared by wafer-level plate packaging, so that the chip can be directly electrically connected to the inside and outside.

[0077] In this embodiment, the DIE is a “bare die 101” or a “crystal grain”, and the packaged DIE forms a chip, that is, a semi-finished chip 100 according to the embodiment of the present invention.

[0078] As a preferred embodiment, the back side of the bare chip 101 is coated with a conductive adhesive layer 106;

[0079] The first wiring layer 104 is formed on the back side of the die 101 through a conductive adhesive layer 106 .

[0080] Specifically, different from the traditional process, the embodiment of the present invention forms a conductive adhesive layer 106 by applying adhesive on the back of the chip. The conductive adhesive layer 106 can play a role of stress buffering, greatly reducing the risk of chip back cracking.

[0081] Preferably, in the manufacturing process of the chip semi-finished product 100, there are two ways of applying glue:

[0082] Apply glue before the ball planting 102 process;

[0083] The glue is applied after the carrier board 300 is removed.

[0084] The glue-brushing process can greatly reduce the risk of chip backside cracking caused by not brushing glue in the traditional process.

[0085] As a preferred embodiment, an outer lead layer 204 is formed on the back of the pad 203;

[0086] The second encapsulation body 205 is coplanar with the back surface of the external lead layer 204 .

[0087] Specifically, the pad 203 is a metal area on the TVS device for soldering component pins or wires. An outer lead layer 204 is electroplated on the pad 203 to provide an electrical connection path from the inside of the chip to the external circuit.

[0088] The bottom surface of the second encapsulation body 205 and the back surface of the external lead layer 204 are located on the same plane, thereby achieving a smooth connection between the chip and the external circuit.

[0089] See also Figure 5 The present invention also provides a method for preparing an advanced packaged stacked transient voltage suppression diode, which is used to prepare the advanced packaged stacked transient voltage suppression diode as described above, and the method comprises:

[0090] Step S1, preparing a chip semi-finished product 100, stacking and packaging a plurality of chip semi-finished products 100 to form a chip stack 200; wherein each chip semi-finished product 100 includes a first redistribution layer 103 and a first lead layer 104 exposed from a first encapsulation body 105 of the chip semi-finished product 100;

[0091] Step S2, forming a second encapsulation body 205 by wrapping the chip stack 200, wherein the first redistribution layer 103 on the front side of the chip stack 200 and the back side of the chip stack 200 are exposed to the second encapsulation body 205, and the second encapsulation body 205 has a via hole 201;

[0092] Step S3, forming a second redistribution layer 202 on the first redistribution layer 103 on the front side of the chip stack 200;

[0093] Step S4 , forming pads 203 on opposite sides of a surface coplanar with the back surface of the second encapsulation body 205 and the chip stack body 200 , and the second redistribution layer 202 is connected to the pads 203 through vias 201 .

[0094] Specifically, in this embodiment, the integration and performance of the transient voltage suppressor diode are significantly improved by stacking and packaging multiple chip semi-finished products 100 into a chip stack 200. This stacking structure allows more chips to be accommodated in a limited packaging space, thereby enhancing the voltage suppression capability and current handling capability.

[0095] The first redistribution layer 103 of each semi-finished chip product 100 is exposed outside the first encapsulation body 105 , so as to realize the electrical connection between the die 101 and the subsequent second redistribution layer 202 .

[0096] The chip stack 200 is wrapped with the second encapsulation body 205 , which can protect the chip stack 200 from interference from the external environment and provide additional mechanical strength.

[0097] While maintaining the same number of stacked sheets, the finished product is prepared by laser drilling and copper deposition in the second rewiring layer 202, which abandons the copper particles of traditional packaging and avoids the accumulation of thickness caused by the copper particles, thereby greatly reducing the thickness of the finished product and making the volume of the product with large current surge smaller.

[0098] As a preferred embodiment, wherein Figure 6 As shown, the preparation of the semi-finished chip 100 includes the following steps:

[0099] In step S100 , a conductive adhesive layer 106 is formed on the back side of the die 101 by coating.

[0100] Step S101, forming a planting ball 102 on the front surface of the bare chip 101, and loading the bare chip 101 onto the carrier 300 after cutting;

[0101] Step S102, performing a first encapsulation outside the bare chip 101 and the implant ball 102, and grinding the encapsulation body until the surface of the implant ball 102 is exposed;

[0102] Step S103, forming a first redistribution layer 103 on a surface of the package body coplanar with the implant ball 102;

[0103] Step S104, removing the carrier 300, and forming a first wiring layer 104 on the back side of the bare chip 101;

[0104] Step S105 , performing a second encapsulation outside the first wiring layer 104 , and grinding the encapsulation until the surface of the first wiring layer 104 is exposed.

[0105] Specifically, in the present embodiment, by forming the conductive adhesive layer 106 on the back side of the bare chip 101 , a stress buffering effect can be achieved, thereby greatly reducing the risk of chip cracking on the back side.

[0106] The bare chip 101 can be electrically connected to the first redistribution layer 103 through the implant ball 102, and the bare chip 101 can be electrically connected to the inside of the TVS device through the first redistribution layer 103. The bare chip 101 can be electrically connected to the outside of the TVS device by providing electrical connection points through the first lead layer 104.

[0107] As a preferred embodiment, wherein Figure 7 As shown, after step S104, the following steps are also included:

[0108] Step S104.1, coating the back side of the die to form a conductive adhesive layer 106.

[0109] Specifically, in the process of preparing the semi-finished chip 100 , step S100 may be removed, and the conductive adhesive layer 106 may be coated after the carrier 300 is removed in step S104 .

[0110] Furthermore, after step S105, the following steps are further included:

[0111] The device prepared in step S105 is subjected to tinning treatment to form a first tin layer 107 on the front side of the first redistribution layer 103 and a second tin layer 108 on the back side of the first lead layer 104, thereby obtaining a chip semi-finished product 100.

[0112] As a preferred embodiment, wherein Figure 8As shown, in step S1, stacking and packaging a plurality of semi-finished chips 100 includes:

[0113] Step S111, brush solder paste on the carrier board 300, and perform reflow soldering after mounting the semi-finished chip 100;

[0114] Step S112 , stacking and packaging a plurality of chip semi-finished products 100 according to the steps of applying solder paste and reflow soldering in step S111 to form a chip stack 200 .

[0115] Specifically, by multiple solder paste brushing and reflow soldering steps, multiple chip semi-finished products 100 are stacked and packaged into a chip stack 200, which can accommodate more chips in a limited packaging space, thereby improving the integration of transient voltage suppression diodes; at the same time, the voltage suppression capability and current handling capability are enhanced.

[0116] As a preferred embodiment, wherein Fig. 9 As shown, step S2 includes:

[0117] Step S201 , performing a first encapsulation on the chip stack 200 on the carrier 300 , and grinding the encapsulation until the first redistribution layer 103 on the front side of the chip stack 200 is exposed;

[0118] Step S202 , drilling a hole in the package by laser etching to form a via hole 201 , wherein the via hole 201 penetrates the package to the carrier 300 .

[0119] As a preferred embodiment, wherein Fig.10 As shown, step S3 includes:

[0120] Step S301 , forming a second redistribution layer 202 on the first redistribution layer 103 and the surface of the via 201 on the front side of the chip stack 200 ;

[0121] Step S302 , performing a second encapsulation on the second redistribution layer 202 and the via hole 201 to form a second encapsulation body 205 .

[0122] Specifically, via holes 201 are drilled by laser etching, and then copper is deposited to form a second redistribution layer 202. While maintaining the same number of stacked sheets, the copper particles of traditional packaging are discarded to avoid the accumulation of thickness caused by the copper particles, thereby greatly reducing the thickness of the finished product and making the volume of products with large current surges smaller.

[0123] Specifically, the steps for preparing the TVS device product according to the embodiment of the present invention include two major processes:

[0124] The first one is to prepare the chip semi-finished product 100 by a wafer-level plate-level packaging method, see the above steps S101 to S105;

[0125] The second step is to stack the semi-finished chip 100 and prepare the finished product through a laser hole conversion and copper deposition RDL process.

[0126] The TVS device of the embodiment of the present invention is mainly used in fields that need to resist large through-current (for example, 8 / 20 μs pure current waveform) surges, including but not limited to outdoor base stations.

[0127] Embodiment 1:

[0128] The embodiment of the present invention provides a 76V bidirectional large current surge TVS device, and the manufacturing method thereof comprises the following steps:

[0129] (1) Semi-finished chip 100 - made by wafer-level plate packaging

[0130] like Fig.11 As shown in (a) to (k), the semi-finished product manufacturing process includes: ball planting 102, cutting, mounting, first encapsulation (molding), first grinding, first copper electroplating, removing the carrier 300, second copper electroplating, second encapsulation, second grinding, tin (Sn) treatment;

[0131] (2) Finished product - three semi-finished products are stacked and processed by laser hole copper deposition RDL process

[0132] like Fig.12 As shown in (a) to (k), the finished product manufacturing process includes: brushing solder paste 400, the first surface mount (Surface Mount Technology, SMT) reflow, brushing solder paste 400, the second surface mount reflow, brushing solder paste 400, the third surface mount reflow, the third encapsulation, grinding, drilling, the third copper plating, the fourth encapsulation, and then electroplating of the pad and the outer lead layer.

[0133] Furthermore, the finished device prepared above is packaged, such as wDFN9580L4P460T210 package. Among them, the wide dual flat no-lead (wDFN) package is a variant of the DFN (Dual Flat No-lead) package. The DFN package is a surface mount package with the advantages of small size, good heat dissipation, small pin spacing, etc., and is suitable for high-density, high-performance integrated circuits.

[0134] The TVS device prepared by the preparation method of the embodiment of the present invention has a volume reduced by 70% compared with the traditional process, which can effectively reduce the volume of the device and make the space occupied by the PCB board smaller.

[0135] The advantages or beneficial effects of adopting the above technical solution are: the present invention abandons the copper particles in traditional packaging, prepares the chip semi-finished product by adopting the wafer-level plate packaging method, directly makes electrical connections inside and outside the chip, and prepares the finished product by the rewiring layer process while maintaining the same number of stacked sheets, which greatly reduces the thickness of the finished product. While effectively reducing the size of the device, the peak pulse current IPP level of the original breakdown direction of the chip is maintained unchanged.

[0136] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. An advanced packaged stacked transient voltage suppressor diode, characterized in that: include: A chip stack, wherein the chip stack is formed by stacking and packaging a plurality of chip semi-finished products, each of the chip semi-finished products comprising a first redistribution layer and a first lead layer exposed from a first package of the chip semi-finished product; A second encapsulation body, wherein the second encapsulation body is wrapped around the chip stack, the first redistribution layer on the front side of the chip stack and the back side of the chip stack are exposed to the second encapsulation body, and the second encapsulation body has a via hole; pads formed on two opposite sides of a surface of the second encapsulation body coplanar with the back surface of the chip stack body; The second redistribution layer is formed on the first redistribution layer on the front side of the chip stack, and the second redistribution layer is connected to the pad through the via hole.

2. The advanced packaged stacked transient voltage suppressor diode according to claim 1, characterized in that: Each of the semi-finished chips further comprises: A bare chip, a planting ball is formed on the front side of the bare chip, and the bare chip is connected to the first redistribution layer through the planting ball; The first lead layer is formed on the back side of the die; The first encapsulation body is wrapped around the bare chip, the implant ball and the first wiring layer, and the back side of the first redistribution layer and the front side of the first wiring layer are coplanar with two opposite sides of the first encapsulation body.

3. The advanced packaged stacked transient voltage suppressor diode according to claim 2, characterized in that: The back side of the bare chip is coated with a conductive adhesive layer; The first lead layer is formed on the back side of the die through the conductive adhesive layer.

4. The advanced packaged stacked transient voltage suppressor diode according to claim 1, characterized in that: An outer lead layer is formed on the back side of the pad; The second encapsulation body is coplanar with the back surface of the outer lead layer.

5. A method for preparing an advanced packaged stacked transient voltage suppressor diode, characterized in that: For preparing the advanced packaged stacked transient voltage suppressor diode according to any one of claims 1 to 4, comprising: Step S1, preparing a chip semi-finished product, stacking and packaging a plurality of the chip semi-finished products to form a chip stack; wherein each of the chip semi-finished products comprises a first redistribution layer and a first lead layer exposed in a first package of the chip semi-finished product; Step S2, wrapping the chip stack outside to form a second encapsulation body, wherein the first redistribution layer on the front side of the chip stack and the back side of the chip stack are exposed to the second encapsulation body, and the second encapsulation body has a via hole; Step S3, forming a second redistribution layer on the first redistribution layer on the front side of the chip stack; Step S4, forming pads on two opposite sides of a surface coplanar with the back surface of the chip stack body, and the second redistribution layer is connected to the pads through the vias.

6. The method for preparing the advanced packaged stacked transient voltage suppressor diode according to claim 5, characterized in that: The preparation of the semi-finished chip comprises the following steps: Step S101, forming a ball on the front side of the die, and loading the die onto a carrier after cutting; Step S102, performing a first encapsulation outside the bare die and the implant ball, and grinding the encapsulation body until the surface of the implant ball is exposed; Step S103, forming the first redistribution layer on a surface of the encapsulation body coplanar with the implant ball; Step S104, removing the carrier board and forming a first lead layer on the back side of the die; Step S105 , performing a second encapsulation outside the first lead layer, and grinding the encapsulation until the surface of the first lead layer is exposed.

7. The method for preparing the advanced packaged stacked transient voltage suppressor diode according to claim 6, characterized in that: Before step S101, the method further includes: Step S100, coating the back side of the die to form a conductive adhesive layer; or After step S104, the method further includes: Step S104.1, coating a conductive adhesive layer on the back side of the die.

8. The method for preparing the advanced packaged stacked transient voltage suppressor diode according to claim 5, characterized in that: In the step S1, stacking and packaging a plurality of the semi-finished chips comprises: Step S111, applying solder paste on the carrier board, and performing reflow soldering after mounting the semi-finished chip; Step S112, stacking and packaging a plurality of the chip semi-finished products according to the steps of applying solder paste and reflow soldering in step S111 to form the chip stack.

9. The method for preparing the advanced packaged stacked transient voltage suppressor diode according to claim 5, characterized in that: The step S2 comprises: Step S201, encapsulating the chip stack body on a carrier for the first time, and grinding the encapsulation body until the first redistribution layer on the front side of the chip stack body is exposed; Step S202 , drilling a hole in the encapsulation body by laser etching to form the via hole, wherein the via hole penetrates the encapsulation body to the carrier board.

10. The method for preparing the advanced packaged stacked transient voltage suppressor diode according to claim 5, characterized in that: The step S3 comprises: Step S301, forming the second redistribution layer on the first redistribution layer on the front side of the chip stack and on the surface of the via hole; Step S302 , performing a second encapsulation on the second redistribution layer and the via hole to form the second encapsulation body.

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