Word line sidewall contacts in 3D NAND structures

Abstract

A three-dimensional (3D) NAND memory structure may include material layers arranged in a vertical stack including alternating horizontal insulating layers and word line layers. The material layer may be etched to form a landing pad. The vertical word lines may extend through one or more horizontal word line layers beneath the landing pad. The vertical word line may be conductively connected to the top horizontal word line, and the vertical word line may be insulated from any of the horizontal word lines through which the vertical word line extends below the top horizontal word line. A pad may also be formed over a top horizontal word line at the landing pad.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Provisional U.S. Patent Application No. 63 / 396,214, filed on August 8, 2022, entitled “WORDLINE SIDEWALL CONTACTS IN3D NAND STRUCTURES,” the entire disclosure of which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] The present disclosure generally describes methods and structures for 3D NAND flash memory devices. More specifically, the present disclosure describes techniques for fabricating word lines in 3D NAND memory structures. Background Art

[0004] A memory design known as NAND memory is a non-volatile flash memory storage architecture that does not require power to maintain its stored data. NAND flash memory is used in many products such as solid-state devices and portable electronic devices. In order to improve the density of NAND memory and reduce its size, the traditional two-dimensional (2D) NAND architecture has been transformed into a three-dimensional (3D) NAND stack. Unlike 2D planar NAND technology, where independent memory cells are stacked together on separate horizontal substrates, 3D NAND uses multiple layers of alternating conductive and dielectric materials with intersecting vertical channels stacked vertically. Summary of the invention

[0005] In some embodiments, a 3D NAND memory structure may include multiple material layers arranged in a vertical stack, the vertical stack may include alternating horizontal insulating layers and horizontal word line layers. The multiple material layers may be etched to form a landing pad. The structure may also include a vertical word line, which may extend through one or more horizontal word line layers below the landing pad. The vertical word line may be conductively connected to a top horizontal word line in the multiple alternating material layers, and the vertical word line may be insulated from one or more horizontal word lines through which the vertical word line extends below the top horizontal word line.

[0006] In some embodiments, a method of manufacturing a 3D NAND memory structure may include forming a plurality of material layers arranged in a vertical stack, the vertical stack may include alternating horizontal insulating layers and horizontal word line layers. The plurality of material layers may be etched to form a landing pad. The method may also include etching holes for the vertical word lines, the vertical word lines extending through one or more horizontal word line layers below the landing pad.

[0007] In some embodiments, a 3D NAND memory structure may include multiple material layers arranged in a vertical stack, which may include alternating horizontal insulating layers and horizontal word line layers. The multiple material layers may be etched to form a landing pad. The structure may include a liner formed above the top horizontal word line at the landing pad. The liner may define a gap between the liner and a vertical sidewall adjacent to the landing pad.

[0008] In any embodiment, any and / or all of the following features may be implemented in any combination and are not limited. The structure may also include an oxide barrier layer that insulates one or more horizontal word lines from the vertical word lines. The barrier layer may be disposed between the vertical word lines and the top horizontal word line at the landing pad. The structure may also include a conductive pad above the top horizontal word line at the landing pad, the conductive pad conductively contacting the top horizontal word line and the vertical word line. The vertical word line may extend downward into the substrate beneath the multiple material layers. The vertical word line may extend downward into the substrate beneath the multiple material layers. The vertical word line may contact the horizontal insulating layer. The method may also include filling the holes of the vertical word lines with a fill material and stripping the sacrificial material from the horizontal word line layer. The method may also include forming a barrier layer in the void remaining after stripping the sacrificial material from the horizontal word line, wherein the barrier layer may be formed on the vertical sidewalls of the fill material, the fill material being exposed in the void remaining after stripping the sacrificial material. Forming the barrier layer may include forming an oxide layer on the vertical sidewalls of the fill material using an ALD process. The barrier layer may be formed on the vertical sidewalls of the fill material. Thick and The method may also include filling a void remaining after stripping the sacrificial material from the horizontal word line with a first conductive material; removing the filling material from the hole of the vertical word line; and / or filling the hole of the vertical word line with a second conductive material, wherein the barrier layer may insulate the second conductive material from the first conductive material for one or more horizontal word lines below the landing pad. The liner may include an insulating liner formed of a material different from the sacrificial material forming the horizontal word line layer. The liner may include a conductive liner comprising a first conductive material in conductive contact with a second conductive material, the second conductive material forming the top horizontal word line at the landing pad. The structure may also include a barrier layer between the horizontal word line layer and the vertical word line, the barrier layer insulating the horizontal word line from the vertical word line. The liner may expose vertical sidewalls of multiple material layers adjacent to the landing pad. The gap may be between about 50 nm wide and about 100 nm wide. The gap may expose a portion of the top horizontal word line at the landing pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A further understanding of the nature and advantages of the various embodiments may be realized by reference to the remainder of the specification and the drawings, wherein the same reference numerals are used in the several drawings to represent similar components. In some instances, a sub-label is associated with a reference numeral to indicate one of multiple similar components. When reference is made to a reference numeral without specifying an existing sub-label, it is intended to represent all such multiple similar components.

[0010] Figure 1 A top plan view of one embodiment of a processing system showing deposition, etch, bake, and cure chambers in accordance with some embodiments.

[0011] FIG. 2A to FIG. 2B A 3D NAND structure formed to expose a landing pad for a horizontal word line is shown in accordance with some embodiments.

[0012] Figure 3 Methods of fabricating a 3D NAND memory structure according to some embodiments are labeled.

[0013] FIG. 4A to FIG. 4L Steps in a process for forming a 3D NAND structure are shown in accordance with some embodiments.

[0014] Figure 5 A 3D NAND structure according to some embodiments is shown. DETAILED DESCRIPTION

[0015] Figure 1 A top plan view of one embodiment of a processing system 100 of deposition, etching, baking, and curing chambers according to some embodiments is shown. In the figure, a pair of front-opening wafer cassettes 102 supply substrates of various sizes, which are received by a robot 104 and placed into a low pressure holding area 106 and then placed into one of the substrate processing chambers 108a-f located in the serial sections 109a-c. A second robot 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. Each substrate processing chamber 108a-f can be equipped to perform a number of substrate processing operations, including dry etching processes described herein in addition to cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma treatment, degassing, orientation, and other substrate processes.

[0016] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing and / or etching a material film on a substrate or wafer. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit materials on a substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to cure, anneal, or process the deposited film. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit and cure films on a substrate. Any one or more of the processes described may be performed in an additional chamber separate from the manufacturing system illustrated in the different embodiments. It will be appreciated that the processing system 100 may consider additional configurations of chambers for deposition, etching, annealing, and curing of material films. In addition, any number of other processing systems may be used for the present technology, which may be incorporated into a chamber for performing any specific operation. In some embodiments, a chamber system that can provide access to multiple processing chambers while maintaining a vacuum environment in various sections (such as the holding and transfer areas) can allow operations to be performed in multiple chambers while maintaining a specific vacuum environment between discrete processes.

[0017] The processing system 100, or more specifically the chambers incorporated into the processing system 100 or other processing systems, can be used to produce structures according to some embodiments of the present technology. For example, the processing system 100 can be used to produce memory arrays by performing operations (such as deposition, etching, sputtering, polishing, cleaning, etc.) in various substrate processing chambers 108.

[0018] The 3D NAND memory structure may include multiple alternating pairs of metal and oxide layers stacked vertically on top of each other. Each of the horizontal metal layers may represent a word line associated with a vertical channel to form a memory component. To connect these horizontal word lines, a landing pad may be created at each independent pair of metal and oxide layers for connecting to the vertical word lines.

[0019] Figure 2AA 3D NAND structure 200 is shown that is formed using a staircase etch to expose a landing pad 216 for each of the horizontal word lines in accordance with some embodiments. Such a staircase formation for the 3D NAND structure 200 can be formed by forming a photolithographic photoresist mask on the top of the structure, and then repeatedly removing edge portions of the mask and performing directional etching downward to remove the independent layer pairs 210. Each of the layer pairs 210 can include a metal layer 212 and an oxide layer 214. As described below, each of the metal layers 212 can be formed by filling the voids remaining after removing the sacrificial nitride material. The landing pad 216 can expose the independent metal layer 212 in each of the layer pairs 210. The vertical word lines 218 can then be formed so that the independent vertical word lines 218 only contact the corresponding horizontal word lines. Care is generally taken to avoid etching through the metal layers 212 so as to prevent the vertical word lines 218 from contacting more than one metal layer 212.

[0020] Figure 2B An alternative 3D NAND structure 202 is shown according to some embodiments. Other embodiments do not form Figure 2A 202. Instead of the pure step structure shown in 202, different geometries may be used to expose the landing pads for each of the vertical word lines. This particular type of structure 202 may be formed using a so-called chop etch. It should be understood that any geometry or 3D NAND structure may be used in conjunction with the techniques described below and / or the disclosed methods for forming contacts between horizontal metal layers and vertical word lines. Thus, as used herein, a landing pad or contact pad may be defined as a surface etched into a 3D NAND structure as part of a step or chop etch that forms a surface to contact the vertical word lines.

[0021] It should also be understood that these 3D NAND structures 200, 202 can actually be very large, including hundreds of alternating oxide / nitride layers. The metal layer 212 can be formed of any conductive or metallic material, and the vertical word lines 218 can also be formed of any conductive or metallic material, including tungsten, molybdenum, or any similar material. These figures are not drawn to scale, and the vertical word lines 218 may be much wider than the thickness of the metal layer 212 and / or the oxide layer 214. For example, the exposed surface of the landing pad 216 can be between about 600nm and about 900nm, and the width of the vertical word lines 218 can be between about 100nm and about 300nm, such as about 200nm.

[0022] Each of the vertical word lines 218 may be formed together in a single etching process. Thus, the etching process may generally have a very high selectivity with respect to the tungsten of the metal layer 212 of the landing pad 216 in order to avoid etching through the metal layer 212 when forming the vertical holes for the vertical word lines 218. Thus, there is a technical problem in manufacturing a 3D NAND structure, namely that great precision is required when etching the holes for the vertical word lines 218. Because the etching must have a high selectivity to the material of the metal layer 212, this limits the type of etching that can be used and creates a risk of accidentally striking through the metal layer 212, thereby connecting multiple metal layers 212 in the structure.

[0023] Embodiments described herein address these and other technical issues by forming a horizontal contact layer on a landing pad and vertically isolating the vertical word lines from the underlying metal layers in the stack. Rather than carefully etching down to the contact pad, holes can be etched through the contact pad and through the underlying oxide / metal layer pairs. These holes can then be filled with silicon and undergo an oxidation process after removing the sacrificial nitride layer. Next, the silicon oxide layer can isolate the horizontal metal word line layer from the vertical holes formed for the vertical metal word lines while the gaps remaining from the sacrificial nitride layer are filled with a metal layer. The metal layer can fill the layer gaps with each landing pad to contact the vertical word lines at the top layer, while the lower layers are isolated by the silicon oxide isolation layer.

[0024] Figure 3 A method 300 of fabricating a 3D NAND memory structure according to some embodiments is labeled. FIG. 4A to FIG. 4L Incremental structural steps in a process for forming a 3D NAND structure are shown. The structural description is provided by way of example only and is not intended to be limiting. Each of the method steps may be FIG. 4A to FIG. 4L The invention is broader than the specific examples shown in FIG.

[0025] The method 300 may include forming a plurality of material layers arranged in a vertical stack including alternating horizontal insulating layers and horizontal word line layers (302). Figure 4AA 3D NAND structure 400 is shown after performing a step etch or other operation to expose multiple landing pads according to some embodiments. The 3D NAND structure 400 may be formed on a substrate and may have multiple stacked layers covering the substrate. The substrate may include silicon, silicon germanium, or other substrate materials. The layers may include an IPD layer of an ONO layer, and a dielectric material may be included in the alternating layers, and the dielectric material may be silicon oxide. For example, the structure 400 may include multiple alternating layers of horizontal insulating layers 414, such as oxide or silicon oxide layers. The structure 400 may also include a placeholder or sacrificial material layer, which may be silicon nitride or polysilicon and may be referred to as a horizontal sacrificial layer 416. The sacrificial layer 416 may be or include a material that will be removed to produce an independent memory cell in a subsequent operation. Thus, the sacrificial layer 414 may also be referred to as a horizontal word line layer because these layers will be used as word lines later. As used herein, the term word line may refer to these layers filled with sacrificial materials or conductive or metallic materials.

[0026] Although shown as only a limited number of material layers, the exemplary structure may include any number of layers, including hundreds of layers of material, and it will be understood that the figures are only schematic to illustrate aspects of the present technology. For example, the semiconductor structure 400 may include 10 or more layer pairs, 20 or more layer pairs, 50 or more layer pairs, 100 or more layer pairs, etc. For example, the height of the structure 400 may be greater than 10 μm, greater than 20 μm, etc.

[0027] In this example, etching has been used to expose the contact pads or landing pads 422 for the word lines. The landing pads 422 can expose the sacrificial layer 416 at each alternating oxide / nitride layer. The landing pads 422 can be defined as the flat areas of the sacrificial layer exposed between different etch levels in the structure 400. For example, Figure 4A Three different landing pads 421, 422, 423 are shown. The etching to produce the landing pads 421, 422, 423 may include the following: Figure 2A The step etching shown in FIG. Figure 2B The following discussion will focus on landing pad 422, but is equally applicable to other etch types.

[0028] After the landing pad 422 is exposed, the liner 420 may be deposited over the structure 400. The liner 420 may include a doped silicon oxide layer. For example, the silicon oxide of the liner 420 may be doped with boron, phosphorus, boron and phosphorus, or other similar materials. The liner 420 may be deposited using any deposition technique. For example, the liner 420 may be deposited using an atomic layer deposition (ALD) process such that the liner 420 is formed over the sacrificial layer 416 exposed at the top of the landing pad 422. The liner 420 may also be formed vertically against the exposed alternating layers of the sacrificial layer 416 and the insulating layer 414. Other techniques for deposition may include chemical vapor deposition (CVD) and other similar processes.

[0029] Figure 4B The removal of a portion of a liner according to some embodiments is shown. For example, a sidewall 429 of the liner 420 can be removed from the exposed edges of the alternating insulating layer 414 and sacrificial layer 416. This sidewall 429 of the liner 420 can be removed using a dry etching process, such as directional etching. For example, a carbon layer can be deposited on top of the liner 420 to expose the sidewall 429 to an argon treatment, so that only the surface area of ​​the sidewall 429 is exposed to the argon treatment, and the vertical sidewall 429 can be subsequently removed.

[0030] Removing sidewalls 429 may define gaps 428 in which sacrificial layer 416 is exposed. For example, gaps 428 may be defined by the edges of liner 420 and vertical sidewalls of multiple material layers adjacent to the landing pad, such as Figure 4B . Gap 428 may be from about 50 nm wide to about 100 nm wide. In various embodiments, gap 428 may be less than or about 25 nm, less than or about 50 nm, less than or about 75 nm, less than or about 100 nm, less than or about 125 nm, less than or about 150 nm, and the like. The size of gap 428 may be adjusted based on the thickness of vertical sidewalls 429 exposed by the carbon layer when vertical sidewalls 429 are removed. In contrast, the length of landing pad 422 may be from about 600 nm wide to about 1000 nm wide. After removing the sidewalls 429 of liner 420 and exposing gap 428 on landing pad 422, a large area gap filling using gap filling material 430 may be performed. For example, silicon oxide may be used as gap filling material 430 in the area above landing pads 421, 422, 423 of stepped structure 400.

[0031] Figure 4C Deposition of a hard mask 432 on top of the gap fill material 430 is shown in accordance with some embodiments. Figure 4DIt is shown how the hard mask 432 according to some embodiments can be opened with a pattern 434 above each of the landing pads. These operations can be performed using conventional techniques. This process can create holes in the hard mask 432 for subsequent etching processes to form contact holes in which vertical word lines can be formed.

[0032] The method 300 may also include etching holes for vertical word lines extending through one or more horizontal word line layers beneath the landing pad ( 304 ). Figure 4E A contact etch is shown that may be performed to create holes for vertical word lines in accordance with some embodiments. An etch may be performed through a hard mask 432 to etch holes through the gap fill material 430 and the liner 420. This may be in contrast to conventional methods for forming vertical word lines. Prior to the present disclosure, this etch was performed after the sacrificial layer 416 was removed and the gap was filled with a metal layer. Subsequently, the etch must be performed so that only the top metal layer is exposed on each landing pad. Therefore, the etch must have a high selectivity to the metal layer (e.g., tungsten) to prevent the etch strike from penetrating the top metal layer and shorting the memory elements within the structure 400.

[0033] In contrast to conventional methods, some embodiments may instead etch contact holes 436 that penetrate not only the gap fill material, but also the liner 420 and multiple sacrificial layers 416 and / or insulating layers 414 below. For example, some embodiments may etch holes 436 down to substrate 438. Substrate 438 may include a silicon substrate or oxide layer that is thicker than other insulating layers 414. Some embodiments may etch holes 436 through all sacrificial layers 416 and / or insulating layers 414. Some embodiments may etch holes 436 such that holes 436 penetrate more than one sacrificial layer 416, but not all sacrificial layers 416 below landing pad 422. Some embodiments may etch holes 436 such that holes 436 penetrate below the surface level of substrate 438. Some embodiments may etch each hole 436 to the same depth, other embodiments may adjust the depth of each hole to penetrate below the top sacrificial layer of each landing pad.

[0034] The method may also optionally include filling the holes of the vertical word lines with a filling material and / or stripping sacrificial material from the horizontal word line layer (306). Figure 4F 436. A deposition process may be used to fill the hole 436 with a filling material 440, such as silicon. In contrast to the prior art, the filling material 440 may fill the hole 436 such that the filling material 440 penetrates through multiple sacrificial layers 416 and / or insulating layers 414, all sacrificial layers 416 and / or insulating layers 414, down to the surface of the substrate 438, or below the surface of the substrate 438.

[0035] Figure 4GA stripping process for sacrificial layer 416 is shown in accordance with some embodiments. For example, a wet etching process may be used to strip the silicon nitride material used as sacrificial layer 416. The voids 442 left after removing sacrificial layer 416 may later be filled with a metal layer to form horizontal word lines for memory elements in structure 400. Thus, the sacrificial layer stripping process may leave behind insulating layer 414, liner 420, fill material 440, and gap fill material 430.

[0036] The method may also optionally include forming a barrier layer (308) in the voids left after stripping the sacrificial material from the horizontal word lines. Figure 4H The formation of a barrier layer 444 for horizontal word lines according to some embodiments is shown. The surface of the fill material 440 may be exposed inside the void 442 left after removing the sacrificial layer 416, and the barrier layer is formed on the vertical sidewalls of the fill material exposed in the void left after stripping the sacrificial material. The barrier layer 444 may be used to isolate the area inside the void 442 from the contact hole filled with the fill material 440. As will be illustrated below, the barrier layer 444 may later isolate the conductive horizontal word lines from the conductive vertical word lines along the depth of each of the contact holes under the contact pads.

[0037] Several different processes can be used to form the barrier layer. In some embodiments, a silicon oxidation process can be used. During the oxidation process, for example, a silicon oxide layer can form on the exposed silicon of the fill material 440 in these voids 442. Thus, the oxidation process can form a barrier layer 444 within each of the voids 442 adjacent to the fill material 440.

[0038] Some embodiments may replace the silicon oxidation process described above with an ALD process to form a barrier layer 444 in the voids 442 adjacent to the fill material 440. The ALD process does not oxidize the silicon of the fill material 440, but may incrementally deposit an oxide layer to form a barrier layer 444 in each of the voids 442. This is useful because the oxidation process may also affect the equivalent oxide thickness (EOT) of the device defined by the MANOS stack. In addition, the ALD process may be used to deposit several other dielectrics that may have more favorable selectivity than silicon-only oxide during the remainder of the device integration steps. The ALD process may also be used to accurately control the thickness of the barrier layer 444.

[0039] Compared to other dimensions within the 3D main structure, barrier layer 444 can be relatively thin. For example, depending on the size of structure 400, barrier layer 444 can be less than or about Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately For example, the barrier layer 444 may be approximately Thick to approximate The barrier layer 444 may extend into the void 442. In various embodiments, the barrier layer may be approximately About Between or greater than about About In about About Between or greater than about About In about About Between or greater than about About In about About Between or greater than about About In about About Between or greater than about About In about About Between or greater than about About etc.

[0040] Fig. 4I 442. The wordline deposition in accordance with some embodiments is shown. For example, some embodiments may first form an aluminum oxide layer (e.g., a high dielectric constant layer) in void 442. The aluminum oxide may be deposited using an ALD process to coat any exposed surfaces in void 442. For example, the aluminum oxide layer may be approximately 2 nm thick to about 3 nm thick. Note that the aluminum oxide layer is Fig. 4I4. The word line layer 450 is not explicitly shown in FIG. 4 due to its relatively small size. Subsequently, a deposition process may be used to deposit a horizontal word line layer 450 in the gap 442. The horizontal word line layer may be formed using any conductive material or metal, such as tungsten, molybdenum, or other similar conductive materials.

[0041] The method 300 may further optionally include removing the fill material and filling the hole with a conductive material ( 310 ). Figure 4J The removal of fill material 440 according to some embodiments is shown. The purpose of fill material 440 is to provide a surface for barrier layer 444 described above. For example, fill material 440 can provide a surface of silicon oxide on which barrier layer 444 will be grown using the oxidation process described above. Alternatively, fill material 440 can provide a surface on which oxide will be formed using the ALD process described above. Thus, after barrier layer 444 is formed and horizontal word line layer 450 has been formed, fill material 440 can be removed. As shown, this can expose contact hole 436 again.

[0042] Figure 4K Removal of the liner 420 is shown in accordance with some embodiments. For example, an etching process may be used to remove a doped silicon oxide material that may be used for the liner 420. In some embodiments, an aluminum oxide layer formed between the horizontal word line layer 450 and the liner 420 may also be removed. By removing the aluminum oxide layer, a void 452 may be exposed between the top horizontal word line layer and the contact hole 436. For example, a two-step etch may be used to first remove the doped silicon oxide of the liner 420, and then a second step may remove the aluminum oxide layer.

[0043] Figure 4L The formation of vertical word lines according to some embodiments is shown. For example, some embodiments may first deposit a titanium nitride liner, and then fill the contact hole 436 with a metal or other conductive material to form a vertical word line 456. This process may also fill the gap 452 with a metal or other conductive material to form a conductive liner 454, which is used to replace the liner 420. The conductive liner 454 may include tungsten, molybdenum, titanium, or other similar materials.

[0044] In some embodiments, the conductive pad 454 may be formed simultaneously with the vertical word line 456. Thus, the same material may be used to form both the conductive pad 454 and the vertical word line 456. This material may be the same or different than the conductive material used to form the horizontal word line layer 450. More generally, the horizontal word line layer 450 may be formed of a first conductive material, and the conductive pad 454 may be formed of a second conductive material. The first conductive material may be the same as the second conductive material, or the first material may be different from the second conductive material.

[0045] Note that the conductive material of vertical word line 456 may only be in electrical contact with conductive pad 454 of replacement pad 420 to contact the top horizontal word line layer. Thus, vertical word line 456, conductive pad 454, and the top horizontal word line layer may be referred to as being conductively connected to each other. For example, this conductive connection may include a resistance of less than 5 ohms. In other embodiments, this conductive connection may include less than about 10 ohms, less than about 20 ohms, less than about 50 ohms, or less than about 100 ohms, depending on the embodiment. This conductive connection may also include direct contact between these layers without any significant intermediate layers of insulating material.

[0046] As with conventional 3D NAND structures, vertical word line 456 is in conductive contact only with the top metal layer as a horizontal word line, while being insulated from the other horizontal word lines. However, here the connection is through conductive pad 454, replacing pad 420. Gap 428 prevents conductive pad 454 from contacting any of the horizontal word line layers 450 above the intended horizontal word line. In addition, since the metal of vertical word line 456 extends downward through structure 400, barrier layer 444 formed on the fill material prevents vertical word line 456 from contacting any of the underlying metal layers. Figure 5 A view of the 3D NAND structure after this process is completed is shown.

[0047] As used herein, the terms "about" or "approximately" or "substantially" may be interpreted as being within the range expected by those skilled in the art in view of the present specification.

[0048] In the above description, for the purpose of explanation, several specific details are set forth in order to provide a thorough understanding of various embodiments. However, it will be apparent that some embodiments may be practiced without some of these specific details. In other cases, well-known structures and devices are illustrated in the form of block diagrams.

[0049] The above description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the above description of the various embodiments will provide an enabling disclosure for implementing at least one embodiment. It should be understood that various changes in the function and arrangement of components may be made without departing from the spirit and scope of some embodiments as set forth in the claims.

[0050] Specific details are given in the above description to provide a thorough understanding of the present disclosure. However, it will be understood that embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be illustrated as components in the form of block diagrams so as not to obscure the embodiments with unnecessary details. In other cases, well-known circuits, processes, algorithms, structures, and techniques may be illustrated without unnecessary details so as to avoid obscuring the embodiments.

[0051] In addition, it is noted that an independent embodiment can be described as a process, which is depicted as a flow chart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flow chart can describe an operation as a continuous process, many operations can be performed in parallel or simultaneously. In addition, the order of the operations can be rearranged. The process can terminate when its operation is completed, but can have additional steps not included in the diagram. The process can correspond to a method, a function, a program, a subroutine, a subprogram, etc. When the process corresponds to a function, its termination can correspond to the function returning to the calling function or the main function.

[0052] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying instructions and / or data. A code segment or machine-executable instruction may represent a program, function, subroutine, program, routine, subroutine, module, software package, category, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or hardware circuit by passing and / or receiving information, data, independent variables, parameters, or memory contents. Information, independent variables, parameters, data, etc. may be passed, forwarded, or sent via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0053] In addition, the embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. When implemented in software, firmware, middleware, or microcode, program code or code segments for performing the necessary tasks may be stored in a machine-readable medium. A processor may perform the necessary tasks.

[0054] In the above description, features are described with reference to specific embodiments thereof, but it should be appreciated that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used independently or in combination. In addition, embodiments may be utilized in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the specification. The specification and drawings are thus to be considered illustrative rather than restrictive.

[0055] In addition, for the purpose of illustration, the method is described in a specific order. It should be understood that in alternative embodiments, the method can be performed in an order different from that described. It should also be understood that the method described above can be performed by hardware components or can be embodied in a sequence of machine executable instructions, which can be used to cause a machine (such as a general or special processor or logic circuit) to perform the method with instruction programming. These machine executable instructions can be stored on one or more machine readable media, such as CD-ROM or other types of optical disks, floppy disks, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, flash memory, or other types of machine readable media suitable for storing electronic instructions. Alternatively, the method can be performed by a combination of hardware and software.

Claims

1. A three-dimensional (3D) NAND memory structure, comprising: a plurality of material layers arranged in a vertical stack, the vertical stack comprising alternating horizontal insulating layers and horizontal word line layers, wherein the plurality of material layers are etched to form a landing pad; and A vertical word line extends through one or more of the horizontal word line layers below the landing pad, wherein: The vertical word line is conductively connected to a top horizontal word line in the plurality of alternating material layers and is insulated from the one or more horizontal word lines through which the vertical word line extends beneath the top horizontal word line.

2. The 3D NAND memory structure of claim 1, further comprising an oxide barrier layer insulating the one or more horizontal word lines from the vertical word lines.

3. The 3D NAND memory structure of claim 2, wherein the barrier layer is disposed between the vertical word line and the top horizontal word line at the landing pad.

4. The 3D NAND memory structure of claim 1, further comprising a conductive pad over the top horizontal word line at the landing pad, the conductive pad conductively contacting the top horizontal word line and the vertical word line.

5. The 3D NAND memory structure of claim 1, wherein the vertical word lines extend down to a substrate beneath the plurality of material layers.

6. The 3D NAND memory structure of claim 1, wherein the vertical word lines extend downward into the substrate beneath the plurality of material layers.

7. The 3D NAND memory structure of claim 1, wherein the vertical word line contacts the horizontal insulating layer.

8. A method of manufacturing a three-dimensional (3D) NAND memory structure, the method comprising the steps of: forming a plurality of material layers arranged in a vertical stack, the vertical stack comprising alternating horizontal insulating layers and horizontal word line layers, wherein the plurality of material layers are etched to form a landing pad; and Holes are etched for vertical word lines extending through one or more of the horizontal word line layers beneath the landing pad.

9. The method of claim 8, further comprising the steps of: filling the hole of the vertical word line with a filling material; and Sacrificial material is stripped from the horizontal word line layer.

10. The method of claim 9, further comprising the step of forming a barrier layer in a void left after stripping the sacrificial material from the horizontal word line, wherein the barrier layer is formed on vertical sidewalls of the filling material exposed in the void left after stripping the sacrificial material.

11. The method of claim 10, wherein forming the barrier layer comprises forming an oxide layer on the vertical sidewalls of the fill material using an ALD process.

12. The method of claim 10, wherein the barrier layer is Thick and Thick between.

13. The method of claim 10, further comprising the steps of: filling the void left after stripping the sacrificial material from the horizontal word line with a first conductive material; removing the fill material from the hole of the vertical word line; and The holes for the vertical word lines are filled with a second conductive material, wherein the barrier layer insulates the second conductive material from the first conductive material for the one or more horizontal word lines underlying the landing pad.

14. A three-dimensional (3D) NAND memory structure comprising: a plurality of material layers arranged in a vertical stack, the vertical stack comprising alternating horizontal insulating layers and horizontal word line layers, wherein the plurality of material layers are etched to form a landing pad; and A liner is formed over the top horizontal character line at the landing pad, wherein the liner defines a gap between the liner and a vertical sidewall adjacent to the landing pad. 15 . The 3D NAND memory structure of claim 14 , wherein the liner comprises an insulating liner formed of a material different from a sacrificial material forming the horizontal word line layer.

16. The 3D NAND memory structure of claim 14, wherein the liner comprises a conductive liner comprising a first conductive material in conductive contact with a second conductive material forming the top horizontal word line at the landing pad.

17. The 3D NAND memory structure of claim 14, further comprising a barrier layer between the horizontal word line layer and the vertical word lines insulating the horizontal word line layer from the vertical word lines.

18. The 3D NAND memory structure of claim 14, wherein the liner exposes vertical sidewalls of the plurality of material layers adjacent to the landing pad.

19. The 3D NAND memory structure of claim 14, wherein the gap is between about 50 nm wide and about 100 nm wide.

20. The 3D NAND memory structure of claim 14, wherein the gap exposes a portion of the top horizontal word line at the landing pad.

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