Chip structure and chip packaging method

Abstract

The invention provides a chip structure and a chip packaging method. The chip structure comprises: a chip substrate; the front side of the chip substrate is provided with a front side metallization layer, and the front side metallization layer comprises a front side pressure point and a front side grounding metallization area; the back side of the chip substrate is provided with a back side metallization layer, the back side metallization layer comprises back side pressure points and back side grounding metallization areas, the front side pressure points and the back side pressure points are correspondingly arranged, and the back side grounding metallization areas and the front side grounding metallization areas are correspondingly arranged; a plurality of Via through hole interconnection structures are arranged in the chip substrate, the front face pressure points are connected with the corresponding back face pressure points through the Via through hole interconnection structures, the front face grounding metallization areas are connected with the back face grounding metallization areas through the Via through hole interconnection structures, and the back face pressure points serve as contact terminals for signal transmission with an external circuit. In the chip manufacturing stage, the pressure points on the front surface of the chip can be led out to the back surface, so that electromagnetic coupling generated when the chip is connected with an external circuit in a packaging manner in the later stage is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a chip structure and a chip packaging method. Background Art

[0002] In recent years, competition in the semiconductor chip market has become fierce, and the chip market has gradually shifted to a situation where product quality and price competition coexist. The final application form of the chip is the packaging form. As a representative of advanced packaging, wafer-level chip packaging has the advantages of small size, low cost, and short electrical interconnection path compared to traditional packaging, and has been widely used.

[0003] Wafer-level chip size packaging is a packaging process that is performed directly on the wafer after the entire wafer is produced, and then it is cut into single chips. The package size is almost the same as the original chip size. The solder balls serve as contact terminals for electrical connection between the chip and the external circuit, and the chip is soldered to the PCB printed circuit board. The typical packaging form of wafer-level chip packaging is to package and implant balls on the circuit layer on the front of the chip, and contact the solder balls with the external circuits such as the pads of the PCB circuit board. At this time, the RF wiring of the package's rewiring layer will have a strong electromagnetic coupling effect with the chip due to the close contact distance with the chip circuit layer, causing interference to normal signals, and even generating spurious or self-excitation. In order to avoid coupling, the conventional practice is to bypass the RF wiring to minimize the overlap between the package RF line and the chip circuit wiring. However, this not only makes the line design complicated and cumbersome, and increases the number of wiring layers, but also increases the transmission loss, which greatly reduces the performance after packaging.

[0004] It can be seen that although there are some common solutions to the above problems, these solutions are to avoid and remedy the problems during the packaging process after the chip is completed, which prolongs the design cycle and has problems such as poor improvement effect or high design cost, and the effect of avoiding electromagnetic coupling is not good. Summary of the invention

[0005] The embodiments of the present invention provide a chip structure and a chip packaging method to solve the problem of poor microwave performance caused by electromagnetic coupling when the chip is packaged and connected with an external circuit.

[0006] In a first aspect, an embodiment of the present invention provides a chip structure, including: Chip substrate; A front metallization layer is provided on the front side of the chip substrate, and the front metallization layer includes a front pressure point and a front grounding metallization area; A back metallization layer is provided on the back of the chip substrate, the back metallization layer includes back pressure points and back grounding metallization areas, the front pressure points are arranged one-to-one with the back pressure points, and the back grounding metallization areas are arranged correspondingly with the front grounding metallization areas; A number of Via through-hole interconnect structures are provided in the chip substrate. The front pressure points are connected to the corresponding back pressure points through the Via through-hole interconnect structures. The front grounding metallization area is connected to the back grounding metallization area through the Via through-hole interconnect structures. The back pressure points serve as contact terminals for signal transmission with external circuits.

[0007] In a possible implementation, the back pressure point is disposed directly below the corresponding front pressure point.

[0008] In a possible implementation, the front metallization layer further includes a die, a capacitor, a resistor, and a microstrip line.

[0009] In a possible implementation, the front voltage point includes a radio frequency input voltage point, a radio frequency output voltage point, a gate electrode voltage point, and a drain electrode voltage point.

[0010] In a second aspect, an embodiment of the present invention provides a chip packaging method, which is implemented based on a chip manufactured based on the above chip structure, and includes: A cavity structure is formed on the front circuit surface of the chip, and the cavity is fixed just above the active area of ​​the chip; The composite material is used to wrap the entire front and side periphery of the chip to form a first plastic encapsulation layer, and the wrapped area covers the front grounding metallization area and the cavity structure; A plurality of first copper pillars are arranged at the back pressure points and the back grounding metallization area, and a second plastic sealing layer is arranged at the bottom of the back of the chip and the bottom of the first plastic sealing layer to wrap the first copper pillars; wherein the second plastic sealing layer is flush with the bottom of the first copper pillars; A second dielectric layer is arranged at the bottom of the second plastic sealing layer, a plurality of second copper pillars are arranged in the second dielectric layer, and the second copper pillars are connected to the first copper pillars in a one-to-one correspondence; A redistribution layer is provided at the bottom of the second dielectric layer; wherein the wiring of the redistribution layer is connected to the second copper pillars correspondingly; A third dielectric layer is provided at the bottom of the second dielectric layer and the redistribution layer, a plurality of third copper pillars are provided in the third dielectric layer, and the wirings of the redistribution layer are connected to the third copper pillars correspondingly; A plurality of metallized contact pads are arranged at the bottom of the third copper column, and solder balls are arranged at the bottom of the metallized contact pads.

[0011] In a possible implementation, the cavity structure is constructed by a first dielectric layer; The first dielectric layer, the second dielectric layer and the third dielectric layer are all PI dielectrics; The first plastic sealing layer and the second plastic sealing layer are both epoxy resin.

[0012] In a possible implementation, the first copper pillar is formed by electroplating; A plurality of second copper pillars are arranged in the second dielectric layer, including: Performing development and exposure at a position of the second dielectric layer corresponding to the first copper pillar to expose the first copper pillar; Performing ion sputtering and metallization filling at the bottom of the first copper column to obtain a second copper column; A plurality of third copper pillars are arranged in the third dielectric layer, including: Expose and develop at a position of the third dielectric layer corresponding to a wiring end of the redistribution layer to expose the wiring end of the redistribution layer; Ion sputtering and metallization filling are performed at the wiring end of the redistribution layer to obtain a third copper column.

[0013] In a possible implementation, a redistribution layer is provided at the bottom of the second dielectric layer, including: Ion sputtering is performed on the surface of the second dielectric layer to provide a redistribution layer, and wiring is performed on the redistribution layer.

[0014] In a possible implementation manner, the bottom of the third copper column is flush with the third dielectric layer.

[0015] In a possible implementation, the solder ball includes a tin ball.

[0016] The embodiment of the present invention provides a chip structure and a chip packaging method, wherein the front pressure points of the chip are connected one-to-one with the back pressure points through a Via through-hole interconnection structure, and the front grounding metallization area is correspondingly connected with the back grounding metallization area through the Via through-hole interconnection structure, so that the front pressure points and the front grounding metallization area are led out to the back, wherein the back pressure points are used as contact terminals for signal transmission with an external circuit and are connected to the package of the external circuit, thereby increasing the distance between the packaged radio frequency circuit and the circuit topology structure of the front side of the chip, ensuring that the packaged radio frequency circuit and the circuit topology structure of the front side of the chip have a certain distance, preventing the lines of the redistribution layer from interfering with useful signals, avoiding electromagnetic coupling, and ensuring the transmission characteristics of microwave signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 is a schematic cross-sectional view of a chip structure provided by an embodiment of the present invention; Figure 2 is a front schematic diagram of a chip structure provided by an embodiment of the present invention; Figure 3 is a schematic diagram of the back side of the chip structure provided by an embodiment of the present invention; Figure 4 is a front schematic diagram of the chip structure of Example 1 provided in an embodiment of the present invention; Figure 5 is a flow chart of the implementation of the chip packaging method provided by the embodiment of the present invention; Figure 6 is a schematic diagram of a first dielectric layer provided by an embodiment of the present invention; Figure 7 is a schematic diagram of a cavity according to Embodiment 1 provided in an embodiment of the present invention; Figure 8 is a schematic diagram of a first plastic encapsulation layer provided in an embodiment of the present invention; Fig. 9 is a schematic diagram of a first copper pillar provided in an embodiment of the present invention; Fig.10 is a schematic diagram of a second plastic encapsulation layer provided in an embodiment of the present invention; Fig.11 is a schematic diagram of a second dielectric layer and a second copper pillar provided in an embodiment of the present invention; Fig.12 is a schematic diagram of a redistribution layer provided by an embodiment of the present invention; Fig.13 is a schematic diagram of a third dielectric layer and a third copper pillar provided in an embodiment of the present invention; Fig.14 is a schematic diagram of a metallized contact pad provided by an embodiment of the present invention; Fig.15 It is a schematic diagram of the solder ball provided by the embodiment of the present invention and its external connection. DETAILED DESCRIPTION

[0019] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0020] In order to make the purpose, technical solutions and advantages of the present invention more clear, specific embodiments will be described below in conjunction with the accompanying drawings.

[0021] See also Figure 1-Figure 3 , which shows a schematic diagram of a chip structure provided by an embodiment of the present invention, and is described in detail as follows: The chip structure includes: Chip substrate; A front metallization layer is provided on the front side of the chip substrate, and the front metallization layer includes a front pressure point and a front grounding metallization area; A back metallization layer is provided on the back of the chip substrate, the back metallization layer includes back pressure points and back grounding metallization areas, the front pressure points are arranged one-to-one with the back pressure points, and the back grounding metallization areas are arranged correspondingly with the front grounding metallization areas; A number of Via through-hole interconnect structures are provided in the chip substrate. The front pressure points are connected to the corresponding back pressure points through the Via through-hole interconnect structures. The front grounding metallization area is connected to the back grounding metallization area through the Via through-hole interconnect structures. The back pressure points serve as contact terminals for signal transmission with external circuits.

[0022] In this embodiment, Figure 2 1-7 are positive pressure points, such as the chip's RF input, chip's RF output, gate electrode and drain electrode pressure points. Figure 3 The back metallization layer of the chip is formed by electron beam evaporation, and then the entire metallization layer is isolated into back pressure points and back ground metallization areas through etching process. 1'-7' is the back pressure point. The back pressure points of the chip correspond to the front pressure points one by one, forming new RF input, RF output, gate electrode and drain electrode pressure points, etc., as contact terminals for signal transmission with external circuits. The etched area itself is in a circuit blank area, and then a layer of insulating isolation layer is deposited to cover the etched area to isolate the back pressure points from the surrounding back ground metallization areas. The front pressure point is connected to the back pressure point through the Via layer. The Via layer is realized through a through-hole lithography process. Lithography is performed on the back side of the wafer. A truncated cone-shaped through-hole with a depth equal to the thickness of the chip is formed at the vertical position of the front pressure point through an etching process, and metal is filled in the through-hole to form an interconnection structure. The Via through-hole interconnection structure is used to conduct the circuit located at the front pressure point 1 of the chip to the back pressure point 1' of the chip, and the circuit at the front pressure point 2 is conducted to the back pressure point 2'. And so on, the circuit at the front pressure point 7 is conducted to the back pressure point 7' of the chip. At the same time, as many Via through-holes as possible should be made in the front grounding metallization area and the back grounding metallization area to improve the grounding performance.

[0023] In a possible implementation, the back pressure point is correspondingly arranged directly below the corresponding front pressure point.

[0024] In this embodiment, due to the correspondence between the back pressure points and the front pressure points, the consistency and accuracy of signal transmission can be guaranteed, which is particularly important for high-frequency power chips. Through this design, the thermal conductivity and RF performance of the chip when electrically connected to the external circuit can be improved.

[0025] In a possible implementation manner, the front metallization layer further includes a die, a capacitor, a resistor, and a microstrip line.

[0026] In this embodiment, the chip circuit is connected on the front side to ensure the chip RF performance output, such as Figure 4 As shown, the chip is a power amplifier chip and the tube die is a transistor die.

[0027] In a possible implementation, the front voltage point includes a radio frequency input voltage point, a radio frequency output voltage point, a gate electrode voltage point, and a drain electrode voltage point.

[0028] In this embodiment, Figure 4 The front pressure point 1 in the middle is the RF input port, the front pressure point 2 and the front pressure point 3 are the RF output ports, the front pressure point 4 is the drain electrode pressure point, the front pressure point 5 is the gate electrode pressure point, and the front pressure point 6 and the front pressure point 7 are the switch state control ports.

[0029] The embodiment of the present invention connects the front pressure points of the chip with the back pressure points one by one through the Via through-hole interconnection structure, and the front grounding metallization area is correspondingly connected to the back grounding metallization area through the Via through-hole interconnection structure, so that the front pressure points and the front grounding metallization area are led to the back side, wherein the back pressure points are used as contact terminals for signal transmission with the external circuit and are connected to the package of the external circuit, thereby increasing the distance between the packaged radio frequency circuit and the circuit topology structure of the front side of the chip, ensuring that the packaged radio frequency circuit has a certain distance from the circuit topology structure of the front side of the chip, preventing the lines of the redistribution layer from interfering with useful signals, avoiding electromagnetic coupling, and ensuring the transmission characteristics of microwave signals.

[0030] See also Figure 5 , which shows a flow chart of the implementation of the chip packaging method provided by an embodiment of the present invention, which is described in detail as follows: Step 501, forming a cavity structure on the front circuit surface of the chip, and fixing the cavity just above the active area of ​​the chip.

[0031] In a possible implementation, the cavity structure is constructed by a first dielectric layer, which is disposed above the front surface of the chip, and a cavity structure is formed between the first dielectric layer and the chip; wherein the cross section of the first dielectric layer is n-shaped.

[0032] In a possible implementation manner, the first medium layer is a PI medium.

[0033] In this embodiment, a cavity structure of a certain height is formed on the front circuit surface of the chip using PI medium. After the cavity structure is formed, the cavity is fixed just above the active area of ​​the chip by gluing or applying a certain pressure to protect the active area from being contacted by other media, such as Figure 6 and Figure 7As shown. Since there is an air bridge structure in the active area on the front of the chip, if other substances come into contact with the air bridge structure, it will affect the original performance of the circuit, especially for high-frequency circuits above the Ka band, which are more sensitive and will cause frequency band shift, which has a greater impact on performance. Therefore, it is necessary to use PI medium to form a cavity structure of a certain height to protect the circuit on the front of the chip.

[0034] Step 502: Use composite materials to wrap the entire front and side peripheries of the chip to form a first plastic packaging layer, where the wrapped area covers the front grounding metallization area and the cavity structure.

[0035] In this embodiment, a first plastic packaging layer is disposed on the first dielectric layer and the side surfaces of the chip and on the top of the first dielectric layer.

[0036] In a possible implementation manner, the first plastic encapsulation layer is epoxy resin.

[0037] In this embodiment, epoxy resin is used to reconstruct the entire chip front and side periphery, and the wrapped area includes the front metallization layer and the cavity structure, such as Figure 8 shown.

[0038] Step 503, set a plurality of first copper pillars at the back pressure points and the back grounding metallization area, set a second plastic sealing layer at the bottom of the back of the chip and the bottom of the first plastic sealing layer to wrap the first copper pillars; wherein the second plastic sealing layer is flush with the bottom of the first copper pillars.

[0039] In a possible implementation manner, the first copper column is formed by electroplating.

[0040] In this embodiment, electroplating is a commonly used metal deposition technology that can form a uniform and dense metal layer on various substrates.

[0041] In a possible implementation manner, the second plastic encapsulation layer is epoxy resin.

[0042] In this embodiment, a first copper pillar of a certain height is formed at the corresponding position at the back pressure point and the back grounding metallization area by electroplating filling. To enhance the grounding effect, as many first copper pillars as possible should be set in the back grounding metallization area. The entire back side of the chip is wrapped with epoxy resin molding material, and the wrapped area covers the back pressure point, the back grounding metallization area and the first copper pillar. The second molding layer is ground and thinned until the first copper pillar wrapped in the molding material is exposed. After grinding, the second molding layer covers the back of the chip, and the height is consistent with the first copper pillar. Fig. 9 and Fig.10 shown.

[0043] Step 504, disposing a second dielectric layer at the bottom of the second plastic packaging layer, disposing a plurality of second copper pillars in the second dielectric layer, and connecting the second copper pillars to the first copper pillars in a one-to-one correspondence.

[0044] In a possible implementation manner, the second medium layer is a PI medium.

[0045] In this embodiment, the PI medium is polyimide, which is a high-performance engineering plastic with good heat resistance, insulation and mechanical strength, and is suitable for the field of electronic packaging.

[0046] In a possible implementation, a plurality of second copper pillars are disposed in the second dielectric layer, and the specific processing is as follows: developing and exposing the positions of the second dielectric layer corresponding to the first copper pillars to expose the first copper pillars; and ion sputtering and metallization filling are performed at the bottom of the first copper pillars to obtain second copper pillars.

[0047] In this embodiment, the second plastic encapsulation layer is covered and wrapped with PI medium to form a second dielectric layer of a certain height. A developing and exposure process is performed at the corresponding position of the first copper column to expose the bottom surface of the first copper column, and then an ion sputtering process is performed at a vertical position of the first copper column to metallize and fill to form a second copper column, thereby realizing the interconnection structure of the first copper column and the second copper column, such as Fig.11 shown.

[0048] Step 505, providing a redistribution layer at the bottom of the second dielectric layer; wherein the wirings of the redistribution layer are correspondingly connected to the second copper pillars.

[0049] In a possible implementation, a redistribution layer is provided at the bottom of the second dielectric layer, and the specific process is as follows: ion sputtering is performed on the surface of the second dielectric layer to provide the redistribution layer, and wiring is performed on the redistribution layer.

[0050] In this embodiment, ion sputtering is performed on the surface of the second dielectric layer, and the redistribution layer RDL routing is designed to lead out the back pressure points of the chip to achieve the purpose of radio frequency interconnection. Fig.12 As shown, the corresponding relationship of the lead-out pressure points is: 1-11, 2-22 and so on. The specific routing form is arranged according to the actual circuit. 11 and 22 are the wiring of the redistribution layer.

[0051] Step 506, a third dielectric layer is provided at the bottom of the second dielectric layer and the redistribution layer, a plurality of third copper pillars are provided in the third dielectric layer, and the wirings of the redistribution layer are connected to the third copper pillars accordingly.

[0052] In a possible implementation manner, the third medium layer is a PI medium.

[0053] In a possible implementation, a plurality of third copper pillars are provided in the third dielectric layer, and the specific processing is as follows: exposure and development are performed at positions of the third dielectric layer corresponding to the wiring ends of the redistribution layer to expose the wiring ends of the redistribution layer; ion sputtering and metallization filling are performed at the wiring ends of the redistribution layer to obtain third copper pillars.

[0054] In a possible implementation manner, the bottom of the third copper column is flush with the third dielectric layer.

[0055] In this embodiment, the second dielectric layer and the redistribution layer RDL wiring are covered and wrapped by the third dielectric layer; the third copper pillar is formed by performing an exposure and development process corresponding to the end of the redistribution layer RDL wiring in the third dielectric layer, and performing an ion sputtering process, and metallization filling, so as to realize the interconnection structure of the redistribution layer RDL wiring and the third copper pillar, such as Fig.13 shown.

[0056] Step 507: a plurality of metallized contact pads are disposed at the bottom of the third copper pillar, and solder balls are disposed at the bottom of the metallized contact pads.

[0057] In this embodiment, ion sputtering is performed on the surface of the third dielectric layer to design a metallized contact pad, which is called a UBM layer. When designing the UBM layer, all the space on the surface of the third dielectric layer should be fully utilized to enlarge the lead-out pad to have a larger pad plane size. The corresponding relationship of the lead-out pressure points is: 1-11', 2-22', etc. Fig.14 As shown, 11 ′ and 22 ′ are both metallized contact pads.

[0058] In a possible implementation manner, the solder ball includes a tin ball.

[0059] In this embodiment, the ball is planted on the metallized contact pad to ensure a large solder ball volume, thereby increasing the contact area, improving the thermal conductivity and radio frequency performance of the electrical connection with the external PCB board, such as Fig.15 In the field of electronic packaging, solder balls are usually used for electrical connection between chips and external circuits (such as PCB boards), and tin balls are one of the most common solder ball materials because of their good conductivity and welding properties.

[0060] The embodiment of the present invention connects the front pressure points of the chip with the back pressure points one by one through the Via through-hole interconnection structure, and the front grounding metallization area is correspondingly connected to the back grounding metallization area through the Via through-hole interconnection structure, so that the front pressure points and the front grounding metallization area are led to the back side, wherein the back pressure points are used as contact terminals for signal transmission with the external circuit and are connected to the package of the external circuit, thereby increasing the distance between the packaged radio frequency circuit and the circuit topology structure of the front side of the chip, ensuring that the packaged radio frequency circuit has a certain distance from the circuit topology structure of the front side of the chip, preventing the lines of the redistribution layer from interfering with useful signals, avoiding electromagnetic coupling, and ensuring the transmission characteristics of microwave signals.

[0061] Different from conventional plastic packaging structures, the present invention takes into account the existence of an air bridge structure in the front circuit of the power chip. By gluing or applying a certain pressure, the cavity structure formed by PI or other similar media is fixed at the corresponding position of the chip active area to protect the active area from being contacted by other media, thereby ensuring the original performance of the chip circuit and avoiding frequency band deviation of the high-frequency circuit.

[0062] Since the power consumption of power devices is very large, conventional solder balls or solder bumps are usually directly soldered, and the solder joints are small in size and have limited contact areas, which easily lead to high impedance and low thermal conductivity effects. The present invention proposes a wafer-level packaging method with a larger soldering contact area, in which contact pads led out by multi-layer copper pillars are extended to the edge layout, so that contact pads with larger planar dimensions can ensure a larger contact area when contacting the PCB circuit board with solder balls, thereby improving the thermal conductivity performance when the chip is electrically connected to the external circuit.

[0063] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip structure, characterized in that: include: Chip substrate; A front metallization layer is provided on the front side of the chip substrate, and the front metallization layer includes a front pressure point and a front grounding metallization area; A back metallization layer is provided on the back of the chip substrate, the back metallization layer includes back pressure points and back grounding metallization areas, the front pressure points are arranged in a one-to-one correspondence with the back pressure points, and the back grounding metallization areas are arranged in a corresponding manner with the front grounding metallization areas; A plurality of Via through-hole interconnect structures are provided in the chip substrate, the front pressure points are connected to the corresponding back pressure points through the Via through-hole interconnect structures, the front grounding metallization area is connected to the back grounding metallization area through the Via through-hole interconnect structures, and the back pressure points serve as contact terminals for signal transmission with external circuits.

2. The chip structure according to claim 1, characterized in that: The back pressure point is correspondingly arranged directly below the corresponding front pressure point.

3. The chip structure according to claim 1, characterized in that: The front metallization layer also includes a tube die, a capacitor, a resistor and a microstrip line.

4. The chip structure according to claim 1, characterized in that: The front voltage points include a radio frequency input voltage point, a radio frequency output voltage point, a gate electrode voltage point and a drain electrode voltage point.

5. A chip packaging method, characterized in that: A chip implementation based on the chip structure according to any one of claims 1 to 4, comprising: Forming a cavity structure on the front circuit surface of the chip, and fixing the cavity just above the active area of ​​the chip; The composite material is used to wrap the entire front and side periphery of the chip to form a first plastic packaging layer, and the wrapped area covers the front grounding metallization area and the cavity structure; A plurality of first copper pillars are arranged at the back pressure points and the back grounding metallization area, and a second plastic sealing layer is arranged at the bottom of the back of the chip and the bottom of the first plastic sealing layer to wrap the first copper pillars; wherein the second plastic sealing layer is flush with the bottom of the first copper pillars; A second dielectric layer is disposed at the bottom of the second plastic sealing layer, a plurality of second copper pillars are disposed in the second dielectric layer, and the second copper pillars are connected to the first copper pillars in a one-to-one correspondence; A redistribution layer is provided at the bottom of the second dielectric layer; wherein the wiring of the redistribution layer is connected to the second copper pillars correspondingly; A third dielectric layer is provided at the bottom of the second dielectric layer and the redistribution layer, a plurality of third copper pillars are provided in the third dielectric layer, and the wirings of the redistribution layer are connected to the third copper pillars correspondingly; A plurality of metallized contact pads are arranged at the bottom of the third copper column, and solder balls are arranged at the bottom of the metallized contact pads.

6. The chip packaging method according to claim 5, characterized in that: The cavity structure is constructed by a first dielectric layer; The first dielectric layer, the second dielectric layer and the third dielectric layer are all PI dielectrics; The first plastic encapsulation layer and the second plastic encapsulation layer are both epoxy resin.

7. The chip packaging method according to claim 5, characterized in that: The first copper column is formed by electroplating; The step of providing a plurality of second copper pillars in the second dielectric layer comprises: Performing development and exposure at a position of the second dielectric layer corresponding to the first copper pillar to expose the first copper pillar; Performing ion sputtering and metallization filling at the bottom of the first copper column to obtain the second copper column; The third copper pillars are arranged in the third dielectric layer, including: Expose and develop at a position of the third dielectric layer corresponding to a wiring end of the redistribution layer to expose the wiring end of the redistribution layer; Ion sputtering and metallization filling are performed on the wiring ends of the redistribution layer to obtain the third copper column.

8. The chip packaging method according to claim 5, characterized in that: The step of providing a redistribution layer at the bottom of the second dielectric layer comprises: Ion sputtering is performed on the surface of the second dielectric layer to provide a redistribution layer, and wiring is performed on the redistribution layer.

9. The chip packaging method according to claim 5, characterized in that: The bottom of the third copper column is flush with the third dielectric layer.

10. The chip packaging method according to claim 5, characterized in that: The solder balls include tin balls.

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