Semiconductor light-emitting structure and method for preparing the same

Abstract

The present invention provides a semiconductor light-emitting structure and a method for preparing the same. The semiconductor light-emitting structure includes: a photonic crystal layer, the photonic crystal layer includes a first semiconductor layer, the first semiconductor layer has grooves, the first semiconductor layer includes multiple sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, the materials of adjacent sub-semiconductor layers are different, and the thickness of each sub-semiconductor layer is less than or equal to 100 nm; wherein, the width of the groove has a minimum value at a first position in the direction perpendicular to the semiconductor substrate layer, and the distance from the first position to the semiconductor substrate layer is greater than the distance from one end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in the direction perpendicular to the semiconductor substrate layer, and the distance from the second position to the semiconductor substrate layer is less than the distance from one end of the groove away from the semiconductor substrate layer to the semiconductor substrate layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor light-emitting structure and a preparation method thereof. Background Art

[0002] Semiconductor lasers are widely used in the modern optoelectronics industry. Introducing embedded periodic photonic crystals in semiconductor lasers is a general method to effectively control the light field mode and manufacture various high-performance semiconductor lasers. In principle, by preparing a periodic air hole structure with high refractive index contrast on semiconductor epitaxial materials, the photon localization effect of nanoscale photonic crystals is used to form a standing wave cavity to generate laser output. Summary of the invention

[0003] Therefore, the technical problem to be solved by the present invention is how to improve the light field mode control capability of a semiconductor light emitting structure, thereby providing a semiconductor light emitting structure and a preparation method thereof.

[0004] The present application provides a semiconductor light-emitting structure, comprising: a semiconductor substrate layer; an active layer located on one side of the semiconductor substrate layer; and a photonic crystal layer located on the side of the active layer away from the semiconductor substrate layer, wherein the photonic crystal layer comprises a first semiconductor layer, wherein the first semiconductor layer comprises a plurality of spaced grooves, the plurality of grooves are arranged periodically, and the grooves extend from a surface of the first semiconductor layer away from the active layer to the first semiconductor layer; wherein the first semiconductor layer comprises a plurality of sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, wherein adjacent sub-semiconductor layers are made of different materials, and the thickness of each sub-semiconductor layer is less than or equal to 100 nm; wherein the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from one end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the second position to the semiconductor substrate layer is less than the spacing distance from one end of the groove away from the semiconductor substrate layer to the semiconductor substrate layer.

[0005] Optionally, the photonic crystal layer also includes: a second semiconductor layer, which is located on a side surface of the first semiconductor layer facing away from the active layer between adjacent grooves and extends to an inner wall of the groove; an area of ​​the groove surrounded by a surface of the second semiconductor layer facing away from the first semiconductor layer is a gap.

[0006] Optionally, the width of the groove decreases in the direction from the semiconductor substrate layer to the active layer, and the first position passes through one end of the groove facing away from the semiconductor substrate layer.

[0007] Optionally, the width of the groove first decreases and then increases in the direction from the semiconductor substrate layer to the active layer, and the first position is between one end of the groove facing away from the semiconductor substrate layer and one end of the groove facing the semiconductor substrate layer.

[0008] Optionally, the width of the groove first increases and then decreases in the direction from the semiconductor substrate layer to the active layer, and the second position is between one end of the groove facing away from the semiconductor substrate layer and one end of the groove facing the semiconductor substrate layer.

[0009] Optionally, the material of the sub-semiconductor layer includes one of ternary-quaternary compound semiconductor materials, insulating dielectric materials, and metal materials.

[0010] This application also provides a method for manufacturing a semiconductor light-emitting structure, including: forming an active layer on one side of a semiconductor substrate layer; forming a photonic crystal layer on a side of the active layer facing away from the semiconductor substrate layer; wherein, the step of forming the photonic crystal includes: forming a first semiconductor layer on a side of the active layer facing away from the semiconductor substrate layer, the first semiconductor layer includes multiple layers of sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, and the materials of adjacent sub-semiconductor layers are different; forming a plurality of spaced grooves, the plurality of grooves are arranged periodically, the grooves extend from a surface of the first semiconductor layer facing away from the active layer into the first semiconductor layer, during the process of forming the grooves, the etching rates of adjacent sub-semiconductor layers are different, and the thickness of each sub-semiconductor layer is less than or equal to 100 nm; wherein, the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and the distance from the first position to the semiconductor substrate layer is greater than the distance from one end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and the distance from the second position to the semiconductor substrate layer is less than the distance from one end of the groove facing away from the semiconductor substrate layer to the semiconductor substrate layer.

[0011] Optionally, the step of forming the groove includes: forming a patterned mask layer on a side of the first semiconductor layer facing away from the active layer; etching the first semiconductor layer using the mask layer as a mask; removing the mask layer; wherein, when the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, during the process of etching the first semiconductor layer using the mask layer as a mask, the etching selectivity of the sub-semiconductor layer relative to the mask layer decreases in a direction from the semiconductor substrate layer to the active layer, or the etching selectivity of the sub-semiconductor layer relative to the mask layer first decreases and then increases in a direction from the semiconductor substrate layer to the active layer; wherein, when the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, during the process of etching the first semiconductor layer using the mask layer as a mask, the etching selectivity of the sub-semiconductor layer relative to the mask layer first increases and then decreases in a direction from the semiconductor substrate layer to the active layer.

[0012] Optionally, forming the photonic crystal layer further includes: forming a second semiconductor layer, the second semiconductor layer being located on a surface of the first semiconductor layer on a side facing away from the active layer between adjacent grooves and extending to an inner wall of the groove; a region surrounded by a surface of the second semiconductor layer facing away from the first semiconductor layer in the groove is a void.

[0013] Optionally, for adjacent sub-semiconductor layers, the absolute value of the difference between the etching rates of adjacent sub-semiconductor layers and the etching rate of any one of the sub-semiconductor layers is greater than or equal to 20%.

[0014] The technical solution of the present invention has the following beneficial effects:

[0015] The semiconductor light-emitting structure provided by the technical solution of the present invention, the first semiconductor layer includes multiple sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, the materials of adjacent sub-semiconductor layers are different, and the thickness of each sub-semiconductor is less than or equal to 100 nm. By regulating the etching rates of different sub-semiconductor layers, the morphology of the groove is regulated, and the ability to regulate the light field mode is improved.

[0016] Further, the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from the end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the second position to the semiconductor substrate layer is less than the spacing distance from the end of the groove away from the semiconductor substrate layer to the semiconductor substrate layer. Based on the groove with special morphology, the volume of the gap is increased, the duty cycle of the gap is improved, and the light field mode control capability is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic structural diagram of a semiconductor light emitting structure according to an embodiment of the present application;

[0019] Figure 2 A schematic structural diagram of a semiconductor light emitting structure according to another embodiment of the present application;

[0020] Figure 3 A schematic structural diagram of a semiconductor light emitting structure according to another embodiment of the present application;

[0021] Figure 4 is a schematic structural diagram of a semiconductor light-emitting structure after forming a first semiconductor layer;

[0022] Figure 5 for Figure 4 A schematic structural diagram of the first semiconductor layer;

[0023] Figure 6 For Figure 4 A schematic diagram of a structure after a groove is formed on the basis of the present invention;

[0024] Figure 7 For Figure 6 A schematic diagram of a structure after a second semiconductor layer is formed on the basis of the above;

[0025] Figure 8 For Figure 7 Schematic diagram of the structure after the Bragg reflector is formed on the basis of. DETAILED DESCRIPTION

[0026] In order to enhance the longitudinal radiation constant of the photonic crystal and thus improve the output power of the semiconductor laser, a scheme is proposed. Specifically, the longitudinal asymmetry of the air holes is regulated, and the etched air holes are further buried by using the secondary epitaxial technology. However, for a single semiconductor material, the overall etching rate of the semiconductor material is similar. Since the top and bottom of the semiconductor material have the same etching selectivity ratio, and the etching time at the top is long while the etching time at the bottom is short, the morphology of the etched air holes will show the characteristics of wide at the top and narrow at the bottom. A relatively thick secondary epitaxial growth is required to completely bury the wide air holes at the top, and the long epitaxial growth time causes the semiconductor material to be redeposited inside the air holes, resulting in a reduction in the pore volume of the photonic crystal after secondary epitaxy. The volume reduction will affect the duty cycle and morphology of the photonic crystal, causing changes in the energy band and output spectrum, and reducing the ability to regulate the optical field mode.

[0027] On this basis, the present invention provides a semiconductor light-emitting structure and a preparation method thereof, which improve the ability to regulate the optical field mode of the semiconductor light-emitting structure.

[0028] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0029] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0030] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0031] An embodiment of the present invention provides a semiconductor light-emitting structure, referring to Figure 1 、 Figure 2 and Figure 3 , including:

[0032] A semiconductor substrate layer 100;

[0033] An active layer 120 located on one side of the semiconductor substrate layer 100;

[0034] A photonic crystal layer 130 located on a side of the active layer 120 facing away from the semiconductor substrate layer 100. The photonic crystal layer 130 includes a first semiconductor layer 1300, and a plurality of spaced grooves 1301 are formed in the first semiconductor layer 1300 (refer to Figure 6 ), the plurality of grooves 1301 are arranged periodically, and the grooves 1301 extend from a surface of the first semiconductor layer 1300 facing away from the active layer 120 into the first semiconductor layer 1300; wherein, the first semiconductor layer 1300 includes a plurality of sub-semiconductor layers 1300a stacked in a direction perpendicular to the semiconductor substrate layer 100 (refer to Figure 5 ), materials of adjacent sub-semiconductor layers 1300a are different, and the thickness of each sub-semiconductor layer 1300a is less than or equal to 100 nm.

[0035] Wherein, the width of the groove 1301 has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer 100, and the distance from the first position to the semiconductor substrate layer 100 is greater than the distance from an end of the groove 1301 facing the semiconductor substrate layer 100 to the semiconductor substrate layer 100; or, the width of the groove 1301 has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer 100, and the distance from the second position to the semiconductor substrate layer 100 is less than the distance from an end of the groove 1301 facing away from the semiconductor substrate layer 100 to the semiconductor substrate layer 100.

[0036] In this embodiment, the first semiconductor layer 1300 includes a plurality of sub-semiconductor layers 1300a stacked in a direction perpendicular to the semiconductor substrate layer 100, materials of adjacent sub-semiconductor layers 1300a are different, and the thickness of each sub-semiconductor layer is less than or equal to 100 nm. By regulating the etching rates of different sub-semiconductor layers 1300a, precise regulation of the morphology of the grooves is achieved, and the ability to regulate the optical field mode is improved.

[0037] In this embodiment, the semiconductor light-emitting structure includes a surface-emitting semiconductor laser.

[0038] In this embodiment, the photonic crystal layer further includes: a second semiconductor layer 1302, the second semiconductor layer 1302 is located on a surface of the first semiconductor layer 1300 between adjacent grooves facing away from the active layer 120 and extends to the inner wall of the groove 1301.

[0039] In one embodiment, the material of the second semiconductor layer 1302 is different from the material of the first semiconductor layer 1300.

[0040] In one embodiment, the refractive index of the second semiconductor layer 1302 is higher than that of the first semiconductor layer 1300. In other embodiments, the refractive index of the second semiconductor layer is lower than or equal to that of the first semiconductor layer.

[0041] The region of the groove 1301 surrounded by the surface of the second semiconductor layer 1302 facing away from the first semiconductor layer 1300 is referred to as the void W. A plurality of voids W are periodically arranged in a direction parallel to the surface of the semiconductor substrate layer 100. The voids W are used for transmitting light of a specific wavelength, making the wavelength of the light emitted by the semiconductor light-emitting structure more concentrated. Due to the precise control of the morphology of the groove, based on the groove with a special morphology, the volume of the void W is increased and the duty cycle of the void W is improved, enhancing the ability to control the light field mode.

[0042] In one embodiment, the material of the sub-semiconductor layer 1300a includes one of a III-V compound semiconductor material, an insulating dielectric material, and a metal material. The III-V compound semiconductor material includes, but is not limited to, GaAs, InP, GaN, and GaSb. The insulating dielectric material is, for example, silicon oxide or silicon nitride. The metal material is, for example, titanium, platinum, or gold.

[0043] In one embodiment, the thickness of each sub-semiconductor layer 1300a is less than or equal to 100 nm, such as 1 nm, 10 nm, 50 nm, or 100 nm. By reducing the thickness of each sub-semiconductor layer 1300a, the ability to control the morphology of the groove 1301 can be improved. The thickness of the sub-semiconductor layer 1300a is the dimension in the direction perpendicular to the semiconductor substrate layer.

[0044] In one embodiment, the material of the second semiconductor layer 1302 includes Al x1 Ga 1-x1 As. In other embodiments, other materials can also be selected for the second semiconductor layer.

[0045] In one embodiment, referring to Figure 1 and Figure 3 , the width of the groove 1301 has a minimum value at a first position in the direction perpendicular to the semiconductor substrate layer 100, and the distance from the first position to the semiconductor substrate layer is greater than the distance from the end of the groove 1301 facing the semiconductor substrate layer 100 to the semiconductor substrate layer 100.

[0046] When the width of the groove 1301 has a minimum value at a first position in the direction perpendicular to the semiconductor substrate layer 100, in a specific embodiment, referring to Figure 1 and Figure 3, the width of the gap W has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer 100, and the distance from the first position to the semiconductor substrate layer is greater than the distance from one end of the gap W facing the semiconductor substrate layer 100 to the semiconductor substrate layer 100; in another specific embodiment, the width of the gap W first increases and then decreases in a direction from the semiconductor substrate layer 100 to the active layer 120.

[0047] In one embodiment, referring to Figure 1 , the width of the groove 1301 decreases in a direction from the semiconductor substrate layer 100 to the active layer 120, and the first position passes through one end of the groove 1301 facing away from the semiconductor substrate layer 100.

[0048] In one embodiment, referring to Figure 3 , the width of the groove 1301 first decreases and then increases in a direction from the semiconductor substrate layer 100 to the active layer 120, and the first position is located between one end of the groove 1301 facing away from the semiconductor substrate layer 100 and one end of the groove 1301 facing the semiconductor substrate layer 100.

[0049] In one embodiment, referring to Figure 2 , the width of the groove 1301 has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer 100, and the distance from the second position to the semiconductor substrate layer 100 is less than the distance from one end of the groove 1301 facing away from the semiconductor substrate layer 100 to the semiconductor substrate layer 100.

[0050] When the width of the groove 1301 has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer 100, in a specific embodiment, referring to Figure 2 , the width of the gap W has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer 100, and the distance from the second position to the semiconductor substrate layer 100 is less than the distance from one end of the gap W facing away from the semiconductor substrate layer 100 to the semiconductor substrate layer 100; in another specific embodiment, the width of the gap W first increases and then decreases in a direction from the semiconductor substrate layer 100 to the active layer 120.

[0051] In one embodiment, the width of one end of the gap W facing away from the semiconductor substrate layer 100 is 100 nanometers to 200 nanometers, such as 100 nanometers, 150 nanometers or 200 nanometers.

[0052] Referring to Figure 2, the width of the groove 1301 first increases and then decreases in the direction from the semiconductor substrate layer 100 to the active layer 120, and the second position is between the end of the groove 1301 facing away from the semiconductor substrate layer 100 and the end of the groove 1301 facing the semiconductor substrate layer 100.

[0053] In one embodiment, the minimum value of the width of the groove 1301 at a first position in the direction perpendicular to the semiconductor substrate layer 100 is 100 nanometers to 200 nanometers, such as 100 nanometers, 150 nanometers or 200 nanometers.

[0054] Reference Figure 1 , the shape of the groove 1301 in the cross-section perpendicular to the semiconductor substrate layer 100 is trapezoidal.

[0055] Reference Figure 2 , the shape of the groove 1301 in the cross-section perpendicular to the semiconductor substrate layer 100 is a convex hexagon.

[0056] Reference Figure 3 , the shape of the groove 1301 in the cross-section perpendicular to the semiconductor substrate layer 100 is dumbbell-shaped.

[0057] In other embodiments, it may also be that: the shape of the groove in the cross-section perpendicular to the semiconductor substrate layer 100 is circular.

[0058] In other embodiments, it may also be that: the shape of the groove in the cross-section perpendicular to the semiconductor substrate layer 100 is oval.

[0059] In this embodiment, the semiconductor light-emitting structure further includes: a Bragg reflector 140 located on the side of the photonic crystal layer 130 facing away from the active layer 120; a carrier transport layer 110 located between the semiconductor substrate layer 100 and the active layer 120, and the doping type of the carrier transport layer 110 is opposite to the doping type of the Bragg reflector 140. For example, the doping type of the Bragg reflector 140 is P-type, and the doping type of the carrier transport layer 110 is N-type.

[0060] In this embodiment, there is no Bragg reflector between the semiconductor substrate layer 100 and the active layer 120. The light emitted by the active layer 120 is transmitted to the Bragg reflector 140 and reflected by the Bragg reflector 140, and then exits from the semiconductor substrate 100 to the side of the semiconductor substrate 100 facing away from the active layer 120, and the photonic crystal layer 130 selects the wavelength of the light.

[0061] In other embodiments, the semiconductor light-emitting structure further includes: a bottom Bragg reflector located between the semiconductor substrate layer and the active layer, and the reflectivity of the bottom Bragg reflector is greater than the reflectivity of the Bragg reflector.

[0062] The present application also provides a method for manufacturing a semiconductor light-emitting structure, including: forming an active layer on one side of a semiconductor substrate layer; forming a photonic crystal layer on a side of the active layer facing away from the semiconductor substrate layer; wherein, the step of forming the photonic crystal includes: forming a first semiconductor layer on a side of the active layer facing away from the semiconductor substrate layer, the first semiconductor layer including multiple sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, and materials of adjacent sub-semiconductor layers being different; forming a plurality of spaced grooves, the plurality of grooves being arranged periodically, the grooves extending from a surface of the first semiconductor layer facing away from the active layer into the first semiconductor layer, and during the process of forming the grooves, etching rates of adjacent sub-semiconductor layers are different, and a thickness of each sub-semiconductor layer is less than or equal to 100 nm; wherein, the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and a distance from the first position to the semiconductor substrate layer is greater than a distance from an end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and a distance from the second position to the semiconductor substrate layer is less than a distance from an end of the groove facing away from the semiconductor substrate layer to the semiconductor substrate layer.

[0063] In this embodiment, etching rates of adjacent sub-semiconductor layers are different, and a thickness of each sub-semiconductor layer is less than or equal to 100 nm. By regulating an arrangement manner of the sub-semiconductor layers, selective etching of the grooves is further realized, and the groove morphology regulation precision is high and the operation is simple, which can meet the advantages of rapid preparation of the photonic crystal layer.

[0064] In one embodiment, the step of forming the grooves includes: forming a patterned mask layer on a side of the first semiconductor layer facing away from the active layer; etching the first semiconductor layer using the mask layer as a mask; removing the mask layer; wherein, when the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, during the process of etching the first semiconductor layer using the mask layer as a mask, an etching selectivity of the sub-semiconductor layer relative to the mask layer decreases in a direction from the semiconductor substrate layer to the active layer, or, the etching selectivity of the sub-semiconductor layer relative to the mask layer first decreases and then increases in a direction from the semiconductor substrate layer to the active layer; wherein, when the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, during the process of etching the first semiconductor layer using the mask layer as a mask, the etching selectivity of the sub-semiconductor layer relative to the mask layer first increases and then decreases in a direction from the semiconductor substrate layer to the active layer.

[0065] In one embodiment, forming the photonic crystal layer further includes: forming a second semiconductor layer on a surface of the first semiconductor layer between adjacent grooves and facing away from the active layer, and the second semiconductor layer extends to an inner wall of the groove; a region surrounded by a surface of the second semiconductor layer facing away from the first semiconductor layer in the groove is a void. Due to the above characteristics of the width of the groove, the amount of the second semiconductor layer filled in the groove is small, which can achieve rapid formation of the second semiconductor layer and increase the duty cycle of the void.

[0066] Next, refer to Figures 4 to 8 to introduce the preparation process of forming the semiconductor structure.

[0067] Refer to Figure 4 , a charge transport layer 110 is formed on one side of the semiconductor substrate layer 100; an active layer 120 is formed on a side of the charge transport layer 110 facing away from the semiconductor substrate layer 100.

[0068] In this embodiment, it further includes: forming a photonic crystal layer on a side of the active layer facing away from the semiconductor substrate layer; wherein, the steps of forming the photonic crystal include: forming a first semiconductor layer on a side of the active layer facing away from the semiconductor substrate layer, and the first semiconductor layer includes multiple sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, and materials of adjacent sub-semiconductor layers are different.

[0069] Refer to Figure 4 , a first semiconductor layer 1300 is formed on a side of the active layer 120 facing away from the semiconductor substrate layer 100.

[0070] In one embodiment, the process of forming the first semiconductor layer 1300 is a deposition process, such as metal-organic chemical vapor deposition process, molecular beam epitaxy process, plasma-enhanced chemical vapor deposition process, and atomic layer deposition process.

[0071] Refer to Figure 5 , the first semiconductor layer 1300 includes multiple sub-semiconductor layers 1300a stacked in a direction perpendicular to the semiconductor substrate layer 100, materials of adjacent sub-semiconductor layers 1300a are different, and the thickness of each sub-semiconductor is less than or equal to 100 nm.

[0072] In one embodiment, multiple sub-semiconductor layers 1300a are continuously formed in the same chamber.

[0073] Refer to Figure 6, a plurality of spaced grooves 1301 are formed, and the plurality of grooves 1301 are arranged periodically. The grooves 1301 extend from the surface of the first semiconductor layer 1300 facing away from the active layer 120 into the first semiconductor layer 1300. During the formation of the grooves 1301, the etching rates of adjacent sub-semiconductor layers 1300a are different, and the thickness of each sub-semiconductor layer 1300a is less than or equal to 100 nm.

[0074] In one embodiment, the process of forming the grooves 1301 is an etching process, and the etching process includes a combination of one or more of a wet etching process and a dry etching process. For example, the wet etching process can select an acidic etching process or an alkaline etching process.

[0075] Figure 6 As an example, at a first position in the direction perpendicular to the semiconductor substrate layer, the width of the groove has a minimum value, and the distance between the first position and the semiconductor substrate layer is greater than the distance between the end of the groove facing the semiconductor substrate layer and the semiconductor substrate layer. In other embodiments, at a second position in the direction perpendicular to the semiconductor substrate layer, the width of the groove has a maximum value, and the distance between the second position and the semiconductor substrate layer is less than the distance between the end of the groove facing away from the semiconductor substrate layer and the semiconductor substrate layer.

[0076] The description of the groove refers to the description of the foregoing embodiment and will not be elaborated here.

[0077] In one embodiment, the steps of forming the groove include: forming a patterned mask layer on the side of the first semiconductor layer 1300 facing away from the active layer 120; etching the first semiconductor layer 1300 using the mask layer as a mask; removing the mask layer; wherein, when the width of the groove has a minimum value at a first position in the direction perpendicular to the semiconductor substrate layer, during the process of etching the first semiconductor layer 1300 using the mask layer as a mask, the etching selectivity of the sub-semiconductor layer 1300a relative to the mask layer decreases in the direction from the semiconductor substrate layer 100 to the active layer 120.

[0078] In other embodiments, when the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, during the process of etching the first semiconductor layer 1300 using the mask layer as a mask, the etching selectivity of the sub-semiconductor layer with respect to the mask layer first decreases and then increases in a direction from the semiconductor substrate layer to the active layer; in other embodiments, when the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, during the process of etching the first semiconductor layer using the mask layer as a mask, the etching selectivity of the sub-semiconductor layer with respect to the mask layer first increases and then decreases in a direction from the semiconductor substrate layer to the active layer.

[0079] In one embodiment, for adjacent sub-semiconductor layers, the ratio of the absolute value of the difference between the etching rates of adjacent sub-semiconductor layers to the etching rate of any one of the sub-semiconductor layers is greater than or equal to 20%.

[0080] Reference Figure 7 , a second semiconductor layer 1302 is formed. The second semiconductor layer 1302 is located on a surface of the first semiconductor layer 1300 on a side away from the active layer 120 between adjacent grooves and extends to the inner wall of the groove; a region of the groove surrounded by a surface of the second semiconductor layer 1302 away from the first semiconductor layer 1300 is a void W.

[0081] In one embodiment, the process of forming the second semiconductor layer 1302 includes an epitaxial growth process. In one embodiment, the process of forming the second semiconductor layer 1302 is, for example, a metalorganic chemical vapor deposition process. The material and refractive index of the second semiconductor layer 1302 are described with reference to the description of the foregoing embodiments.

[0082] Since precise control of the topography of the groove is achieved, based on the groove with a special topography, the volume of the void W is increased, the duty cycle of the void W is improved, and the ability to control the optical field mode is enhanced.

[0083] Reference Figure 8 , a Bragg reflector 140 is formed on a side of the photonic crystal layer 130 away from the active layer 120.

[0084] Regarding the material of the Bragg reflector 140, reference is made to the foregoing embodiments.

[0085] In other embodiments, the semiconductor light-emitting structure further includes: a bottom Bragg reflector, located between the semiconductor substrate layer and the active layer, and the reflectivity of the bottom Bragg reflector is greater than the reflectivity of the Bragg reflector.

[0086] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or alterations can be made based on the above description. It is not necessary and impossible to exhaustively list all implementation manners here. And the obvious changes or alterations derived therefrom still fall within the protection scope of the present invention.

Claims

1. A semiconductor light emitting structure, characterized in that: include: Semiconductor substrate layer; an active layer located on one side of the semiconductor substrate layer; A photonic crystal layer located on a side of the active layer away from the semiconductor substrate layer, the photonic crystal layer comprising a first semiconductor layer, the first semiconductor layer having a plurality of spaced grooves, the plurality of grooves being arranged periodically, the grooves extending from a surface of the first semiconductor layer away from the active layer into the first semiconductor layer; Wherein, the first semiconductor layer comprises a plurality of sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, adjacent sub-semiconductor layers are made of different materials, and the thickness of each sub-semiconductor layer is less than or equal to 100 nm; Wherein, the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from one end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the second position to the semiconductor substrate layer is less than the spacing distance from one end of the groove facing away from the semiconductor substrate layer to the semiconductor substrate layer.

2. The semiconductor light emitting structure according to claim 1, characterized in that: The photonic crystal layer also includes: a second semiconductor layer, which is located on a side surface of the first semiconductor layer facing away from the active layer between adjacent grooves and extends to the inner wall of the groove; the area of ​​the groove surrounded by the surface of the second semiconductor layer facing away from the first semiconductor layer is a gap.

3. The semiconductor light emitting structure according to claim 1, characterized in that: The width of the groove decreases in a direction from the semiconductor substrate layer to the active layer, and the first position passes through an end of the groove away from the semiconductor substrate layer.

4. The semiconductor light emitting structure according to claim 1, characterized in that: The width of the groove first decreases and then increases in a direction from the semiconductor substrate layer to the active layer, and the first position is located between an end of the groove away from the semiconductor substrate layer and an end of the groove toward the semiconductor substrate layer.

5. The semiconductor light emitting structure according to claim 1, characterized in that: The width of the groove increases first and then decreases in a direction from the semiconductor substrate layer to the active layer, and the second position is located between an end of the groove away from the semiconductor substrate layer and an end of the groove toward the semiconductor substrate layer.

6. The semiconductor light emitting structure according to claim 1, characterized in that: The material of the sub-semiconductor layer includes one of a III-V compound semiconductor material, an insulating dielectric material and a metal material.

7. A method for preparing a semiconductor light-emitting structure, characterized in that: include: forming an active layer on one side of the semiconductor substrate layer; forming a photonic crystal layer on a side of the active layer away from the semiconductor substrate layer; Wherein, the step of forming the photonic crystal comprises: forming a first semiconductor layer on a side of the active layer away from the semiconductor substrate layer, the first semiconductor layer comprising a plurality of sub-semiconductor layers stacked in a direction perpendicular to the semiconductor substrate layer, and adjacent sub-semiconductor layers are made of different materials; forming a plurality of spaced grooves, the plurality of grooves being arranged periodically, the grooves extending from a surface of the first semiconductor layer away from the active layer to the first semiconductor layer, in the process of forming the grooves, etching rates of adjacent sub-semiconductor layers are different, and the thickness of each layer of the sub-semiconductor is less than or equal to 100 nm; Wherein, the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the first position to the semiconductor substrate layer is greater than the spacing distance from one end of the groove facing the semiconductor substrate layer to the semiconductor substrate layer; or, the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, and the spacing distance from the second position to the semiconductor substrate layer is less than the spacing distance from one end of the groove facing away from the semiconductor substrate layer to the semiconductor substrate layer.

8. The method for preparing a semiconductor light emitting structure according to claim 7, characterized in that: The step of forming the groove includes: forming a patterned mask layer on a side of the first semiconductor layer away from the active layer; etching the first semiconductor layer using the mask layer as a mask layer; and removing the mask layer; Wherein, when the width of the groove has a minimum value at a first position in a direction perpendicular to the semiconductor substrate layer, in a process of etching the first semiconductor layer using the mask layer as a mask layer, the etching selectivity of the sub-semiconductor layer relative to the mask layer decreases from the semiconductor substrate layer to the active layer, or the etching selectivity of the sub-semiconductor layer relative to the mask layer first decreases and then increases from the semiconductor substrate layer to the active layer; Among them, when the width of the groove has a maximum value at a second position in a direction perpendicular to the semiconductor substrate layer, in a process of etching the first semiconductor layer using the mask layer as a mask layer, the etching selectivity of the sub-semiconductor layer relative to the mask layer first increases and then decreases in a direction from the semiconductor substrate layer to the active layer.

9. The method for preparing a semiconductor light emitting structure according to claim 7, characterized in that: Forming the photonic crystal layer also includes: forming a second semiconductor layer, wherein the second semiconductor layer is located on a side surface of the first semiconductor layer facing away from the active layer between adjacent grooves and extends to the inner wall of the groove; the area of ​​the groove surrounded by the surface of the second semiconductor layer facing away from the first semiconductor layer is a gap.

10. The method for preparing a semiconductor light emitting structure according to claim 7, characterized in that: For adjacent sub-semiconductor layers, a ratio of an absolute value of a difference between etching rates of adjacent sub-semiconductor layers to an etching rate of any one of the sub-semiconductor layers is greater than or equal to 20%.

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