Power amplification chip and radio frequency front-end module

Abstract

The invention relates to the technical field of radio frequency, in particular to a power amplification chip and a radio frequency front-end module. The power amplification chip and the radio frequency front-end module provided by the embodiment of the invention comprise at least two transistor units and at least two metal components, and each transistor unit comprises at least one amplification transistor and at least one first bias transistor; by arranging the at least two transistor units, the size of the metal component corresponding to the transistor units can be reduced, so that the stress distribution of the metal component is uniform, and the circuit performance and reliability in the power amplification chip are improved; at least one first bias transistor is arranged in each transistor unit, the temperature of the corresponding transistor unit is tracked by the first bias transistor, and a bias signal is provided for the amplification transistor according to the temperature, so that the thermal uniformity of the transistor can be improved; the linearity of the power amplification chip can be improved, and the error vector amplitude of the power amplification chip can be reduced.

Description

Technical Field

[0001] The present application relates to the field of radio frequency technology, and in particular to a power amplifier chip and a radio frequency front-end module. Background Art

[0002] In the background art, a power amplifier chip is provided with a transistor array and a metal component corresponding to the transistor array, and the metal component extends the metallization layer inside the power amplifier chip to the periphery, for example, to export the electrical signal from the transistor inside the power amplifier chip to other component units on the power amplifier chip or component units on the circuit substrate, and the power amplifier chip and the circuit substrate are connected to each other through the metal component. As the size of the transistor array increases, the size of the metal component increases accordingly, resulting in uneven stress distribution of the metal component during chip packaging, and even causing the metal component to be easily cracked due to excessive stress at some positions, which is not conducive to improving the circuit performance and reliability in the power amplifier chip. Summary of the invention

[0003] In view of the above problems, the embodiments of the present application provide a power amplifier chip and a radio frequency front-end module to solve the technical problem that the metal components are prone to cracking due to uneven stress distribution during the packaging of the above-mentioned metal components.

[0004] In a first aspect, an embodiment of the present application provides a power amplifier chip, including:

[0005] At least two transistor units, each of the transistor units includes a plurality of transistors arranged in sequence, at least two of the plurality of transistors are configured as amplifier transistors and at least one is configured as a first bias transistor, wherein the amplifier transistor is used to amplify an input radio frequency signal, and the first bias transistor is used to provide a bias signal for the amplifier transistor;

[0006] A metal component is arranged in a one-to-one correspondence with at least two of the transistor units, and the metal component is electrically connected to at least the first end of each of the amplifying transistors in the transistor unit.

[0007] Optionally, the power amplifier chip integrates a power amplifier circuit and a bias circuit, the power amplifier circuit includes the amplifier transistor, the bias circuit includes the first bias transistor, and the bias circuit is connected to the control terminal of the amplifier transistor to output the bias signal to the amplifier transistor;

[0008] Wherein, the first end of the amplifying transistor is grounded through the corresponding metal component, and the second end of the amplifying transistor is used to output the amplified radio frequency signal.

[0009] Optionally, the first bias transistor is located between two adjacent amplifying transistors; or, each amplifying transistor in the transistor unit is located on the same side of the first bias transistor; or, the number of the first bias transistors in the transistor unit is two, and each amplifying transistor is located between two first bias transistors.

[0010] Optionally, the bias signal includes a bias current, the bias circuit includes a first bias unit and a second bias unit, the first bias unit includes at least the first bias transistor, and the first bias transistor is configured to output a control current following the temperature of the transistor unit to the second bias unit;

[0011] The second bias unit is connected to the control terminal of the amplifying transistor, and is used for generating the bias current according to the control current, and outputting the bias current to the amplifying transistor.

[0012] Optionally, the first bias unit further includes a second bias transistor, a first end of the second bias transistor is connected to the second end of each of the first bias transistors, and a second end of the second bias transistor is connected to the second bias unit.

[0013] Optionally, the second bias unit includes a third bias transistor, a control terminal of the third bias transistor is connected to the second terminal of the second bias transistor, a first terminal of the third bias transistor is connected to the control terminal of the amplifying transistor, and a second terminal of the third bias transistor is used to input a power supply voltage.

[0014] Optionally, the second bias unit includes a plurality of third bias transistors arranged in one-to-one correspondence with the transistor units, the control end of the third bias transistor is connected to the second end of the second bias transistor, the first end of the third bias transistor is connected to the control end of each amplifying transistor in the corresponding transistor unit, and the second end of the third bias transistor is used to input a power supply voltage.

[0015] Optionally, the number of the transistor units is two, namely a first transistor unit and a second transistor unit; the first bias unit includes at least the first bias transistor in the first transistor unit and the first bias transistor in the second transistor unit; the second bias unit is respectively connected to each of the amplifying transistors in the first transistor unit and each of the amplifying transistors in the second transistor unit.

[0016] Optionally, the power amplifier chip is integrated with a plurality of bias circuits arranged in one-to-one correspondence with the transistor units, each of the bias circuits includes a first bias unit and a second bias unit, the first bias unit includes at least the first bias transistor, the first bias transistor is located in the corresponding transistor unit or in other transistor units, and the first bias transistor is configured to output a control current that follows the temperature of the transistor unit in which it is located to the second bias unit;

[0017] The second bias unit is connected to the control terminal of each of the amplifying transistors in the corresponding transistor unit, and is used to generate a bias current according to the control current, and output the bias current to the amplifying transistor.

[0018] Optionally, the number of the transistor units is at least two, including a first transistor unit and a second transistor unit; the bias circuit is provided with at least two, including a first bias circuit and a second bias circuit, the first bias circuit corresponds to the first transistor unit and is used to output the bias current to the amplifying transistor in the first transistor unit, and the second bias circuit corresponds to the second transistor unit and is used to output the bias current to the amplifying transistor in the second transistor unit;

[0019] The first bias transistor of the first bias circuit is located in the first transistor unit; and the first bias transistor of the second bias circuit is located in the second transistor unit.

[0020] Optionally, the number of the transistor units is at least two, including a first transistor unit and a second transistor unit; the bias circuit is provided with at least two, including a first bias circuit and a second bias circuit, the first bias circuit corresponds to the first transistor unit and is used to output the bias current to the amplifying transistor in the first transistor unit, and the second bias circuit corresponds to the second transistor unit and is used to output the bias current to the amplifying transistor in the second transistor unit;

[0021] The first bias transistor of the first bias circuit is located in the second transistor unit; and the first bias transistor of the second bias circuit is located in the first transistor unit.

[0022] Optionally, each bias circuit further includes a second bias transistor arranged corresponding to the first bias transistor, a first end of the second bias transistor is connected to a second end of the first bias transistor, and a second end of the second bias transistor is connected to the second bias unit.

[0023] Optionally, the amplifying transistor is a heterojunction bipolar transistor, the control end of the amplifying transistor is the base, the first end of the amplifying transistor is the emitter, and the second end of the amplifying transistor is the collector.

[0024] Optionally, the first bias transistor is a heterojunction bipolar transistor, the control terminal of the first bias transistor is the base, the first terminal of the first bias transistor is the emitter, the second terminal of the first bias transistor is the collector, and the base of the first bias transistor is connected to the collector;

[0025] Alternatively, the first bias transistor is a diode, the first end of the first bias transistor is a cathode, and the second end of the first bias transistor is an anode.

[0026] Optionally, the first end of the first bias transistor is grounded through the corresponding metal component.

[0027] Optionally, the second bias transistor is a heterojunction bipolar transistor, the control terminal of the second bias transistor is the base, the first terminal of the second bias transistor is the emitter, the second terminal of the second bias transistor is the collector, and the base of the second bias transistor is connected to the collector;

[0028] Alternatively, the second bias transistor is a diode, the first end of the second bias transistor is a cathode, and the second end of the second bias transistor is an anode.

[0029] Optionally, a projection of the metal component on the power amplifier chip along a first direction has an overlapping area with a setting area of ​​the transistor unit, and the first direction is a thickness direction of the power amplifier chip.

[0030] Optionally, a setting area of ​​the transistor unit is located within a projection of the metal component on the power amplifier chip along the first direction.

[0031] In a second aspect, an embodiment of the present application provides a radio frequency front-end module, comprising a circuit substrate and the above-mentioned power amplifier chip arranged on the circuit substrate; the power amplifier chip is provided with a side of a metal component opposite to the circuit substrate, and the metal component is connected to the circuit substrate so as to flip-chip-mount the power amplifier chip on the circuit substrate.

[0032] The power amplifier chip and the radio frequency front-end module provided in the embodiments of the present application include at least two transistor units and metal components arranged in a one-to-one correspondence with the at least two transistor units, at least two of the multiple transistors of each transistor unit are configured as amplifier transistors and at least one is configured as a first bias transistor; by setting at least two transistor units, the size of the metal component corresponding to the transistor unit can be reduced, and the stress distribution of the metal component is uniform, thereby improving the circuit performance and reliability in the power amplifier chip; by setting at least one first bias transistor in the transistor unit, using the first bias transistor to track the temperature of the corresponding transistor unit and providing a bias signal for the amplifier transistor according to the temperature, the thermal uniformity of the transistor can be improved, which is beneficial to improving the linearity of the power amplifier chip and reducing the error vector amplitude of the power amplifier chip.

[0033] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 FIG. 1 is a schematic diagram of the structure of a power amplifier chip according to an embodiment of the present application.

[0035] Figure 2 for Figure 1 A top view of the power amplifier chip shown.

[0036] Figure 3 for Figure 1 The circuit diagram of the power amplifier chip shown.

[0037] Figure 4 for Figure 1 Schematic diagram of the arrangement of transistor units in the power amplifier chip shown.

[0038] Figure 5 for Figure 1 Schematic diagram of the arrangement of transistor units in the power amplifier chip shown.

[0039] Figure 6 for Figure 1 Schematic diagram of the arrangement of transistor units in the power amplifier chip shown.

[0040] Figure 7 for Figure 1 Schematic diagram of the structure of the bias circuit in the power amplifier chip shown.

[0041] Figure 8 for Figure 1 Schematic diagram of the structure of the bias circuit in the power amplifier circuit shown.

[0042] Fig. 9 for Figure 1 Circuit diagram of the bias circuit in the power amplifier chip shown.

[0043] Fig.10 for Figure 1 Circuit diagram of the bias circuit in the power amplifier chip shown.

[0044] Fig.11 for Figure 1 Circuit diagram of the bias circuit in the power amplifier chip shown.

[0045] Fig.12 This is a schematic diagram of the structure of a radio frequency front-end module according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0047] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0048] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0049] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0050] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0051] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0052] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0053] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0054] The present application embodiment provides a power amplifier chip 100, see Figure 1 and Figure 2 As shown, the power amplifier chip 100 includes: at least two transistor units 11 and at least two metal components 12 arranged in a one-to-one correspondence with the at least two transistor units 11 .

[0055] The transistor unit 11 includes a plurality of transistors arranged in sequence, at least two of the plurality of transistors are configured as amplifying transistors Q1 and at least one is configured as a first biasing transistor Q2 .

[0056] The amplifying transistor Q1 is used to amplify the input radio frequency signal, and the first biasing transistor Q2 is used to provide a biasing signal for the amplifying transistor Q1.

[0057] The multiple amplifier transistors Q1 included in the same transistor unit 11 may be connected in parallel with each other, the multiple amplifier transistors Q1 may share the same bias signal, or the multiple amplifier transistors Q1 may respectively receive different bias signals.

[0058] Optionally, the amplifier transistor Q1 may be a triode, a heterojunction bipolar transistor (HBT), a field effect transistor, etc. The amplifier transistor Q1 is integrated in a chip, and the chip may be a chip having a gallium arsenide (GaAs) substrate, or a chip having a gallium nitride (GaN) substrate or a silicon (Si) substrate. Exemplarily, the amplifier transistor Q1 is a heterojunction bipolar transistor integrated on a chip having a gallium arsenide (GaAs) substrate.

[0059] Specifically, the RF signal is input from the control end of the amplifier transistor Q1, and is output from the second end of the amplifier transistor Q1 after amplification. The first end of the amplifier transistor Q1 is grounded. Exemplarily, taking a triode or HBT as an example, the control end of the amplifier transistor Q1 may be a base, the first end may be an emitter, and the second end may be a collector. When the temperature of the amplifier transistor Q1 changes, the conduction voltage between the control end and the first end thereof changes. Specifically, when the temperature of the amplifier transistor Q1 increases, the conduction voltage between the control end and the first end thereof decreases. If a bias signal of the same magnitude is provided to the control end of the amplifier transistor Q1 before and after the temperature change, the characteristic parameters of the amplifier transistor Q1 will be affected, for example, the linearity and error vector amplitude of the power amplification will be affected.

[0060] The first bias transistor Q2 is disposed in a bias circuit, and the bias circuit is used to provide a bias signal for the amplifying transistor Q1. In addition to the first bias transistor Q2, the bias circuit may further include other transistors.

[0061] The type of the first bias transistor Q2 can be the same as the type of the amplifier transistor Q1, for example, the first bias transistor Q2 and the amplifier transistor Q1 are both heterojunction bipolar transistors. In the bias circuit, the control end of the first bias transistor Q2 is connected to its second end, and the first end of the first bias transistor Q2 can be grounded. Exemplarily, the control end of the first bias transistor Q2 can be a base, the first end can be an emitter, and the second end can be a collector. When the temperature of the first bias transistor Q2 changes, the on-state voltage between the control end and the first end changes. Specifically, when the temperature of the first bias transistor Q2 increases, the on-state voltage between the control end and the first end decreases, so that the output voltage and output current of the bias circuit decrease.

[0062] The metal component 12 is arranged in one-to-one correspondence with the transistor unit 11, and the metal component 12 is at least electrically connected to the first end of each amplifier transistor Q1 in the transistor unit 11. Exemplarily, the first end of each amplifier transistor Q1 can be grounded through the corresponding metal component 12. The metal component 12 can also be called a bump, which grows on the surface of the power amplifier chip 100. When the power amplifier chip 100 is flipped on the substrate, the metal component 12 contacts the substrate and is electrically connected to the circuit on the substrate, thereby realizing the connection between the circuit inside the power amplifier chip 100 and the components on the substrate, or realizing the grounding of a specific node inside the power amplifier chip 100.

[0063] In the related art, multiple amplifier transistors connected in parallel are arranged in a row, and the multiple amplifier transistors share a bias signal and correspond to the same metal component. When the number of amplifier transistors is large, the length of the metal component increases, which makes the metal component easy to be damaged during chip packaging.

[0064] In order to solve the above problems, the inventor of the present application first thought of setting two smaller metal components, for example, in order to reduce the size of the metal component, and the multiple amplifier transistors are correspondingly divided into two groups; however, in order to meet the minimum spacing requirements for the metal component setting, there must be a certain interval between the two metal components, and there must be a certain interval between the two groups of amplifier transistors, which will result in inconsistent temperature changes of the two groups of amplifier transistors. If the first bias transistor Q2 is set in the gap area between the two groups of amplifier transistors, since the first bias transistor Q2 is far away from the two groups of amplifier transistors, the bias signal provided to the amplifier transistor cannot be adjusted in real time according to the temperature change of the amplifier transistor, resulting in the gain and / or output power of the two groups of amplifier transistors being affected by temperature changes, thereby affecting the linearity and error vector amplitude of the power amplifier. If the first bias transistor Q2 is set in one of the groups of amplifying transistors, since the temperature changes of the two groups of amplifying transistors are inconsistent, the first bias transistor Q2 can only adjust the output bias signal according to the temperature change of one group of amplifying transistors, but cannot respond to the temperature change of the other amplifying transistor. This will cause the gain and / or output power of at least one group of amplifying transistors to still be affected by the temperature change, and the linearity and error vector amplitude of the power amplifier will still be difficult to meet the requirements.

[0065] Therefore, in this embodiment, by setting at least two transistor units, the size of each transistor unit can be reduced, and then the size of each metal component can be reduced, so that the stress distribution of the metal component is uniform, and the circuit performance and reliability in the power amplifier chip are improved; by setting at least one first bias transistor in the transistor unit, using the first bias transistor to track the temperature of the corresponding transistor unit and providing a bias signal for the amplifier transistor according to the temperature, the bias signal can follow the temperature change of at least two transistor units, so that the bias signal provided to the at least two transistor units is more reasonable, which is beneficial to improving the linearity of the power amplifier chip and reducing the error vector amplitude of the power amplifier chip.

[0066] As an implementation, see Figure 3 As shown, the power amplifier chip 100 integrates a power amplifier circuit 21 and a bias circuit 22 . The power amplifier circuit 21 includes an amplifier transistor Q1 , and the bias circuit 22 includes a first bias transistor Q2 .

[0067] The bias circuit 22 is connected to the control terminal of the amplifier transistor Q1 to output a bias signal to the amplifier transistor Q1. The first terminal of the amplifier transistor Q1 is grounded through the corresponding metal component 12, and the second terminal of the amplifier transistor Q1 is used to output the amplified RF signal.

[0068] In this embodiment, the bias signal provided by the bias circuit to the amplifier transistor is related to the on-voltage of each first bias transistor. Since the first bias transistor has a temperature characteristic that the on-voltage decreases as the temperature increases, and each transistor unit is provided with a first bias transistor, the bias signal output by the bias circuit to the amplifier transistor can follow the temperature of each transistor unit, thereby reducing the influence of temperature changes on the gain and output power of each transistor unit, so as to improve the linearity of the power amplifier chip and reduce the error vector amplitude of the power amplifier chip.

[0069] In some embodiments, the first bias transistor Q2 may be located at any position in the transistor unit 11 , for example, at an edge of the transistor unit 11 , or between two adjacent amplifying transistors Q1 in the transistor unit 11 .

[0070] For example, see Figure 4 As shown, the first bias transistor Q2 is located between two adjacent amplifying transistors Q1. The first bias transistor Q2 can simultaneously follow the temperature change of the amplifying transistors Q1 located on both sides thereof, and has a good temperature tracking effect.

[0071] For example, see Figure 5As shown, the first bias transistor Q2 is located at one edge of the transistor unit 11 along the arrangement direction, and each amplifying transistor Q1 in the transistor unit 11 is located on the same side of the first bias transistor Q2. Under the premise of ensuring the temperature tracking effect of the first bias transistor Q2 on the amplifying transistor Q1, it is convenient to connect the first bias transistor Q2 with other components in the bias circuit.

[0072] For example, see Figure 6 As shown, there are two first bias transistors Q2 in the transistor unit 11, and the two first bias transistors Q2 are located at two edges of the transistor unit 11 along the arrangement direction, and each amplifier transistor Q1 is located between the two first bias transistors Q2. The two first bias transistors Q2 respectively follow the overall temperature change of the plurality of amplifier transistors Q1, which is conducive to further improving the temperature tracking effect, and because the two first bias transistors are located at the edge area of ​​the transistor unit 11, it is convenient to connect the two first bias transistors with other components in the bias circuit.

[0073] It can be understood that, in the same transistor unit, the ambient temperature of each transistor is consistent. In the above embodiments, as long as the first bias transistor Q2 is arranged in the transistor unit and keeps a small distance from at least one amplifying transistor Q1, no matter whether the first bias transistor Q2 is in the central area or the edge area of ​​the transistor unit, the first bias transistor Q2 can achieve temperature tracking for the amplifying transistor in the transistor unit.

[0074] In some embodiments, the bias signal includes a bias current, see Figure 7 As shown, the bias circuit 22 includes a first bias unit 221 and a second bias unit 222 . The first bias unit 221 includes at least a first bias transistor Q2 . The first bias transistor Q2 is configured to output a control current that follows the temperature of the transistor unit 11 to the second bias unit 222 .

[0075] The second bias unit 222 is connected to the control terminal of the amplifying transistor Q1 , and is configured to generate a bias current according to the control current, and output the bias current to the amplifying transistor Q1 .

[0076] In this embodiment, as the temperature of the amplifier transistor increases, the on-state voltage between the control terminal (base) and the first terminal (emitter) of the amplifier transistor decreases. If the bias current of the amplifier transistor remains unchanged, the output current of the second terminal (collector) of the amplifier transistor will increase, that is, the output gain curve of the power amplifier chip is not flat, resulting in a decrease in the linearity of the power amplifier chip and an increase in the error vector amplitude.

[0077] By setting the first bias transistor to follow the temperature change of the amplifying transistor, when the temperature of the amplifying transistor increases, the temperature of the first bias transistor increases accordingly, and the on-voltage between the control terminal (base) and the first terminal (emitter) of the first bias transistor decreases. Since the control terminal (base) and the second terminal (collector) of the first bias transistor are short-circuited, the reduction of the on-voltage causes the voltage of the second terminal (collector) of the first bias transistor to decrease, so that the control current output by the first bias transistor decreases. The second bias unit generates a bias current of the amplifying transistor according to the control current of the first bias transistor, and the bias current decreases accordingly, which can offset the increase in the output current of the amplifying transistor caused by the increase in temperature, improve the flatness of the gain curve of the power amplifier chip, and thus improve the linearity of the power amplifier chip and reduce the error vector amplitude.

[0078] In some embodiments, please refer to Figure 7 As shown, the first bias unit 221 further includes a second bias transistor Q3 , a first end of the second bias transistor Q3 is connected to the second end of each first bias transistor Q2 , and a second end of the second bias transistor Q3 is connected to the second bias unit 222 .

[0079] The control current outputted from the second end of each first bias transistor Q2 follows the transistor unit 11 where it is located, and the current outputted from the second end of the second bias transistor Q3 is the sum of the control currents outputted from the first bias transistors Q2, so the current outputted from the second bias transistor Q3 can follow the temperature change of the plurality of transistor units 11. Based on this, the bias current generated by the second bias unit 222 according to the current outputted from the second bias transistor Q3 can also follow the temperature change of the plurality of transistor units 11.

[0080] As an embodiment, the first bias transistor Q2 is a heterojunction bipolar transistor, the control terminal of the first bias transistor Q2 is the base, the first terminal of the first bias transistor Q2 is the emitter, the second terminal of the first bias transistor Q2 is the collector, and the base of the first bias transistor Q2 is connected to the collector. The second bias transistor Q3 is a heterojunction bipolar transistor, the control terminal of the second bias transistor Q3 is the base, the first terminal of the second bias transistor Q3 is the emitter, the second terminal of the second bias transistor Q3 is the collector, and the base of the second bias transistor Q3 is connected to the collector. In some embodiments, the first terminal of the first bias transistor Q2 is grounded through the corresponding metal component 12.

[0081] Therefore, in the bias circuit, the control terminal (base) and the second terminal (collector) of the first bias transistor Q2 are short-circuited, the control terminal (base) and the second terminal (collector) of the second bias transistor Q3 are short-circuited, and the first bias transistor Q2 and the second bias transistor Q3 are equivalent to a diode structure respectively. Since a certain voltage drop will be generated after the diode structure is turned on, illustratively, the voltage drop is about 1.2V, and the first bias transistor Q2 and the second bias transistor Q3 connected in series can provide a voltage of about 2.4V for the second bias unit 222, so that the second bias unit 222 can be smoothly turned on.

[0082] It can be understood that if the bias voltage required by the second bias unit 222 is higher, multiple second bias transistors Q3 connected in series can be provided so that the first bias transistor Q2 and multiple second bias transistors Q3 connected in series can provide the second bias unit 222 with a bias voltage to turn it on.

[0083] In other embodiments, the first bias transistor Q2 is a diode, the first end of the first bias transistor Q2 is a negative electrode, and the second end of the first bias transistor Q2 is a positive electrode. The second bias transistor Q3 is a diode, the first end of the second bias transistor Q3 is a negative electrode, and the second end of the second bias transistor Q3 is a positive electrode. The principle of using a diode as the first bias transistor Q2 and the second bias transistor Q3 to provide a bias voltage for the second bias unit 222 is similar to the previous embodiment, and will not be repeated here.

[0084] In this embodiment, each first bias transistor is connected to the second bias unit through a second bias transistor, and each first bias transistor is in a parallel relationship. The second bias unit generates a bias current according to the sum of the control currents of each first bias transistor, and the bias current generated by the second bias unit follows the comprehensive temperature change of each transistor unit.

[0085] In some embodiments, please refer to Figure 7 As shown, the second bias unit 222 includes a third bias transistor Q4, a control end of the third bias transistor Q4 is connected to the second end of the second bias transistor Q3, a first end of the third bias transistor Q4 is connected to the control end of the amplifying transistor Q1, and a second end of the third bias transistor Q4 is used to input a power supply voltage.

[0086] The control end of the third bias transistor Q4 receives the sum of the control currents of the first bias transistors Q2, and the first end of the third bias transistor Q4 is used to output a bias current generated according to the sum of the control currents of the first bias transistors Q2. The first end of the third bias transistor Q4 is connected to the control end of the amplifying transistor Q1 in each transistor unit 11, and the bias current is output to at least two transistor units 11 through the same third bias transistor Q4.

[0087] In this embodiment, the control end of the third bias transistor receives a control current that follows the comprehensive temperature change of each transistor unit, and the first end of the third bias transistor is used to output the bias current of the amplifier transistor, so that the bias current of the amplifier transistor follows the comprehensive temperature change of each transistor unit.

[0088] As an implementation manner, the third bias transistor Q4 is a heterojunction bipolar transistor, the control end of the third bias transistor Q4 is the base, the first end of the third bias transistor Q4 is the emitter, and the second end of the third bias transistor Q4 is the collector.

[0089] In some embodiments, see Figure 8 As shown, the second bias unit 222 includes a plurality of third bias transistors Q4, and the plurality of third bias transistors Q4 are arranged in one-to-one correspondence with the plurality of transistor units 11. The control end of the third bias transistor Q4 is connected to the second end of the second bias transistor Q3, the first end of the third bias transistor Q4 is connected to the control end of each amplifying transistor Q1 in the corresponding transistor unit 11, and the second end of the third bias transistor Q4 is used to input the power supply voltage.

[0090] The control end of each third bias transistor Q4 receives the sum of the control currents of each first bias transistor Q2, and the first end of each third bias transistor Q4 is used to output the bias current generated according to the sum of the control currents of each first bias transistor Q2. The first end of the third bias transistor Q4 is connected to the control end of the amplifying transistor Q1 in the corresponding transistor unit 11, and the bias current is output to at least two transistor units 11 through different third bias transistors Q4.

[0091] In this embodiment, the control end of each third bias transistor receives a control current that follows the comprehensive temperature change of each transistor unit, and the first end of each third bias transistor is used to output the bias current of the amplifier transistor, so that the bias current of the amplifier transistor follows the comprehensive temperature change of each transistor unit.

[0092] In some embodiments, please refer to Figure 7 and Figure 8 As shown, the number of transistor units 11 is two, namely the first transistor unit 11a and the second transistor unit 11b; the first bias unit 221 at least includes the first bias transistor Q2 in the first transistor unit 11a and the first bias transistor Q2 in the second transistor unit 11b; the second bias unit 222 is respectively connected to each amplifying transistor Q1 in the first transistor unit 11a and each amplifying transistor Q1 in the second transistor unit 11b.

[0093] It is understandable that the setting of each metal component will generate resistance and parasitic inductance, resulting in increased losses in the power amplifier circuit, and as the size of the metal component becomes smaller, its heat dissipation decreases. In this embodiment, the number of transistor units and metal components is set to two instead of more, respectively. This can minimize the impact on the insertion loss and heat dissipation effect of the power amplifier chip while achieving improved uniformity of stress distribution and thermal uniformity of the transistor.

[0094] Exemplarily, when the number of amplifying transistors in the amplifying circuit is 20 to 30, the amplifying transistors are divided into two groups to form two transistor units with two first bias transistors. This not only enables the packaging stress distribution of the metal component to be uniform, but also utilizes the thermal following effect of the first bias transistor to improve the linearity of the power amplifying chip and reduce the error vector amplitude of the power amplifying chip. In addition, compared with a low-power amplifier with less than 10 amplifying transistors, it can also reduce the insertion loss of the power amplifying chip and improve the heat dissipation effect.

[0095] Of course, it is understandable that when the number of amplifying transistors set in the amplifying circuit is greater, resulting in a larger total area of ​​the metal component, the amplifying transistors can also be divided into more groups, and more first bias transistors can be set accordingly to form more transistor units together with the amplifying transistors in each group.

[0096] As an implementation, see Fig. 9 As shown, the power amplifier chip 100 integrates a plurality of bias circuits 22, and the plurality of bias circuits 22 are arranged in a one-to-one correspondence with the transistor units 11. Each bias circuit 22 includes a first bias unit 221 and a second bias unit 222. The first bias unit 221 includes at least a first bias transistor Q2, which may be located in a corresponding transistor unit 11 or in other transistor units 11. The first bias transistor Q2 is configured to output a control current to the second bias unit 222 that follows the temperature of the transistor unit 11 in which it is located.

[0097] The second bias unit 222 is connected to the control terminal of each amplifying transistor Q1 in the corresponding transistor unit 11 , and is used for generating a bias current according to the control current, and outputting the bias current to the amplifying transistor Q1 .

[0098] As the temperature of the amplifier transistor Q1 increases or decreases, the temperature of the first bias transistor Q2 increases or decreases accordingly. The temperature change of the first bias transistor Q2 causes its resistance value to change, so that the control current output by the first bias transistor Q2 changes. The second bias unit 222 generates a bias current of the amplifier transistor Q1 in its corresponding transistor unit 11 according to the control current of the connected first bias transistor Q2, so that the bias current of the amplifier transistor Q1 can follow the temperature change of the transistor unit 11 in which it is located or other transistor units 11.

[0099] In this embodiment, a corresponding bias circuit is provided for each transistor unit so that the bias current of the transistor unit amplifying transistor can follow the temperature change of the transistor unit or other transistor units, thereby reducing the influence of temperature change on the gain and output power of each transistor unit.

[0100] In some embodiments, see Fig.10 As shown, the number of transistor units 11 is at least two, and the at least two transistor units 11 include a first transistor unit 11a and a second transistor unit 11b; the bias circuit 22 is provided with at least two, including a first bias circuit 22a and a second bias circuit 22b, the first bias circuit 22a corresponds to the first transistor unit 11a and is used to output a bias current to the amplifier transistor Q1 in the first transistor unit 11a, and the second bias circuit 22b corresponds to the second transistor unit 11b and is used to output a bias current to the amplifier transistor Q1 in the second transistor unit 11b.

[0101] The first bias transistor Q2 of the first bias circuit 22a is located in the first transistor unit 11a; the first bias transistor Q2 of the second bias circuit 22b is located in the second transistor unit 11b.

[0102] In this embodiment, the number of transistor units and metal components is set to two respectively, so as to reduce the insertion loss of the power amplifier chip and improve the heat dissipation effect while improving the uniformity of stress distribution and the thermal uniformity of the transistor; and the bias current of the amplifier transistor follows the temperature of the transistor unit in which it is located, which is beneficial to improve the matching degree between the temperature of the amplifier transistor and the bias current.

[0103] In some embodiments, see Fig.11As shown, the number of transistor units 11 is at least two, and the at least two transistor units 11 include a first transistor unit 11a and a second transistor unit 11b; the bias circuit 22 is provided with at least two, including a first bias circuit 22a and a second bias circuit 22b, the first bias circuit 22a corresponds to the first transistor unit 11a and is used to output a bias current to the amplifier transistor Q1 in the first transistor unit 11a, and the second bias circuit 22b corresponds to the second transistor unit 11b and is used to output a bias current to the amplifier transistor Q1 in the second transistor unit 11b.

[0104] The first bias transistor Q2 of the first bias circuit 22a is located in the second transistor unit 11b; the first bias transistor Q2 of the second bias circuit 22b is located in the first transistor unit 11a.

[0105] In this embodiment, the number of transistor units and metal components is set to two respectively, so as to reduce the insertion loss of the power amplifier chip and improve the heat dissipation effect while improving the uniformity of stress distribution and the thermal uniformity of the transistor; and the bias current of the amplifier transistor follows the temperature of another transistor unit, which is beneficial to reducing the influence of temperature changes on the gain and output power of each transistor unit.

[0106] In some embodiments, please refer to Fig. 9 As shown, each bias circuit 22 further includes a second bias transistor Q3 arranged corresponding to the first bias transistor Q2 , a first end of the second bias transistor Q3 is connected to a second end of the first bias transistor Q2 , and a second end of the second bias transistor Q3 is connected to a second bias unit 222 .

[0107] The second end of the first bias transistor Q2 outputs a control current that follows the temperature of the transistor unit 11 where the first bias transistor Q2 is located. The second end of the second bias transistor Q3 is used to output the control current of the first bias transistor Q2. The second bias unit 222 generates a bias current according to the control current of the first bias transistor Q2.

[0108] In this embodiment, the first bias transistor Q2 is connected to the second bias unit through the second bias transistor Q3. The second bias unit generates a bias current according to the control current of the first bias transistor. The bias current generated by the second bias unit follows the temperature of the corresponding transistor unit, which is beneficial to reducing the impact of temperature changes on the gain and output power of each transistor unit.

[0109] In some embodiments, please refer to Fig. 9As shown, the second bias unit 222 includes a third bias transistor Q4, the control end of the third bias transistor Q4 is connected to the second end of the second bias transistor Q3, the first end of the third bias transistor Q4 is connected to the control end of the amplifying transistor Q1 in the corresponding transistor unit 11, and the second end of the third bias transistor Q4 is used to input the power supply voltage.

[0110] The control end of the third bias transistor Q4 receives the control current of the first bias transistor Q2 through the second bias transistor Q3, and the first end of the third bias transistor Q4 is used to output the bias current generated according to the control current of the first bias transistor Q2. The first end of the third bias transistor Q4 is connected to the control end of the amplifying transistor Q1 in the corresponding transistor unit 11, and the bias current is output to the corresponding transistor unit 11 through the third bias transistor Q4.

[0111] In this embodiment, the control end of the third bias transistor receives a control current that follows the temperature of any transistor unit, and the first end of the third bias transistor is used to output the bias current of the amplifier transistor, so that the bias current of the amplifier transistor follows the temperature of any transistor unit.

[0112] As an implementation, see Figure 1 As shown, the projection of the metal component 12 on the power amplifier chip 100 along the first direction has an overlapping area with the setting area of ​​the transistor unit 11, and the first direction is the thickness direction of the power amplifier chip 100. In this embodiment, the projection area of ​​the metal component and the setting area of ​​the transistor unit at least partially overlap, so that each transistor in the transistor unit is grounded through the metal component, and the heat of the transistor is dissipated through the metal component.

[0113] In some embodiments, the setting area of ​​the transistor unit 11 is located within the projection of the metal component 12 on the power amplifier chip 100 along the first direction. In this embodiment, the setting area of ​​the transistor unit completely falls within the projection area of ​​the metal component, and the stress applied to the transistor unit by the metal component is more uniform. In addition, the size of the metal component 12 is larger, the loss of the RF signal is lower, and the heat dissipation performance is better.

[0114] An embodiment of the present application provides a radio frequency front-end module 200, see Fig.12 As shown, the RF front-end module 200 includes a circuit substrate 201 and the above-mentioned power amplifier chip 100 arranged on the circuit substrate 201; the power amplifier chip 100 is provided with a metal component 12 on one side opposite to the circuit substrate 201, and the metal component 12 is connected to the circuit substrate 201 so as to flip-chip the power amplifier chip 100 on the circuit substrate 201.

[0115] In this embodiment, the power amplifier chip is flip-chip mounted on the circuit substrate, and the metal component plays a supporting and electrical connection role. By arranging at least two transistor units, the size of the metal component corresponding to the transistor unit can be reduced, and the stress distribution of the metal component is uniform, thereby improving the circuit performance and reliability in the power amplifier chip; by arranging at least one first bias transistor in the transistor unit, using the first bias transistor to track the temperature of the corresponding transistor unit and providing a bias signal for the amplifier transistor according to the temperature, the thermal uniformity of the transistor can be improved, which is beneficial to improving the linearity of the power amplifier chip and reducing the error vector amplitude of the power amplifier chip.

[0116] The above is only an implementation method of the present application. It should be pointed out that a person skilled in the art can make improvements without departing from the inventive concept of the present application, but these improvements are within the scope of protection of the present application.

Claims

1. A power amplifier chip, characterized in that: include: At least two transistor units, each of the transistor units includes a plurality of transistors arranged in sequence, at least two of the plurality of transistors are configured as amplifier transistors and at least one is configured as a first bias transistor, wherein the amplifier transistor is used to amplify an input radio frequency signal, and the first bias transistor is used to provide a bias signal for the amplifier transistor; A metal component is arranged in a one-to-one correspondence with at least two of the transistor units, and the metal component is electrically connected to at least the first end of each of the amplifying transistors in the transistor unit.

2. The power amplifier chip according to claim 1, characterized in that: The power amplifier chip integrates a power amplifier circuit and a bias circuit, the power amplifier circuit includes the amplifier transistor, the bias circuit includes the first bias transistor, and the bias circuit is connected to the control terminal of the amplifier transistor to output the bias signal to the amplifier transistor; Wherein, the first end of the amplifying transistor is grounded through the corresponding metal component, and the second end of the amplifying transistor is used to output the amplified radio frequency signal.

3. The power amplifier chip according to claim 2, characterized in that: The first bias transistor is located between two adjacent amplifying transistors; or, each amplifying transistor in the transistor unit is located on the same side of the first bias transistor; or, the number of the first bias transistors in the transistor unit is two, and each amplifying transistor is located between two first bias transistors.

4. The power amplifier chip according to claim 2, characterized in that: The bias signal includes a bias current, the bias circuit includes a first bias unit and a second bias unit, the first bias unit includes at least the first bias transistor, and the first bias transistor is configured to output a control current following the temperature of the transistor unit to the second bias unit; The second bias unit is connected to the control terminal of the amplifying transistor, and is used for generating the bias current according to the control current, and outputting the bias current to the amplifying transistor.

5. The power amplifier chip according to claim 4, characterized in that: The first bias unit further includes a second bias transistor, a first terminal of the second bias transistor is connected to the second terminal of each of the first bias transistors, and a second terminal of the second bias transistor is connected to the second bias unit.

6. The power amplifier chip according to claim 5, characterized in that: The second bias unit includes a third bias transistor, a control terminal of the third bias transistor is connected to the second terminal of the second bias transistor, a first terminal of the third bias transistor is connected to the control terminal of the amplifying transistor, and a second terminal of the third bias transistor is used to input a power supply voltage.

7. The power amplifier chip according to claim 5, characterized in that: The second bias unit includes a plurality of third bias transistors arranged in one-to-one correspondence with the transistor units, the control end of the third bias transistor is connected to the second end of the second bias transistor, the first end of the third bias transistor is connected to the control end of each amplifying transistor in the corresponding transistor unit, and the second end of the third bias transistor is used to input a power supply voltage.

8. The power amplifier chip according to claim 4, characterized in that: The number of the transistor units is two, namely a first transistor unit and a second transistor unit; the first bias unit at least includes the first bias transistor in the first transistor unit and the first bias transistor in the second transistor unit; The second bias unit is connected to each of the amplifying transistors in the first transistor unit and each of the amplifying transistors in the second transistor unit, respectively.

9. The power amplifier chip according to claim 2, characterized in that: The power amplifier chip is integrated with a plurality of bias circuits arranged in a one-to-one correspondence with the transistor units, each of the bias circuits includes a first bias unit and a second bias unit, the first bias unit includes at least the first bias transistor, the first bias transistor is located in the corresponding transistor unit or in other transistor units, and the first bias transistor is configured to output a control current that follows the temperature of the transistor unit in which it is located to the second bias unit; The second bias unit is connected to the control terminal of each of the amplifying transistors in the corresponding transistor unit, and is used to generate a bias current according to the control current, and output the bias current to the amplifying transistor.

10. The power amplifier chip according to claim 9, characterized in that: The number of the transistor units is at least two, including a first transistor unit and a second transistor unit; the bias circuit is provided with at least two, including a first bias circuit and a second bias circuit, the first bias circuit corresponds to the first transistor unit and is used to output the bias current to the amplifying transistor in the first transistor unit, and the second bias circuit corresponds to the second transistor unit and is used to output the bias current to the amplifying transistor in the second transistor unit; The first bias transistor of the first bias circuit is located in the first transistor unit; and the first bias transistor of the second bias circuit is located in the second transistor unit.

11. The power amplifier chip according to claim 9, characterized in that: The number of the transistor units is at least two, including a first transistor unit and a second transistor unit; the bias circuit is provided with at least two, including a first bias circuit and a second bias circuit, the first bias circuit corresponds to the first transistor unit and is used to output the bias current to the amplifying transistor in the first transistor unit, and the second bias circuit corresponds to the second transistor unit and is used to output the bias current to the amplifying transistor in the second transistor unit; The first bias transistor of the first bias circuit is located in the second transistor unit; and the first bias transistor of the second bias circuit is located in the first transistor unit.

12. The power amplifier chip according to claim 9, characterized in that: Each of the bias circuits further includes a second bias transistor arranged corresponding to the first bias transistor, a first end of the second bias transistor is connected to a second end of the first bias transistor, and a second end of the second bias transistor is connected to the second bias unit.

13. The power amplifier chip according to claim 1, characterized in that: The amplifying transistor is a heterojunction bipolar transistor, the control end of the amplifying transistor is a base, the first end of the amplifying transistor is an emitter, and the second end of the amplifying transistor is a collector.

14. The power amplifier chip according to claim 4 or 9, characterized in that: The first bias transistor is a heterojunction bipolar transistor, the control terminal of the first bias transistor is the base, the first terminal of the first bias transistor is the emitter, the second terminal of the first bias transistor is the collector, and the base of the first bias transistor is connected to the collector; Alternatively, the first bias transistor is a diode, the first end of the first bias transistor is a cathode, and the second end of the first bias transistor is an anode.

15. The power amplifier chip according to claim 14, characterized in that: The first terminal of the first bias transistor is grounded through the corresponding metal component.

16. The power amplifier chip according to claim 7 or 12, characterized in that: The second bias transistor is a heterojunction bipolar transistor, the control terminal of the second bias transistor is a base, the first terminal of the second bias transistor is an emitter, the second terminal of the second bias transistor is a collector, and the base of the second bias transistor is connected to the collector; Alternatively, the second bias transistor is a diode, the first end of the second bias transistor is a cathode, and the second end of the second bias transistor is an anode.

17. The power amplifier chip according to claim 1, characterized in that: A projection of the metal component on the power amplifier chip along a first direction has an overlapping area with a setting area of ​​the transistor unit, and the first direction is a thickness direction of the power amplifier chip.

18. The power amplifier chip according to claim 17, characterized in that: The arrangement area of ​​the transistor unit is located within a projection of the metal component on the power amplifier chip along the first direction.

19. A radio frequency front-end module, characterized in that: It comprises a circuit substrate and a power amplifier chip as described in any one of claims 1 to 18 arranged on the circuit substrate; the power amplifier chip has a side with a metal component opposite to the circuit substrate, and the metal component is connected to the circuit substrate so that the power amplifier chip is flip-chip arranged on the circuit substrate.

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