Dual-power-supply three-state output circuit with power-on and power-off process output state control function and working method of dual-power-supply three-state output circuit

Abstract

The invention provides a dual-power three-state output circuit with power-on and power-off process output state control and a working method of the dual-power three-state output circuit. The dual-power three-state output circuit comprises a logic control circuit, a weak pull-up and pull-down level conversion circuit and a driving circuit. The logic control circuit is powered by kernel logic voltage, the weak pull-up and pull-down level conversion circuit is powered by input and output unit voltage and the kernel logic voltage, and the driving power is powered by the input and output unit voltage. Aiming at the condition that the input / output unit is powered by voltage and the kernel logic voltage is not powered, a weak pull-up and pull-down circuit powered by the input / output voltage is added in the three-state output unit, and when the kernel logic voltage is not powered, the input node voltage of a level conversion circuit of the three-state output unit is controlled; the pull-up driving tube and the pull-down driving tube in the driving circuit are both in a closed state, it is ensured that the three-state output unit works in a three-state mode at the moment, the abnormal working condition of large current of an application system is avoided, and the problem of large current caused by signal competition of a bus is avoided.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuits and relates to a dual-power three-state output circuit with output state control during power-on and power-off processes and a working method thereof. Background Art

[0002] Monolithic integrated circuits mainly include circuit modules such as logic units, on-chip memory, phase-locked loop circuits, and input-output units. The main function of the input-output unit is to serve as an interface for the information processed by the integrated circuit core logic to communicate with the outside of the chip, to realize the input and output of signals. These units adjust the driving and matching requirements of the input and output signals according to different electrical characteristics to ensure the correct processing and transmission of signals. Usually, for the design of very large-scale integrated circuits, the input-output unit and the core logic circuit use two different power supply voltages respectively. The input-output unit voltage uses a higher operating voltage to ensure the driving capability and signal transmission reliability of the input-output unit, such as working at 3.3V, 2.5V, etc.; the core logic voltage uses a lower operating voltage to reduce the static power consumption and dynamic power consumption of the integrated circuit, and suppress the heat dissipation problem caused by the continuous reduction of the feature size of the integrated circuit device and the continuous improvement of the device working performance, such as working at 1.2V, 0.9V, etc.

[0003] For a monolithic integrated circuit powered by dual power supplies, the power-on and power-off sequences of the input-output unit voltage VDDIO and the core logic voltage VDDC are different for different application scenarios and user system design schemes, and the power-on and power-off time intervals of the input-output unit voltage and the core logic voltage are also different. As a type of input-output unit, the three-state output unit is often used for bus-based multi-circuit interface interconnection. During normal operation, only one circuit's three-state output unit interface is configured as a normal output working mode, and the three-state output unit interfaces of other circuits are configured as three-state working modes to avoid state competition between different output unit interfaces on the bus causing large current. However, during the power-on and power-off process of the system, for different application environments, there may be a situation where the input-output unit voltage is powered and the core logic voltage is not powered. At this time, the control signal output by the core logic cannot effectively control the output state of the three-state output unit, which may cause a competition state on the system bus and generate a large current, thereby causing abnormal system working state. Some traditional three-state output units lack the output state control function during the power-on and power-off process, and some use complex circuit structures to implement the state control function, thereby introducing a large area and design complexity. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention proposes a dual-power three-state output circuit with output state control during power-on and power-off processes, with the purpose of simplifying the control logic design structure of the three-state output unit and solving the problem of high system current caused by the uncontrollable three-state output state when the input and output unit voltage is powered but the core logic voltage is not powered.

[0005] The present invention is achieved through the following technical solutions: A dual power supply three-state output circuit with power-on and power-off process output state control, comprising: Logic control circuit 821, weak pull-up and pull-down level conversion circuit 822, driving circuit 823; The input end of the logic control circuit 821 is connected to the enable control signal OE and the power input signal VIN, and the output end of the logic control circuit 821 is connected to the input end of the weak pull-up and pull-down level conversion circuit 822 through the first signal VA1 and the second signal VB1 respectively, and the output end of the weak pull-up and pull-down level conversion circuit 822 is connected to the input end of the driving circuit 823 through the third signal VA2 and the fourth signal VB2 respectively, and the output end of the driving circuit 823 is connected to the power output signal VOUT.

[0006] The logic control circuit 821 is powered by the core logic voltage VDDC, the weak pull-up and pull-down level conversion circuit 822 is powered by the input-output unit voltage VDDIO and the core logic voltage VDDC, and the driving circuit 823 is powered by the input-output unit voltage VDDIO.

[0007] Preferably, when the input-output unit voltage VDDIO and the core logic voltage VDDC are both powered normally, if the enable control signal OE is at a low level, the dual-power three-state output circuit operates in a normal working mode, the power output signal VOUT changes with the power input signal VIN, and the power output signal VOUT maintains the same state as the power input signal VIN.

[0008] Preferably, when the input-output unit voltage VDDIO and the core logic voltage VDDC are both powered normally, if the enable control signal OE is at a high level, the dual power tri-state output circuit operates in a normal tri-state mode, and the power output signal VOUT is in a high impedance state.

[0009] Preferably, when the input-output unit voltage VDDIO is normally powered and the core logic voltage VDDC is not powered, the dual-power tri-state output circuit operates in an abnormal tri-state mode, and the power output signal VOUT is in a high-impedance state.

[0010] Preferably, when the input-output unit voltage VDDIO is not powered, regardless of whether the core logic voltage VDDC is powered, the dual-power tri-state output circuit operates in a non-driving mode, and the power output signal VOUT has no driving capability.

[0011] Preferably, the logic control circuit 821 includes an inverter, a two-input NAND gate and a two-input NOR gate.

[0012] Preferably, the weak pull-up and pull-down level conversion circuit 822 includes 8 pmos transistors and 8 nmos transistors.

[0013] Preferably, the driving circuit 823 includes 3 pmos transistors and 3 nmos transistors. A working method of a dual power supply three-state output circuit with output state control during power-on and power-off processes, The logic control circuit 821 is powered by the core logic voltage VDDC. When the enable control signal OE is at a low level, the first signal VA1 and the second signal VB1 at the output end of the logic control 821 are in the same state as the power input signal VIN; when the enable control signal OE is at a high level, the first signal VA1 is at a high level and the second signal VB1 is at a low level. The weak pull-up and pull-down level conversion circuit 822 is powered by the input-output unit voltage VDDIO and the core logic voltage VDDC at the same time. When the input-output unit voltage VDDIO and the core logic voltage VDDC are both powered normally, the third signal VA2 and the fourth signal VB2 at the output end of the weak pull-up and pull-down level conversion circuit 822 are respectively in the same state as the first signal VA1 and the second signal VB1 at the input end of the weak pull-up and pull-down level conversion circuit 822; when the input-output unit voltage VDDIO is powered normally and the core logic voltage VDDC is not powered, the third signal VA2 at the output end of the weak pull-up and pull-down level conversion circuit 822 is at a low level and the fourth signal VB2 is at a high level; The driving circuit 823 is powered by the input-output unit voltage VDDC. When the third signal VA2 and the fourth signal VB2 at the input end of the driving circuit 823 are both high, the power output signal VOUT is high; when the third signal VA2 and the fourth signal VB2 at the input end of the driving circuit 823 are both low, the power output signal VOUT is low; when the third signal VA2 at the input end is low and the fourth signal VB2 at the output end is high, the power output signal VOUT is in a high impedance state. An integrated circuit with a dual-power tri-state output circuit with power-on and power-off process output state control, comprising three input control signals, three power input signals and three dual-power tri-state output circuits with power-on and power-off process output state control; Each input control signal and power input signal is respectively connected to the input end of a dual power three-state output circuit with power-on and power-off process output state control, and the output ends of the three dual power three-state output circuits with power-on and power-off process output state control are all connected to the bus.

[0014] Compared with the prior art, the present invention has the following beneficial technical effects: Aiming at the demand of state control of three-state output unit in the process of powering on and off of dual power supplies, the present invention proposes a dual power supply three-state output circuit with output state control in the process of powering on and off and a working method thereof, comprising a logic control circuit, a weak pull-up and pull-down level conversion circuit, and a driving circuit; the logic control circuit 821 is powered by a core logic voltage VDDC, the weak pull-up and pull-down level conversion circuit is powered by an input-output unit voltage VDDIO and a core logic voltage VDDC, and the driving circuit is powered by the input-output unit voltage VDDIO. The logic control circuit 821 is powered by the core logic voltage VDDC, while the weak pull-up and pull-down level conversion circuit 822 and the driving circuit 823 are powered by the input-output unit voltage VDDIO. This dual power supply design enables the circuit to adapt to different voltage environments more flexibly, thereby improving the compatibility and reliability of the circuit. In the case where the input-output unit voltage is powered but the core logic voltage is not powered, a weak pull-up and pull-down circuit powered by the input-output voltage VDDIO is added to the three-state output unit. When the core logic voltage VDDC is not powered, the input node voltage of the three-state output unit level conversion circuit is controlled to make the pull-up drive tube and the pull-down drive tube in the drive circuit both in the off state, ensuring that the three-state output unit works in the three-state mode at this time, avoiding abnormal operation of large current in the application system. By adding a weak pull-up and pull-down function at the input end of the level conversion circuit, it is ensured that when the input-output unit voltage VDDIO is normally powered and the core logic voltage VDDC is not powered, the output end of the three-state output unit is in a high-impedance state, avoiding the problem of large current caused by signal competition on the bus, and the circuit structure is simple and easy to implement.

[0015] Furthermore, the design of the weak pull-up and pull-down level conversion circuit 822 enables the circuit to pull the output end to a certain level through the weak pull-up and pull-down functions when the circuit does not need to output a specific level, thereby reducing power consumption, helping to reduce the floating state of the output end, and improving the circuit's anti-interference ability.

[0016] Furthermore, by integrating the logic control circuit, the level conversion circuit and the driving circuit into one circuit, the overall circuit design can be simplified, the number of components can be reduced, the manufacturing cost can be reduced, and the reliability and stability of the circuit can be improved.

[0017] Furthermore, the driving circuit 823 is powered by the input-output unit voltage VDDIO, which generally means that it can provide stronger driving capability, which is particularly important for application scenarios that require driving a large load or transmitting signals over long distances.

[0018] Furthermore, the stability of the circuit during power on and off can be ensured by the precise processing of the enable control signal OE and the power input signal VIN by the logic control circuit 821. This helps prevent circuit malfunctions caused by power fluctuations or signal interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is an integrated circuit with a dual-power three-state output circuit that controls the output state during power-on and power-off processes; Figure 2 It is a dual power supply three-state output circuit diagram with output state control during power-on and power-off processes; Figure 3 It is a waveform diagram of a dual power supply three-state output circuit with output state control during power-on and power-off processes; Figure 4 It is a structure diagram of a dual power supply three-state output circuit with output state control during power-on and power-off processes; DETAILED DESCRIPTION The present invention is further described in detail below in conjunction with specific embodiments, which are intended to explain the present invention rather than to limit it.

[0020] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0021] like Figure 1 As shown, an integrated circuit with a dual power supply three-state output circuit with power-on and power-off process output state control includes a first dual power supply three-state output circuit 811 with power-on and power-off process output state control, a second dual power supply three-state output circuit 812 with power-on and power-off process output state control, and a third dual power supply three-state output circuit 813 with power-on and power-off process output state control.

[0022] The first enable control signal OE1 and the second power input signal VIN1 are connected to the input end of the first dual power tri-state output circuit 811 with output state control of the power-on and power-off processes, the second enable control signal OE2 and the power input signal VIN2 are connected to the input end of the dual power tri-state output circuit 812 with output state control of the power-on and power-off processes, the third enable control signal OE3 and the third power input signal VIN3 are connected to the input end of the third dual power tri-state output circuit 813 with output state control of the power-on and power-off processes, the first dual power tri-state output circuit 811 with output state control of the power-on and power-off processes, the second dual power tri-state output circuit 812 with output state control of the power-on and power-off processes, and the third dual power tri-state output circuit 813 with output state control of the power-on and power-off processes are all connected to the bus.

[0023] like Figure 2 As shown, a dual power tri-state output circuit with power-on and power-off process output state control of the present invention includes a logic control 821, a weak pull-up and pull-down level conversion circuit 822 and a drive circuit 823.

[0024] The logic control 821 is powered by the core logic voltage VDDC, the weak pull-up and pull-down level conversion circuit 822 is powered by the input-output unit voltage VDDIO and the core logic voltage VDDC, and the drive circuit 823 is powered by the input-output unit voltage VDDIO. The enable control signal OE and the power input signal VIN are connected to the input end of the logic control 821, the output end of the logic control circuit 821 is connected to the input end of the weak pull-up and pull-down level conversion circuit 822 through the first signal VA1 and the second signal VB1, the output end of the weak pull-up and pull-down level conversion circuit 822 is connected to the input end of the drive circuit 823 through the third signal VA2 and the fourth signal VB2, and the drive circuit 823 outputs the power supply signal VOUT.

[0025] The logic control 821 operates on the power input signal VIN and the enable control signal OE. When OE is at a low level, the first signal VA1 and the second signal VB1 at the output end are both the logical inverse state of the power input signal VIN; when OE is at a high level, the power input signal VIN is shielded, the first signal VA1 at the output end constantly outputs a high level, and the second signal VB1 at the output end constantly outputs a low level; the weak pull-up and pull-down level conversion circuit 822 realizes the level conversion of the power input signal VIN and the enable control signal OE, and ensures that when the input-output unit voltage VDDIO is powered and the core operating voltage VDDC is not powered, the third signal VA2 at the output end is at a low level and the fourth signal VB2 at the output end is at a high level, so that the output signal of the output unit is in a high impedance state; the driving circuit 823 increases the driving capability of the third signal VA2 and the fourth signal VB2, and improves the adaptability and matching of the power output signal VOUT to the external load of the circuit.

[0026] like Figure 4 As shown, the logic control 821 includes an inverter, a two-input NAND gate and a two-input NOR gate; the enable control signal OE is connected to the input terminal b of the inverter inv1 and the two-input NOR gate nor1, the power input signal VIN is connected to the input terminal a of the two-input NOR gate nor1 and the input terminal b of the two-input NAND gate nand1, the output terminal of the inverter inv1 is connected to the input terminal a of the two-input NAND gate nand1, the output terminal y of the two-input NAND gate nand1 is connected to the first signal VA1, and the output terminal y of the two-input NOR gate nor1 is connected to the second signal VB1. The logic control 821 implements the operation of the enable control signal OE and the power input signal VIN. When OE is low level, the first signal VA1 and the second signal VB1 at the output terminal are both the logical inverse state of the power input signal VIN; when OE is high level, the first signal VA1 at the output terminal is high level, and the second signal VB1 at the output terminal is low level.

[0027] like Figure 4As shown, the weak pull-up and pull-down level conversion circuit 822 includes 8 pmos transistors and 8 nmos transistors; the input first signal VA1 is connected to the d-end of transistor mp1, the g-end of transistor mp2, the g-end of transistor mn2, the d-end of transistor mp6, the d-end of transistor mn6, the g-end of transistor mn7, and the g-end of transistor mn4, the s-end of transistor mp1 is connected to the input-output unit voltage VDDIO, the g-end of transistor mp1 is connected to the g-end of transistor mn1 and the d-end of transistor mn1, the s-end of transistor mn1 is connected to the ground line, and the s-end of transistor mp2 is connected to the core logic The voltage VDDC is connected, the d-end of the transistor mp2 is connected to the d-end of the transistor mn2, the g-end of the transistor mn3, and the second signal VB1 at the input end, the s-end of the transistor mn2 is connected to the ground line, the s-end of the transistor mp3 is connected to the input-output unit voltage VDDIO, the g-end of the transistor mp3 is connected to the d-end of the transistor mp4, the d-end of the transistor mn4, and the third signal VA2 at the output end, the d-end of the transistor mp3 is connected to the d-end of the transistor mn3, the g-end of the transistor mp4, the s-end of the transistor mn3 is connected to the ground line, and the s-end of the transistor mp4 is connected to the input-output unit voltage VDDI O is connected, the s terminal of transistor mn4 is connected to the ground line, the second signal VB1 at the input end is connected to the d terminal of transistor mp5, the g terminal of transistor mp6, the g terminal of transistor mn6, the d terminal of transistor mp2, the d terminal of transistor mn2, the g terminal of transistor mn3, and the g terminal of transistor mn8, the s terminal of transistor mn5 is connected to the ground line, the g terminal of transistor mn5 is connected to the g terminal of transistor mp5 and the d terminal of transistor mp5, the s terminal of transistor mp5 is connected to the input and output unit voltage VDDIO, the s terminal of transistor mp6 is connected to the core logic voltage VDDC, and the d terminal of transistor mp6 is connected to the The end is connected to the d-end of transistor mn6, the g-end of transistor mn7, and the input first signal VA1, the s-end of transistor mn6 is connected to the ground line, the s-end of transistor mp7 is connected to the input-output unit voltage VDDIO, the g-end of transistor mp7 is connected to the d-end of transistor mp8, the d-end of transistor mn8, and the fourth signal VB2 at the output end, the d-end of transistor mp7 is connected to the d-end of transistor mn7, the g-end of transistor mp8, the s-end of transistor mn7 is connected to the ground line, the s-end of transistor mp8 is connected to the input-output unit voltage VDDIO, and the s-end of transistor mn8 is connected to the ground line;Transistors mp1 and mn1 implement a pull-up function, and pull up the relevant nodes when the core logic voltage is not powered. Transistors mp5 and mn5 implement a pull-down function, and pull down the relevant nodes when the core logic voltage is not powered. Transistors mp2, mp3, mp4, mn2, mn3, and mn4 implement a level conversion. Transistors mp6, mp7, mp8, mn6, mn7, and mn8 implement a level conversion. The weak pull-up and pull-down level conversion circuit 822 implements signal level conversion in the normal working mode, and when the input-output unit voltage VDDIO is powered and the core working voltage VDDC is not powered, ensures that the third signal VA2 at the output end is low level and the fourth signal VB2 at the output end is high level, so that the output signal of the tri-state output unit is in a high impedance state. ;

[0028] like Figure 4 As shown, the driving circuit 823 includes 3 pmos transistors and 3 nmos transistors, the input signal VA2 is connected to the g-end of the transistor mp9 and the g-end of the transistor mn9, the s-end of the transistor mp9 is connected to the input-output unit voltage VDDIO, the d-end of the transistor mp9 is connected to the d-end of the transistor mn9 and the g-end of the transistor mp11, the s-end of the transistor mn9 is connected to the ground line, the s-end of the transistor mn11 is connected to the input-output unit voltage VDDIO, the input signal VB2 is connected to the g-end of the transistor mp10 and the g-end of the transistor mn10 The s-end of the transistor mp10 is connected to the input-output unit voltage VDDIO, the d-end of the transistor mp10 is connected to the d-end of the transistor mn10 and the g-end of the transistor mn11, the s-end of the transistor mn10 is connected to the ground line, the s-end of the transistor mn11 is connected to the ground line, and the d-end of the transistor mp11 is connected to the d-end of the transistor mn11 and the power output signal VOUT; the driving circuit 823 implements the buffering and driving enhancement of the third signal VA2 and the fourth signal VB2 at the input end, ensuring that the power output signal VOUT can normally drive the external load of the circuit.

[0029] The working principle of the dual power supply three-state output circuit with power-on and power-off process output state control is as follows: 1) Working principle of logic control 821: Logic control 821 is powered by core logic voltage VDDC, and processes the power input signal VIN and enable control signal OE of the three-state output unit. When the enable control signal OE is at a low level, the first signal VA1 and the second signal VB1 at the output end of logic control 821 are in the same state as the power input signal VIN; when the enable control signal OE is at a high level, the first signal VA1 is at a high level and the second signal VB1 is at a low level; 2) Working principle of weak pull-up and pull-down level conversion circuit 822: The weak pull-up and pull-down level conversion circuit 822 is powered by the input-output unit voltage VDDIO and the core logic voltage VDDC at the same time. When the voltages VDDIO and VDDC are both powered normally, the output third signal VA2 and the fourth signal VB2 are respectively in the same state as the input first signal VA1 and the second signal VB1; when VDDIO is powered normally and VDDC is not powered, the third signal VA2 at the output end is low level and the fourth signal VB2 at the output end is high level; 3) Working principle of the driving circuit 823: The driving circuit 823 is powered by the input-output unit voltage (VDDC) to achieve enhanced driving of the internal signal. When the third signal VA2 and the fourth signal VB2 at the input end are both high, the power output signal VOUT is high; when the third signal VA2 and the fourth signal VB2 at the input end are both low, the power output signal VOUT is low; when the input signal VA2 is low and the fourth signal VB2 at the output end is high, the output signal is in a high impedance state; 4) Normal working mode: When the input and output unit voltage VDDIO and the core logic voltage VDDC are both powered normally, if the OE signal is low, the tri-state output unit works in the normal working mode, the power output signal VOUT changes with the power input signal VIN, and the two signals VOUT and VIN remain in the same state; 5) Normal tri-state mode: When the input and output unit voltage VDDIO and the core logic voltage VDDC are both powered normally, if the OE signal is high, the tri-state output unit works in the normal tri-state mode, and the power output signal VOUT is in a high impedance state; 6) Abnormal tri-state mode: When the input-output unit voltage VDDIO is normally powered, but the core logic voltage VDDC is not powered, the tri-state output unit works in the abnormal tri-state mode, and the power output signal VOUT is in a high-impedance state; 7) No-drive mode: When the input-output unit voltage VDDIO is not powered, regardless of whether the core logic voltage VDDC is powered, the tri-state output unit operates in the no-drive mode, and the power output signal VOUT has no driving capability.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] It should be noted that when a component is referred to as being "fixed to" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "connected to" another component, it may be directly connected to the other component or there may be a central component at the same time. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0033] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any ordinary technician in the industry can smoothly implement the present invention as shown in the drawings and described above. However, any equivalent changes, modifications and evolutions made by technicians familiar with the profession without departing from the scope of the technical solution of the present invention using the technical content disclosed above are all equivalent embodiments of the present invention. At the same time, any equivalent changes, modifications and evolutions made to the above embodiments based on the essential technology of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A dual power supply three-state output circuit with power-on and power-off process output state control, characterized in that: include, Logic control circuit 821, weak pull-up and pull-down level conversion circuit 822, driving circuit 823; The input end of the logic control circuit 821 is connected to the enable control signal OE and the power input signal VIN, the output end of the logic control circuit 821 is connected to the input end of the weak pull-up and pull-down level conversion circuit 822 through the first signal VA1 and the second signal VB1, the output end of the weak pull-up and pull-down level conversion circuit 822 is connected to the input end of the drive circuit 823 through the third signal VA2 and the fourth signal VB2, and the output end of the drive circuit 823 is connected to the power output signal VOUT; The logic control circuit 821 is powered by the core logic voltage VDDC, the weak pull-up and pull-down level conversion circuit 822 is powered by the input-output unit voltage VDDIO and the core logic voltage VDDC, and the driving circuit 823 is powered by the input-output unit voltage VDDIO.

2. A dual power supply three-state output circuit with power-on and power-off process output state control according to claim 1, characterized in that: When the input-output unit voltage VDDIO and the core logic voltage VDDC are both powered normally, if the enable control signal OE is at a low level, the dual-power tri-state output circuit operates in a normal working mode, and the power output signal VOUT changes with the power input signal VIN, and the power output signal VOUT maintains the same state as the power input signal VIN.

3. A dual power supply three-state output circuit with power-on and power-off process output state control according to claim 1, characterized in that: When the input and output unit voltage VDDIO and the core logic voltage VDDC are both powered normally, if the enable control signal OE is at a high level, the dual power tri-state output circuit operates in a normal tri-state mode, and the power output signal VOUT is in a high impedance state.

4. A dual power supply three-state output circuit with power-on and power-off process output state control according to claim 1, characterized in that: When the input-output unit voltage VDDIO is normally powered, but the core logic voltage VDDC is not powered, the dual-power tri-state output circuit operates in an abnormal tri-state mode, and the power output signal VOUT is in a high-impedance state.

5. A dual power supply three-state output circuit with power-on and power-off process output state control according to claim 1, characterized in that: When the input-output unit voltage VDDIO is not powered, regardless of whether the core logic voltage VDDC is powered, the dual-power tri-state output circuit operates in a no-drive mode, and the power output signal VOUT has no drive capability.

6. A dual power supply three-state output circuit with power-on and power-off process output state control according to claim 1, characterized in that: The logic control circuit 821 includes an inverter, a two-input NAND gate, and a two-input NOR gate.

7. A dual power supply three-state output circuit with power-on and power-off process output state control according to claim 1, characterized in that: The weak pull-up and pull-down level conversion circuit 822 includes 8 pmos transistors and 8 nmos transistors.

8. A dual power supply three-state output circuit with power-on and power-off process output state control according to claim 1, characterized in that: The driving circuit 823 includes 3 pmos transistors and 3 nmos transistors.

9. A working method of a dual power supply three-state output circuit with output state control during power-on and power-off processes according to any one of claims 1 to 8, characterized in that: The logic control circuit 821 is powered by the core logic voltage VDDC. When the enable control signal OE is at a low level, the first signal VA1 and the second signal VB1 at the output end of the logic control 821 are in the same state as the power input signal VIN; when the enable control signal OE is at a high level, the first signal VA1 is at a high level and the second signal VB1 is at a low level. The weak pull-up and pull-down level conversion circuit 822 is powered by the input-output unit voltage VDDIO and the core logic voltage VDDC at the same time. When the input-output unit voltage VDDIO and the core logic voltage VDDC are both powered normally, the third signal VA2 and the fourth signal VB2 at the output end of the weak pull-up and pull-down level conversion circuit 822 are respectively in the same state as the first signal VA1 and the second signal VB1 at the input end of the weak pull-up and pull-down level conversion circuit 822; when the input-output unit voltage VDDIO is powered normally and the core logic voltage VDDC is not powered, the third signal VA2 at the output end of the weak pull-up and pull-down level conversion circuit 822 is at a low level and the fourth signal VB2 is at a high level; The driving circuit 823 is powered by the input-output unit voltage VDDC. When the third signal VA2 and the fourth signal VB2 at the input end of the driving circuit 823 are both high, the power output signal VOUT is high; when the third signal VA2 and the fourth signal VB2 at the input end of the driving circuit 823 are both low, the power output signal VOUT is low; when the third signal VA2 at the input end is low and the fourth signal VB2 at the output end is high, the power output signal VOUT is in a high impedance state.

10. An integrated circuit with a dual power supply three-state output circuit and output state control during power-on and power-off processes according to any one of claims 1 to 8, characterized in that: It includes three input control signals, three power input signals and three dual power three-state output circuits with power-on and power-off process output state control; Each input control signal and power input signal is respectively connected to the input end of a dual power three-state output circuit with power-on and power-off process output state control, and the output ends of the three dual power three-state output circuits with power-on and power-off process output state control are all connected to the bus.

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