LED driving system, chip, LED driving control circuit and method

Abstract

This invention provides an LED driving system, chip, LED driving control circuit, and method, including: an overcurrent detection module that generates an overcurrent detection signal for the output current; a maximum on-time control module that sets the maximum on-time; a negative voltage detection module that generates a negative voltage detection signal for the driving signal; a maximum off-time control module that sets the maximum off-time; a noise reduction module that generates a turn-off end signal when the power switch is turned off for a preset time when the power supply voltage is abnormal; a logic control module that generates a PWM signal; and a driving module that generates a driving signal. This invention adds a noise reduction mode, which shortens the off-time of the power switch so that the operating frequency in noise reduction mode exceeds the range perceptible to the human ear, providing a better user experience; it also adaptively delays the negative voltage detection signal, causing the drain voltage of the power switch to drop to a preset voltage before switching back to 0V, improving efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to an LED driving system, chip, LED driving control circuit and method. Background Technology

[0002] In the past, most LED constant current driver chips (circuits) used electrolytic capacitors externally (inside the circuit) in practical applications. However, with the market demand for LED driver chips in high-frequency fields and considerations for cost reduction, electrolytic capacitors are gradually being replaced by ceramic capacitors, which are more suitable for high-frequency and high-voltage circuits. Ceramic capacitors have advantages such as high dielectric constant, good stability, and small size. However, ceramic capacitors will expand and contract (vibrate) due to the piezoelectric effect when voltage is applied. When the vibration period is within the range that the human ear can perceive (generally 20Hz to 20KHz), the human ear will hear a ringing sound, i.e., "whistling".

[0003] In existing chip (circuit) designs, when connected to ceramic capacitors (as an example, acting as input capacitors), a power-down whistling phenomenon occurs because the signal frequency during power-down is within the range perceptible to the human ear. How to avoid this power-down whistling phenomenon and improve the customer experience has become one of the urgent problems to be solved by those skilled in the art.

[0004] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an LED driving system, chip, LED driving control circuit and method to solve the problem of power-down whistling when using ceramic capacitors in the LED constant current driving circuit in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides an LED driving control circuit, the LED driving control circuit comprising at least:

[0007] Overcurrent detection module, maximum on-time control module, negative pressure detection module, maximum off-time control module, anti-whistling module, logic control module and driver module;

[0008] The overcurrent detection module detects the output current of the LED and generates an overcurrent detection signal when the output current exceeds the preset peak current.

[0009] The maximum conduction time control module times the conduction time of the power switch that controls the output current, and generates a maximum conduction signal when the preset maximum conduction time is reached.

[0010] The negative voltage detection module detects the voltage of the drive signal of the power switch tube, and generates a negative voltage detection signal when the voltage of the drive signal is detected to be less than zero.

[0011] The maximum turn-off time control module times the turn-off time of the power switch and generates a maximum turn-off signal when the preset maximum turn-off time is reached.

[0012] The anti-whistling module is connected to the output terminals of the overcurrent detection module, the maximum on-time control module, the maximum off-time control module, and the logic control module. When the overcurrent detection signal and the negative voltage detection signal cannot be detected, and the maximum on-time signal and the maximum off-time signal alternate, a turn-off end signal is generated when the power switch is turned off for a preset time. The frequency corresponding to the sum of the maximum on-time and the preset time is outside the range that the human ear can perceive.

[0013] The logic control module generates a PWM signal to control the power switch to turn on and off based on the output signals of the overcurrent detection module, the maximum on-time control module, the negative voltage detection module, the maximum off-time control module, and the anti-whistling module;

[0014] The drive module is connected to the output of the logic control module and generates the drive signal for the power switch based on the PWM signal.

[0015] Optionally, the preset time is less than 10 μs.

[0016] Optionally, the noise reduction module includes a power-down detection unit, a delay unit, and a logic unit;

[0017] The power-down detection unit receives the overcurrent detection signal, the maximum on signal, and the maximum off signal. When the overcurrent detection signal is valid, it generates a first judgment signal; when the overcurrent detection signal is invalid and the maximum on signal and the maximum off signal appear alternately, it generates a second judgment signal.

[0018] The delay unit receives the PWM signal and generates the shutdown end signal when the falling edge of the PWM signal is delayed to the preset time.

[0019] The logic unit is connected to the output of the power-down detection unit and the delay unit. When the first judgment signal is valid, the shutdown end signal is blocked. When the second judgment signal is valid, the shutdown end signal is output.

[0020] Alternatively, the power-down detection unit includes a first RS flip-flop, a second RS flip-flop, and a frequency divider;

[0021] The set terminal of the first RS flip-flop is connected to the maximum turn-on signal, and the reset terminal is connected to the maximum turn-off signal;

[0022] The clock terminal of the frequency divider is connected to the output terminal of the first RS flip-flop, and the reset terminal is connected to the overcurrent detection signal to divide the output signal of the first RS flip-flop.

[0023] The set terminal of the second RS flip-flop is connected to the overcurrent detection signal, the reset terminal is connected to the output terminal of the frequency divider, and the inverting output terminal outputs either the first judgment signal or the second judgment signal.

[0024] Alternatively, the frequency divider is a divide-by-two circuit composed of two D flip-flops.

[0025] Alternatively, the delay unit includes a current source, a first capacitor, a switching transistor, and a Schmitt trigger;

[0026] One end of the current source is connected to the power supply voltage, and the other end is connected to the upper plate of the first capacitor; the lower plate of the first capacitor is grounded; the switching transistor is connected in parallel across the two ends of the first capacitor, and the control terminal receives the PWM signal; the input terminal of the Schmitt trigger is connected to the upper plate of the first capacitor, and outputs the turn-off end signal.

[0027] Alternatively, the logic unit is a NAND gate.

[0028] Alternatively, the LED drive control circuit may further include an adaptive delay module;

[0029] The adaptive delay module is connected between the negative voltage detection module and the logic control module, and receives the drain voltage of the power switch. When the negative voltage detection signal is valid, the negative voltage detection signal is delayed based on the falling slope of the drain voltage of the power switch, so that the drain voltage of the power switch gradually decreases to a preset voltage and then the power switch is turned on; wherein, the delay time is negatively correlated with the falling slope.

[0030] Alternatively, the adaptive delay module includes a slope detection unit, a second capacitor, a comparator, and an AND logic unit;

[0031] The slope detection unit receives the negative voltage detection signal and the drain voltage of the power switch. When the negative voltage detection signal is valid, it detects the falling slope of the drain voltage of the power switch and converts it into a corresponding current signal.

[0032] The upper plate of the second capacitor is connected to the output terminal of the slope detection unit, and the lower plate is grounded;

[0033] The non-inverting input of the comparator is connected to the upper plate of the second capacitor, the inverting input receives the reference voltage, and the comparator outputs the comparison result.

[0034] One end of the logic unit is connected to the output of the comparator, and the other end receives the negative pressure detection signal and outputs a delayed signal of the negative pressure detection signal.

[0035] Optionally, the LED driving control circuit further includes a power supply module and a protection module; the power supply module provides power voltage to the LED driving control circuit; and the protection module provides protection signals.

[0036] To achieve the above and other related objectives, the present invention also provides a chip, the chip comprising at least the above-described LED driving control circuit.

[0037] To achieve the above and other related objectives, the present invention also provides an LED driving system, the LED driving system comprising at least:

[0038] Switching power supply circuit, LED load, ceramic capacitor and the aforementioned LED driver control circuit;

[0039] The switching power supply circuit is connected to the LED load and provides drive current to the LED load based on the on and off states of the power switching transistor.

[0040] The LED driver control circuit is connected to the switching power supply circuit and provides a drive signal to the power switching transistor in the switching power supply circuit; the ceramic capacitor is connected to the LED driver control circuit.

[0041] To achieve the above and other related objectives, the present invention also provides an LED driving control method, the LED driving method comprising at least:

[0042] In normal operating mode, the overcurrent detection signal of the LED output current and the negative voltage detection signal of the power switch drive signal are detected. When the overcurrent detection signal is valid, the power switch is controlled to turn off, and when the negative voltage detection signal is valid, the power switch is controlled to turn on.

[0043] As the power supply voltage drops, the overcurrent detection signal and the negative voltage detection signal cannot be detected, and the system enters an abnormal operating mode. At this time, when the conduction time of the power switch reaches the preset maximum conduction time, the power switch is controlled to turn off, and when the turn-off time of the power switch reaches the preset maximum turn-off time, the power switch is controlled to turn on.

[0044] The power supply voltage continuously decreases, making it impossible to detect the overcurrent detection signal and the negative voltage detection signal. Furthermore, the on-time and off-time of the power switch alternately reach the maximum on-time and the maximum off-time, entering a de-whistling mode. At this time, when the on-time of the power switch reaches the preset maximum on-time, the power switch is controlled to turn off. After the power switch has been off for a preset time, the power switch is controlled to turn on. The frequency corresponding to the sum of the maximum on-time and the preset time exceeds the range perceptible to the human ear.

[0045] Optionally, the preset time is less than 10 μs.

[0046] Optionally, the LED driving control method further includes: when the negative voltage detection signal is valid, delaying the negative voltage detection signal based on the falling slope of the drain voltage of the power switch, so that the drain voltage of the power switch gradually decreases to a preset voltage and then the power switch is turned on; wherein the delay time is negatively correlated with the falling slope.

[0047] As described above, the LED driving system, chip, LED driving control circuit, and method of the present invention have the following beneficial effects:

[0048] 1. The LED driving system, chip, LED driving control circuit and method of the present invention have added a noise reduction mode. By shortening the turn-off time of the power switching transistor, the operating frequency in the noise reduction mode is >20KHz, which is beyond the range that the human ear can perceive, thereby realizing the noise reduction function after power-off; thus solving the problem of noise generated by the application of ceramic capacitors, and giving users a good user experience.

[0049] 2. The LED driving system, chip, LED driving control circuit and method of the present invention adaptively delay the negative voltage detection signal, so that the drain voltage of the power switch tube drops to a preset voltage before switching to 0V, thereby improving efficiency and customer experience. Attached Figure Description

[0050] Figure 1 The diagram shown is a structural schematic of an LED driver control circuit.

[0051] Figure 2 Displayed as Figure 1A waveform diagram of key nodes when the LED driver control circuit is working normally.

[0052] Figure 3 Displayed as Figure 1 A waveform diagram of a key node when the LED driver control circuit malfunctions.

[0053] Figure 4 Displayed as Figure 1 A schematic diagram illustrating the principle behind the low efficiency of LED driver control circuits.

[0054] Figure 5 The diagram shown is a structural schematic of the LED driving control circuit of the present invention.

[0055] Figure 6 The diagram shown is a structural schematic of the anti-whistling module of the present invention.

[0056] Figure 7 The diagram shown is a structural schematic of the power-down detection module unit of the present invention.

[0057] Figure 8 The diagram shown is a structural schematic of the delay unit of the present invention.

[0058] Figure 9 The diagram shown is another structural schematic of the LED driving control circuit of the present invention.

[0059] Figure 10 The diagram shown is a structural schematic of the adaptive delay module of the present invention.

[0060] Figure 11 The diagram shown is a structural schematic of the LED driving system of the present invention.

[0061] Figure 12 The diagram shown illustrates the principle of the LED driving control method for eliminating whistling according to the present invention.

[0062] Figure 13 The diagram shows the principle of improving efficiency using the LED driving control method of the present invention.

[0063] Component designation explanation

[0064] 1- LED driver control circuit one; 11- Overcurrent detection module one; 12- Maximum on-time control module one; 13- Negative voltage detection module one; 14- Maximum off-time control module one; 15- Logic control module one; 16- Driver module one; 2- LED driver control circuit two; 20- Overcurrent detection module two; 21- Maximum on-time control module two; 22- Negative voltage detection module two; 23- Maximum off-time control module two; 24- Anti-whistling module; 241- Power-down detection unit; 241a- First RS flip-flop; 241b- Frequency divider; 241c- Second RS flip-flop; 242- Delay unit; 242a- Schmitt trigger; 243- Logic unit; 25- Logic control module two; 251- First logic control unit; 252- Second logic control unit; 253- PWM signal generation unit; 26-Drive module two; 27-Power supply module; 28-Protection module; 29-Adaptive delay module; 291-Slope detection unit; 292-Comparator; 293-AND logic unit; 3-Switching power supply circuit. Detailed Implementation

[0065] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0066] Please see Figures 1-13 As shown. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0067] like Figure 1The diagram shows an LED driver control circuit 1, comprising: an overcurrent detection module 11, a maximum on-time control module 12, a negative voltage detection module 13, a maximum off-time control module 14, a logic control module 15, and a driver module 16. The logic control module 15 generates a PWM signal of corresponding level based on the output signals of the overcurrent detection module 11 and the maximum on-time control module 12, and controls the power switch (not shown) to turn off through the drive signal DRV output by the driver module 16; the logic control module 15 also generates a PWM signal of corresponding level based on the output signals of the negative voltage detection module 13 and the maximum off-time control module 14, and controls the power switch to turn on through the drive signal DRV output by the driver module 16.

[0068] like Figure 2 As shown, when the LED driver control circuit 1 is in normal operating condition (normal power supply), the negative voltage detection module 13 detects the drive signal DRV of the power transistor switch. After detecting a negative voltage, the negative voltage detection signal ZC becomes valid, and the logic control module 15 controls the PWM signal to flip from low to high level. Simultaneously, the overcurrent detection module 11 detects the sampling voltage Vcs. When the sampling voltage Vcs reaches a set voltage, the output current Iout is considered to have reached the set peak current Ipk, and the overcurrent detection signal OC becomes valid. The logic control module 15 then controls the PWM signal to flip from high to low level. Since the peak value of the output current Iout is constant, the average value of the output current Iout is also constant, thus achieving constant current drive.

[0069] like Figure 3 As shown, when the LED driver control circuit 1 is in an abnormal operating state (including but not limited to the power-down process), the power supply voltage of the LED driver control circuit 1 will gradually decrease and gradually approach the voltage of the load LED. At this time, the effective overcurrent detection signal OC cannot be detected. The maximum conduction time is set by the maximum conduction time control module 12. When the output signal Tonmax of the maximum conduction time control module 12 is valid, the PWM signal is controlled by the logic control module 15 to switch from high level to low level. Considering that the LED drive control circuit 1 operates at low frequency, the maximum conduction time... It is typically set to tens of microseconds; simultaneously, as the power supply voltage decreases, the effective negative voltage detection signal ZC is no longer detected. At this time, the maximum shutdown time is set through the maximum shutdown time control module 14. When the output signal Toffmax of the maximum shutdown time control module 14 is valid, the logic control module 15 controls the PWM signal to switch from low to high level. To reduce the short-circuit power consumption of the system output, the maximum shutdown time... It is set to a period of several hundred microseconds. In this state, the period of the PWM signal... The frequency is on the order of several hundred microseconds, which is within the range that the human ear can perceive, and therefore it will produce a whistling sound during use.

[0070] Furthermore, according to the above control logic, when a negative voltage is detected (negative voltage detection signal ZC is valid), the drive signal DRV quickly switches from low to high level. This causes the drain voltage Vsw of the power switch to quickly switch from a high voltage close to the external power supply voltage to 0V. Figure 4 As shown, this high voltage falls on the power switching transistor, resulting in low efficiency.

[0071] To address the aforementioned problems, this invention proposes an LED driving system, a chip, an LED driving control circuit, and a method. Figure 1 Based on the LED driver control circuit 1, a power-down noise reduction mode is added, and the switching logic of the PWM signal is optimized so that the signal frequency during the power-down process exceeds the range that the human ear can perceive, so as to realize the noise reduction function and improve the efficiency during normal operation.

[0072] Example 1

[0073] like Figure 5 As shown, the present invention provides an LED driving control circuit 2, which includes:

[0074] Overcurrent detection module 20, maximum on-time control module 21, negative pressure detection module 22, maximum off-time control module 23, de-whistling module 24, logic control module 25, and drive module 26.

[0075] like Figure 5 As shown, the overcurrent detection module 20 detects the output current Iout of the LED and generates an overcurrent detection signal OC when the output current Iout is greater than the preset peak current Ipk.

[0076] Specifically, in this embodiment, the overcurrent detection module 20 receives a sampling voltage Vcs, which samples the output current Iout of the LED. For example, the sampling voltage Vcs is the voltage across the sampling resistor at the source terminal of the power switch. The overcurrent detection module 20 has an internal set voltage; when the sampling voltage Vcs reaches the set voltage, it outputs the overcurrent detection signal OC (indicating that the output current Iout has reached the set peak current Ipk).

[0077] like Figure 5 As shown, the maximum conduction time control module 21 times the conduction time of the power switch transistor that controls the output current, and reaches the preset maximum conduction time. The maximum conduction signal Tonmax is generated at this time.

[0078] Specifically, in this embodiment, the maximum on-time control module 21 receives the PWM signal and counts the high-level time of the PWM signal (i.e., the on-time of the power switch). When the high-level time of the PWM signal reaches the maximum on-time... When the maximum conduction signal Tonmax is output, the maximum conduction signal Tonmax is output; as an example, the maximum conduction signal Tonmax is a positive pulse.

[0079] like Figure 5 As shown, the negative voltage detection module 22 detects the voltage of the drive signal DRV of the power switch tube, and generates a negative voltage detection signal ZC when the voltage of the drive signal DRV is less than zero.

[0080] Specifically, in this embodiment, the negative pressure detection module 22 receives the driving signal DRV and compares the driving signal DRV with the reference signal (0V). When the voltage of the driving signal DRV is less than 0V, the negative pressure detection signal ZC is output.

[0081] like Figure 5 As shown, the maximum turn-off time control module 23 times the turn-off time of the power switch transistor and reaches the preset maximum turn-off time. The maximum shutdown signal Toffmax is generated at this time.

[0082] Specifically, in this embodiment, the maximum turn-off time control module 23 receives the PWM signal and counts the time the PWM signal is low (i.e., the turn-off time of the power switch). When the time the PWM signal is low reaches the maximum turn-off time... When the maximum shutdown signal Toffmax is output, the maximum shutdown signal Toffmax is output; as an example, the maximum shutdown signal Toffmax is a positive pulse.

[0083] like Figure 5 As shown, the anti-whistling module 24 is connected to the output terminals of the overcurrent detection module 20, the maximum on-time control module 21, the maximum off-time control module 23, and the logic control module 25. When the overcurrent detection signal OC and the negative voltage detection signal ZC cannot be detected, and the maximum on-time signal Tonmax and the maximum off-time signal Toffmax alternate, the power switch is turned off for a preset time. The shutdown end signal PWM_delay is generated at this time.

[0084] Specifically, such as Figure 6 As shown, in this embodiment, the noise reduction module 24 includes a power-down detection unit 241, a delay unit 242, and a logic unit 243.

[0085] More specifically, such as Figure 6 As shown, the power-down detection unit 241 receives the overcurrent detection signal OC, the maximum on signal Tonmax, and the maximum off signal Toffmax. When the overcurrent detection signal OC is valid, a first judgment signal is generated; when the overcurrent detection signal OC is invalid, and the maximum on signal Tonmax and the maximum off signal Toffmax alternate, a second judgment signal is generated. In this example, the first judgment signal and the second judgment signal are represented by different levels of the output signal VINOFF of the power-down detection unit 241. Figure 7As shown in the figure, as an example, the power-down detection unit 241 includes a first RS flip-flop 241a, a frequency divider 241b, and a second RS flip-flop 241c; the set terminal S of the first RS flip-flop 241a is connected to the maximum turn-on signal Tonmax, the reset terminal R is connected to the maximum turn-off signal Toffmax, and the output terminal Q outputs a trigger signal. The clock input CLK of the frequency divider 241b is connected to the output Q of the first RS flip-flop 241a, and the reset input RST is connected to the overcurrent detection signal OC, thus dividing the output signal of the first RS flip-flop 241a. In this example, the frequency divider 241b is a divide-by-two circuit composed of two D flip-flops. Specifically, the clock input CLK of the first D flip-flop is connected to the output Q of the first RS flip-flop 241a, and the data input D of the first D flip-flop is connected to the inverted output QB. The clock input CLK of the second D flip-flop is connected to the inverted output QB of the first D flip-flop, and the data input D of the second D flip-flop is connected to the inverted output QB and outputs the divided signal. In practical use, the frequency divider can be configured as a divide-by-four or divide-by-six circuit, as long as it reflects the alternation of the maximum turn-on signal Tonmax and the maximum turn-off signal Toffmax. Of course, the larger the division number of the frequency divider, the longer the delay time (i.e., the longer the response time) in detecting the drop in power supply voltage. The set terminal S of the second RS flip-flop 241c is connected to the overcurrent detection signal OC, the reset terminal R is connected to the output terminal of the frequency divider 241b, and the inverting output terminal QB outputs either the first judgment signal or the second judgment signal. Any circuit structure capable of detecting a drop in power supply voltage is applicable to this invention and is not limited to this embodiment.

[0086] More specifically, such as Figure 6 As shown, the delay unit 242 receives the PWM signal, and delays the falling edge of the PWM signal to the preset time. The shutdown end signal PWM_delay is generated at that time. Figure 8As shown in the example, the delay unit 242 includes a current source I1, a first capacitor C1, a switching transistor M1, and a Schmitt trigger 242a. One end of the current source I1 is connected to the power supply voltage, and the other end is connected to the upper plate of the first capacitor C1; the lower plate of the first capacitor C1 is grounded. The switching transistor M1 is connected in parallel across the first capacitor C1, and the control terminal receives the PWM signal. In this embodiment, the switching transistor M1 is implemented using an NMOS transistor, with its drain connected to the upper plate of the first capacitor C1, its source grounded, and its gate connected to the PWM signal. The input terminal of the Schmitt trigger 242a is connected to the upper plate of the first capacitor C1, and it outputs the turn-off end signal PWM_delay. When the PWM signal is high, the switching transistor M1 is turned on, and the first capacitor C1 discharges rapidly; when the PWM signal is low, the switching transistor M1 is turned off, and the current source I1 charges the first capacitor C1; the delay time is calculated from the falling edge of the PWM signal until the preset time has elapsed. The shutdown end signal PWM_delay is output after a delay; as an example, the shutdown end signal PWM_delay is a positive pulse. Any circuit structure that generates the shutdown end signal by delaying the falling edge of the PWM signal to a preset time is applicable to the present invention and is not limited to this embodiment.

[0087] More specifically, such as Figure 6 As shown, the logic unit 243 is connected to the output terminals of the power-down detection unit 241 and the delay unit 242. When the first judgment signal is valid, the shutdown end signal PWM_dealy is masked; when the second judgment signal is valid, the shutdown end signal PWM_dealy is output. In this embodiment, the first judgment signal is active low, and the second judgment signal is active high. Figure 6 As shown in the example, the logic unit 243 is a NAND gate. The first input of the NAND gate is connected to the output of the power-down detection unit 241, and the second input is connected to the output of the delay unit 242. When the power-down detection unit 241 outputs a low level, the NAND gate outputs a low level (the shutdown end signal PWM_dealy is masked). When the power-down detection unit 241 outputs a high level, the NAND gate outputs the shutdown end signal PWM_dealy. Any circuit structure that can control the output or masking of the PWM signal based on the judgment signal is applicable to the present invention and is not limited to this embodiment.

[0088] It should be noted that the maximum conduction time With the preset time The setting meets the condition: the maximum conduction time With the preset time The sum of these frequencies exceeds the range perceptible to the human ear. Considering that the LED drive control circuit 2 operates at low frequencies, the maximum conduction time... The preset time is typically set to tens of μs; The timeframe is typically set to within 100 μs, preferably less than 10 μs; in this example... If the frequency is less than 50μs, then the frequency of the PWM signal in the anti-whispering mode is greater than 20KHz, which is beyond the range that the human ear can perceive, thus achieving the anti-whispering function.

[0089] like Figure 5 As shown, the logic control module 25 generates a PWM signal to control the power switch to turn on and off based on the output signals of the overcurrent detection module 20, the maximum on-time control module 21, the negative pressure detection module 22, the maximum off-time control module 23, and the noise reduction module 24.

[0090] Specifically, when the overcurrent detection signal OC and the negative voltage detection signal ZC can be detected, a PWM signal is generated based on the overcurrent detection signal OC and the negative voltage detection signal ZC to control the power switch to turn on and off; when the overcurrent detection signal OC and the negative voltage detection signal ZC cannot be detected, the PWM signal is generated based on the maximum on signal Tonmax and the maximum off signal Toffmax; when the overcurrent detection signal OC and the negative voltage detection signal ZC cannot be detected, and the maximum on signal Tonmax and the maximum off signal Toffmax alternate, the PWM signal is generated based on the maximum on signal Tonmax and the off-end signal PWM_delay.

[0091] Specifically, such as Figure 5As shown, in this embodiment, the logic control module 25 includes a first logic control unit 251, a second logic control unit 252, and a PWM signal generation unit 253. The first logic control unit 251 receives the overcurrent detection signal OC and the maximum turn-on signal Tonmax, and generates a control signal to control the power switch to turn off based on the overcurrent detection signal OC or the maximum turn-on signal Tonmax under different operating states (normal operating state, abnormal operating state, and de-whistling operating state). The second logic control unit 252 receives the negative voltage detection signal ZC, the maximum turn-off signal Toffmax, and the turn-off end signal PWM_delay, and generates a control signal to control the power switch to turn on based on the negative voltage detection signal ZC, the maximum turn-off signal Toffmax, or the turn-off end signal PWM_delay under different operating states (normal operating state, abnormal operating state, and de-whistling operating state). The PWM signal generation unit 253 is connected to the output terminals of the first logic control unit 251 and the second logic control unit 252, and generates a PWM signal based on the control signals output by the first logic control unit 251 and the second logic control unit 252. In practical applications, any circuit structure that can generate a PWM signal to control the power switch based on the overcurrent detection signal OC, the maximum turn-on signal Tonmax, the negative voltage detection signal ZC, the maximum turn-off signal Toffmax, and the turn-off end signal PWM_delay is applicable to this invention.

[0092] like Figure 5 As shown, the second driving module 26 is connected to the output terminal of the second logic control module 25, and generates the driving signal DRV of the power switching transistor based on the PWM signal.

[0093] like Figure 5 As shown, in another implementation of the present invention, the LED driving control circuit 2 further includes a power supply module 27, which provides power voltage to the LED driving control circuit 2.

[0094] like Figure 5 As shown, as another implementation of the present invention, the LED driving control circuit 2 further includes a protection module 28, which is used to provide protection signals to improve reliability; including but not limited to over-temperature protection signals, over-voltage protection signals, and short-circuit protection signals, which will not be described in detail here.

[0095] This embodiment also provides a chip, which includes the LED driving control circuit 2.

[0096] Example 2

[0097] like Figure 9 As shown, this embodiment provides an LED driving control circuit 2 and a chip. The difference from the first embodiment is that the LED driving control circuit 2 further includes an adaptive delay module 29 to improve efficiency.

[0098] like Figure 9 As shown, the adaptive delay module 29 is connected between the negative voltage detection module 22 and the logic control module 25, and receives the drain voltage Vsw of the power switch. When the negative voltage detection signal ZC is valid, the negative voltage detection signal ZC is delayed based on the falling slope of the drain voltage Vsw of the power switch, so that the drain voltage Vsw of the power switch gradually decreases to a preset voltage Vset and then the power switch is turned on; wherein, the delay time is negatively correlated with the falling slope.

[0099] Specifically, such as Figure 10 As shown, in this embodiment, the adaptive delay module 29 includes a slope detection unit 291, a second capacitor C2, a comparator 292, and an AND logic unit 293. The slope detection unit 291 receives the negative voltage detection signal ZC and the drain voltage Vsw of the power switch. When the negative voltage detection signal ZC is valid, it detects the falling slope of the drain voltage Vsw of the power switch (the falling slope detection can be performed within a fixed time period, without needing to be performed during the entire falling process of the valid negative voltage detection signal ZC) and converts it into a corresponding current signal I2. The upper plate of the second capacitor C2 is connected to the output terminal of the slope detection unit 291, and the lower plate is grounded; the current signal I2 output by the slope detection unit 291 charges the second capacitor C2. The non-inverting input terminal of the comparator 292 is connected to the upper plate of the second capacitor C2, and the inverting input terminal receives the reference voltage Vref, outputting the comparison result. One end of the logic unit 293 is connected to the output of the comparator 292, and the other end receives the negative voltage detection signal ZC and outputs a delay signal ZC_DLY for the negative voltage detection signal. The delay time is related to the current signal I2 output by the slope detection unit 291. The greater the falling slope of the drain voltage Vsw of the power switch, the greater the current signal I2 output by the slope detection unit 291, and the shorter the delay time. The smaller the falling slope of the drain voltage Vsw of the power switch, the smaller the current signal I2 output by the slope detection unit 291, and the longer the delay time.

[0100] It should be noted that in this embodiment, the current signal I2 is calculated by detecting the slope, and then the second capacitor C2 is charged using this current. After reaching the set voltage (that is, the switching voltage of the drain voltage Vsw of the power switch: the preset voltage Vset), the PWM signal flips. In other words, the purpose of setting the delay time is to allow the drain voltage Vsw of the power switch to drop to the preset voltage Vset. Any circuit structure that can cause the drain voltage Vsw of the power switch to drop to the preset voltage Vset before conduction is applicable to this invention and is not limited to this embodiment.

[0101] The other structures and principles are the same as in Embodiment 1, and will not be described in detail here.

[0102] Example 3

[0103] like Figure 11 As shown, this embodiment provides an LED driving system, which includes:

[0104] The LED driver control circuit 2, the switching power supply circuit 3, the LED load, and the ceramic capacitor C3 are described.

[0105] like Figure 11 As shown, the switching power supply circuit 3 is connected to the LED load and provides driving current to the LED load based on the on and off states of the power switching transistor.

[0106] Specifically, the structure of the switching power supply circuit 3 is not limited; any circuit structure capable of regulating the drive current based on the power switching transistor is applicable, including but not limited to BUCK, BOOST, BUCK-BOOST, forward, and flyback converters. For example... Figure 11 As shown in the figure, as an example, the switching power supply circuit 3 includes a power switch M2, a freewheeling diode D, an inductor L, a capacitor C4, and a sampling resistor Rcs; the cathode of the freewheeling diode D is connected to the bus voltage Vbus, and the anode is connected to the drain of the power switch M2; the upper plate of the capacitor C4 is connected to the cathode of the freewheeling diode D, and the lower plate is connected to the anode of the freewheeling diode D via the inductor L; the source of the power switch is grounded via the sampling resistor Rcs, and the gate receives the driving signal DRV provided by the LED driving control circuit 2.

[0107] Specifically, in this example, the positive terminal of the LED load is connected to the upper plate of the capacitor C4, and the negative terminal is connected to the lower plate of the capacitor C4.

[0108] like Figure 11 As shown, the LED driving control circuit 2 is connected to the switching power supply circuit 3 and provides a driving signal DRV to the power switching transistor M2 in the switching power supply circuit 3.

[0109] Specifically, the LED driving control circuit 2 adopts the structure of Embodiment 1 or Embodiment 2, which will not be described in detail here.

[0110] like Figure 11 As shown, the ceramic capacitor C3 is connected to the LED driver control circuit 2.

[0111] Specifically, in this embodiment, the ceramic capacitor C3 serves as the input capacitor of the LED driving control circuit 2. In actual use, the ceramic capacitor C3 can be configured with corresponding functions and connections as needed, which will not be elaborated here.

[0112] The LED driving system of this invention solves the problem of howling caused by the application of ceramic capacitors, giving users a better user experience.

[0113] Example 4

[0114] like Figure 12 As shown, this embodiment provides an LED driving control method. In this embodiment, the LED driving method is implemented based on the LED driving control circuit 2 of Embodiment 1 or Embodiment 2. In actual use, any hardware circuit that can implement this method is applicable. The LED driving method includes:

[0115] 1) In normal operating mode, the overcurrent detection signal OC of the LED output current and the negative voltage detection signal ZC of the power switch drive signal are detected. When the overcurrent detection signal OC is valid, the power switch M2 is controlled to turn off. When the negative voltage detection signal ZC is valid, the power switch M2 is controlled to turn on.

[0116] Specifically, such as Figure 12 As shown, in normal operating mode, the power supply voltage Vin provides normal power, and the LED output current Iout can reach the preset peak current Ipk. The gate voltage (voltage of the drive signal DRV) of the power switch M2 will then exhibit a negative voltage. At this time, the overcurrent detection module 20 performs overcurrent detection on the LED output current Iout, and the negative voltage detection module 22 detects the gate voltage of the power switch M2. When the overcurrent detection signal OC is detected, the power switch M2 is turned off; when the negative voltage detection signal ZC is detected, the power switch M2 is turned on, thereby achieving constant current control. For details, please refer to [link to relevant documentation]. Figure 1 The working principle will not be elaborated here.

[0117] It should be noted that in this state, the de-whistling module 24 outputs a low level, and the de-whistling function is not enabled.

[0118] 2) As the power supply voltage Vin decreases, the overcurrent detection signal OC and the negative voltage detection signal ZC cannot be detected, and the system enters an abnormal operating mode; at this time, when the conduction time of the power switch M2 reaches the preset maximum conduction time... The power switch M2 is turned off in a timely manner. When the turn-off time of the power switch M2 reaches the preset maximum turn-off time... The power switch M2 is turned on at the specified time.

[0119] Specifically, such as Figure 12 As shown, when the circuit is in an abnormal operating state (including but not limited to the power-down process), the power supply voltage Vin gradually decreases and gradually approaches the voltage Vout of the load LED. At this time, the output current Iout of the LED cannot reach the preset peak current Ipk, and the gate voltage of the power switch M2 cannot detect a negative voltage. Therefore, based on the maximum conduction time... and the maximum shutdown time The specific principle of controlling the turn-off and turn-on of the power switch M2 can be found in [reference needed]. Figure 1 The working principle will not be elaborated here.

[0120] 3) The power supply voltage Vin continuously decreases, making it impossible to detect the overcurrent detection signal OC and the negative voltage detection signal ZC, and the on-time and off-time of the power switch M2 alternately reach the maximum on-time. and the maximum shutdown time Entering the de-screeching mode; at this time, when the conduction time of the power switch M2 reaches the preset maximum conduction time. The power switch M2 is turned off at a set time. Then, the power switch M2 is turned on; wherein, the maximum on-time is... With the preset time The sum of these frequencies corresponds to frequencies beyond the range that the human ear can perceive.

[0121] Specifically, such as Figure 12 As shown, when the overcurrent detection signal OC and the negative voltage detection signal ZC cannot be detected, and the on-time and off-time of the power switch M2 alternately reach the maximum on-time, and the maximum shutdown time The system determines that it needs to enter de-whistle mode. For example, as shown... Figure 7As shown, when the overcurrent detection signal OC is low, the frequency divider 241b is de-reset and begins to work. When the maximum turn-on signal Tonmax is 1, the output signal of the first RS flip-flop 241a is 1; when the maximum turn-off signal Toffmax is 1, the output signal of the first RS flip-flop 241a is 0; when both the maximum turn-on signal Tonmax and the maximum turn-off signal Toffmax are 0, the output signal of the first RS flip-flop 241a remains in the previous state. According to the generation logic of the maximum turn-on signal Tonmax and the maximum turn-off signal Toffmax, there will be no state where both the maximum turn-on signal Tonmax and the maximum turn-off signal Toffmax are 1 (because both the maximum turn-on signal Tonmax and the maximum turn-off signal Toffmax are generated by the PWM signal; the maximum turn-on signal Tonmax is 1 when the PWM signal is high, and the maximum turn-off signal Toffmax is 1 when the PWM signal is low). Therefore, when the maximum turn-on signal Tonmax and the maximum turn-off signal Toffmax appear alternately, the output signal of the first RS flip-flop 241a will present a square wave with alternating 0 and 1. This square wave serves as the clock signal of the frequency divider 241b. When the maximum turn-on signal Tonmax is received for the first time, the output signal of the first-stage D flip-flop flips (becomes 0), while the output signal of the second-stage D flip-flop does not flip (remains 0). When the maximum turn-off signal Toffmax is received for the first time, the output signal of the first-stage D flip-flop does not flip (remains 0), and the output signal of the second-stage D flip-flop also does not flip (remains 0). When the maximum turn-on signal Tonmax is received for the second time, the output signal of the first-stage D flip-flop flips again (becomes 1), and the output signal of the second-stage D flip-flop also flips (becomes 1). The inverted output signal VINOFF of the second RS flip-flop 241c is set to 1, entering the de-whistling mode. The de-whistling module is reset by the overcurrent detection signal OC. When the power supply voltage Vin returns to the normal operating voltage, the overcurrent detection signal OC is high, resetting the frequency divider 241b and the second RS flip-flop 241c. At this time, the inverted output signal VINOFF of the second RS flip-flop 241c is reset to 0, and the de-whistling mode is exited.

[0122] Specifically, such as Figure 12 As shown, when entering the de-whistling mode, the turn-off time of the power switch M2 is shortened to a preset time. So that the maximum conduction time With the preset time The sum of these frequencies exceeds the range perceptible to the human ear. In this embodiment, the preset time is set based on the delay unit 242. ,like Figure 8 As shown, the charging and discharging of the first capacitor C1 is controlled based on the PWM signal. When the PWM signal is low, the first capacitor C1 is slowly charged through the charging current. When the voltage on the first capacitor C1 reaches the toggling voltage of the Schmitt trigger 242a, the shutdown end signal PWM_delay becomes valid. As an example, the preset time... Set to less than 10μs, so that If the frequency is less than 50μs, then the frequency of the PWM signal in the anti-whistling mode is greater than 20KHz, thereby achieving the anti-whistling function.

[0123] like Figure 9 , Figure 10 and Figure 13 As shown, in another implementation of the present invention, the LED driving control method further includes: when the negative voltage detection signal ZC is valid, delaying the negative voltage detection signal based on the falling slope of the drain voltage Vsw of the power switch, so that the drain voltage of the power switch gradually decreases to a preset voltage and then the power switch is turned off; wherein, the delay time is negatively correlated with the falling slope.

[0124] Specifically, such as Figure 11 As shown, due to the series resonance generated by the coupling capacitor between inductor L and the power switch M2, after the inductor L's stored energy is depleted and a negative voltage is detected, the coupling capacitor discharges to charge inductor L, causing the drain voltage Vsw of the power switch to decrease. The magnitude of this decrease is controlled by the delay time. Figure 10 As shown, the drain voltage Vsw of the power switch is sampled at fixed time intervals, and the voltage difference between the start and end of the fixed time interval is calculated. This allows for the detection of the falling slope of the drain voltage Vsw and its conversion into a current signal I2. The voltage generated by charging the second capacitor C2 with this current is compared with the reference voltage Vref by the comparator 292. An appropriate delay time is adaptively determined (i.e., the larger the slope of SW falling, the larger the output current and the shorter the adaptive delay time; the smaller the slope of SW falling, the smaller the output current and the longer the adaptive delay time). This delay time allows the drain voltage Vsw of the power switch to drop to a lower preset voltage Vset. At this point, the drive signal DRV is controlled to flip from low to high (the power switch M2 is turned on), and the drain voltage Vsw of the power switch switches from a lower voltage to 0V, thus achieving an efficient design.

[0125] It should be noted that any method that can reduce the drain voltage Vsw of the power switch to a preset voltage Vset by delay before switching to 0V is applicable to the present invention.

[0126] In summary, this invention provides an LED driving system, chip, LED driving control circuit, and method, including: an overcurrent detection module, a maximum on-time control module, a negative voltage detection module, a maximum off-time control module, a noise reduction module, a logic control module, and a driving module. The overcurrent detection module detects the output current of the LED and generates an overcurrent detection signal when the output current exceeds a preset peak current. The maximum on-time control module times the on-time of the power switch controlling the output current and generates a maximum on-time signal when a preset maximum on-time is reached. The negative voltage detection module detects the voltage of the driving signal of the power switch and generates a negative voltage detection signal when the voltage of the driving signal is less than zero. The maximum off-time control module times the off-time of the power switch and generates a maximum off-time signal when a preset maximum off-time is reached. The signal; the anti-whistling module is connected to the output terminals of the overcurrent detection module, the maximum on-time control module, the maximum off-time control module, and the logic control module; when the overcurrent detection signal and the negative voltage detection signal cannot be detected, and the maximum on-time signal and the maximum off-time signal alternate, a turn-off end signal is generated when the power switch is turned off for a preset time; wherein, the frequency corresponding to the sum of the maximum on-time and the preset time exceeds the range that the human ear can perceive; the logic control module generates a PWM signal to control the on and off of the power switch based on the output signals of the overcurrent detection module, the maximum on-time control module, the negative voltage detection module, the maximum off-time control module, and the anti-whistling module; the drive module is connected to the output terminal of the logic control module and generates a drive signal for the power switch based on the PWM signal. The LED driving system, chip, LED driving control circuit, and method of this invention introduce a new anti-whistling mode. By shortening the turn-off time of the power switch, the operating frequency in anti-whistling mode is greater than 20kHz, exceeding the range perceptible to the human ear, thus achieving power-off anti-whistling functionality. This solves the problem of whistling caused by ceramic capacitors, providing users with a better experience. This invention also adaptively delays the negative voltage detection signal, causing the drain voltage of the power switch to drop to a preset voltage before switching to 0V, thereby improving efficiency and user experience. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0127] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An LED drive control circuit, characterized by, The LED driving control circuit at least comprises: An overcurrent detection module, a maximum on-time control module, a negative voltage detection module, a maximum off-time control module, a de-whistling module, a logic control module, a driving module and an adaptive delay module; The overcurrent detection module detects the output current of the LED and generates an overcurrent detection signal when the output current is greater than a preset peak current; The maximum on-time control module times the on-time of a power switch tube that controls the output current and generates a maximum on-time signal when the preset maximum on-time is reached; The negative voltage detection module detects the voltage of the driving signal of the power switch tube and generates a negative voltage detection signal when the voltage of the driving signal is less than zero; The maximum off-time control module times the off-time of the power switch tube and generates a maximum off-time signal when the preset maximum off-time is reached; The de-whistling module is connected to the output ends of the overcurrent detection module, the maximum on-time control module, the maximum off-time control module and the logic control module; when the overcurrent detection signal and the negative voltage detection signal cannot be detected and the maximum on-time signal and the maximum off-time signal appear alternately, a turn-off end signal is generated when the power switch tube is turned off for a preset time; the sum of the maximum on-time and the preset time corresponds to a frequency beyond the range recognizable by human ears; the de-whistling module comprises a power-down detection unit, a delay unit and a logic unit; the power-down detection unit receives the overcurrent detection signal, the maximum on-time signal and the maximum off-time signal, generates a first judgment signal when the overcurrent detection signal is valid, and generates a second judgment signal when the overcurrent detection signal is invalid and the maximum on-time signal and the maximum off-time signal appear alternately; the delay unit receives a PWM signal and generates the turn-off end signal when the falling edge of the PWM signal is delayed to the preset time; the logic unit is connected to the output ends of the power-down detection unit and the delay unit, masks the turn-off end signal when the first judgment signal is valid, and outputs the turn-off end signal when the second judgment signal is valid; The logic control module generates a PWM signal that controls the on and off of the power switch tube based on the output signals of the overcurrent detection module, the maximum on-time control module, the negative voltage detection module, the maximum off-time control module and the de-whistling module; The driving module is connected to the output end of the logic control module and generates the driving signal of the power switch tube based on the PWM signal; The adaptive delay module is connected between the negative voltage detection module and the logic control module and receives the drain voltage of the power switch tube; when the negative voltage detection signal is valid, the negative voltage detection signal is delayed based on the falling slope of the drain voltage of the power switch tube, so that the power switch tube is turned on after the drain voltage of the power switch tube gradually decreases to a preset voltage; the delay time is negatively correlated with the falling slope.

2. The LED drive control circuit of claim 1, wherein: The preset time is less than 10 microseconds.

3. The LED drive control circuit of claim 1, wherein: The power-off detection unit comprises a first RS flip-flop, a second RS flip-flop and a frequency divider; The set end of the first RS flip-flop is connected to the maximum conduction signal, and the reset end is connected to the maximum turn-off signal; The clock end of the frequency divider is connected to the output end of the first RS flip-flop, the reset end is connected to the overcurrent detection signal, and the output signal of the first RS flip-flop is frequency-divided; The set end of the second RS flip-flop is connected to the overcurrent detection signal, the reset end is connected to the output end of the frequency divider, and the inverted output end outputs the first judgment signal or the second judgment signal.

4. The LED drive control circuit of claim 3, wherein: The frequency divider is a two-stage D flip-flop two-frequency divider circuit.

5. The LED drive control circuit of claim 1, wherein: The delay unit comprises a current source, a first capacitor, a switch tube and a Schmitt trigger; One end of the current source is connected to a power supply voltage, the other end is connected to the upper plate of the first capacitor, the lower plate of the first capacitor is grounded, the switch tube is connected in parallel across the first capacitor, and the control end receives the PWM signal; the input end of the Schmitt trigger is connected to the upper plate of the first capacitor, and the output end outputs the turn-off end signal.

6. The LED drive control circuit of claim 1, wherein: The adaptive delay module comprises a slope detection unit, a second capacitor, a comparator and an AND logic unit; The slope detection unit receives the negative voltage detection signal and the drain voltage of the power switch tube, detects the falling slope of the drain voltage of the power switch tube and converts it into a corresponding current signal when the negative voltage detection signal is valid; The upper plate of the second capacitor is connected to the output end of the slope detection unit, and the lower plate is grounded; The positive input end of the comparator is connected to the upper plate of the second capacitor, the negative input end receives a reference voltage, and the output end outputs a comparison result; One end of the AND logic unit is connected to the output end of the comparator, the other end receives the negative voltage detection signal, and the output end outputs a delay signal of the negative voltage detection signal.

7. A chip, characterized by The chip at least comprises the LED drive control circuit according to any one of claims 1-6.

8. An LED driving system, characterized by, The LED drive system at least comprises: a switching power supply circuit, an LED load, a ceramic capacitor and the LED drive control circuit according to any one of claims 1-6; The switching power supply circuit is connected to the LED load and provides driving current for the LED load based on the conduction and turn-off of the power switch tube; The LED drive control circuit is connected to the switching power supply circuit and provides a driving signal for the power switch tube in the switching power supply circuit; and the ceramic capacitor is connected to the LED drive control circuit.

9. A method for driving and controlling an LED, implemented based on the LED driving and controlling circuit according to any one of claims 1-6, characterized in that, The LED drive method at least comprises: In a normal working mode, an overcurrent detection signal of an LED output current and a negative voltage detection signal of a power switch tube driving signal are detected, the power switch tube is controlled to turn off when the overcurrent detection signal is valid, and the power switch tube is controlled to conduct when the negative voltage detection signal is valid. With the power supply voltage dropping, the over-current detection signal and the negative voltage detection signal cannot be detected, and an abnormal working mode is entered; at this time, when the on time of the power switch tube reaches a preset maximum on time, the power switch tube is controlled to be turned off, and when the off time of the power switch tube reaches a preset maximum off time, the power switch tube is controlled to be turned on; With the power supply voltage continuously dropping, the over-current detection signal and the negative voltage detection signal cannot be detected, and the on time and the off time of the power switch tube alternately reach the maximum on time and the maximum off time, and a de-whining mode is entered; at this time, when the on time of the power switch tube reaches a preset maximum on time, the power switch tube is controlled to be turned off, and when the power switch tube is turned off for a preset time, the power switch tube is controlled to be turned on; wherein the sum of the maximum on time and the preset time corresponds to a frequency beyond the range of human ear recognition.

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