SOI LDMOS device and manufacturing method thereof
By forming buried oxygen extension protrusions and charge tanks at the junction of the N-type drift region of the SOI LDMOS device and the buried oxygen layer, the problem of poor longitudinal voltage withstand voltage withstand voltage withstand voltage withstand voltage withstand voltage with lower longitudinal breakdown risk is solved.
Patent Information
- Application Number
- CN202510107934.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-04-29
AI Technical Summary
The longitudinal voltage withstand voltage of existing SOI LDMOS devices is poor, and longitudinal breakdown is prone to occur at the interface between the top silicon and the buried oxygen layer.
By forming several buried oxygen extension protrusions at the junction of the N-type drift region and the buried oxygen layer, charge tanks are formed between the adjacent two buried oxygen extension protrusions, increasing the accumulation of electrons and holes, and improving the potential barrier at the interface and the electric field strength of the buried oxygen layer.
It significantly improves the longitudinal withstand voltage of the device, reduces the occurrence of longitudinal breakdown, and enhances the overall performance of the device.
Smart Images
Figure CN119907270A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a SOI LDMOS device and a manufacturing method thereof. Background Art
[0002] The silicon on insulator (SOI) LDMOS device includes a P-type silicon substrate, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top in the vertical direction. The top silicon layer includes an N-type drift region and a P-type body region forming a PN junction reverse depletion layer in the lateral direction, and an inversion layer is formed at the interface between the top silicon and the buried oxide layer. The device drain is formed in the N-type drift region, and the source is formed in the P-type body region. As the device drain voltage continues to increase, the lateral depletion layer expands into the N-type drift region and connects to the inversion layer.
[0003] According to Gauss's theorem, the integral of the electric field lines passing through the interface of the top silicon and buried oxide layer along the interface is inversely proportional to the dielectric constant. Figure 7 The relationship between the vertical depth of the device and the electric field strength in the related art is shown, where t si is the thickness of the top silicon layer, t Box is the thickness of the buried oxide layer. When the top silicon reaches the critical breakdown electric field strength Esi (about 20V / um-40V / um) at the interface between the top silicon and the buried oxide layer, the electric field strength borne by the buried oxide layer is 3 times of Esi, about 60V / um-120V / um. It can be seen from this that the longitudinal withstand voltage of the device in the related art is poor, and the longitudinal breakdown is easy to occur at the interface between the top silicon and the buried oxide layer. Summary of the invention
[0004] The present application provides a SOI LDMOS device and a manufacturing method thereof, which can solve the problem of poor longitudinal withstand voltage of the device in the related art.
[0005] In order to solve the technical problem in the background technology, the first aspect of the present application provides a SOI LDMOS device, the SOI LDMOS device comprising: a first silicon layer, a buried oxide layer and a second silicon layer stacked in sequence from top to bottom;
[0006] A first conductivity type drift region and a second conductivity type body region are formed in the first silicon layer, and the first conductivity type drift region and the second conductivity type body region are laterally adjacent to each other in the first silicon layer;
[0007] The first conductive type drift region is vertically adjacent to the buried oxide layer, a plurality of buried oxide extension protrusions are formed at the junction of the first conductive type drift region and the buried oxide layer, the buried oxide extension protrusions extend from the junction into the first conductive type drift region, and a charge slot is formed between two adjacent buried oxide extension protrusions, and the charge slot is a portion of the first conductive type drift region;
[0008] One end of the first conductive type drift region away from the second conductive type body region forms a drain;
[0009] A source is formed in the second conductive type body region;
[0010] The gate is connected between the first conductive type drift region and the second conductive type body region.
[0011] Optionally, a height of the buried oxide extension protrusion extending from the junction into the first conductive type drift region is 75 nm to 100 nm.
[0012] Optionally, the width of the interval between two adjacent buried oxide extension protrusions is 200 nm to 300 nm.
[0013] In order to solve the technical problem in the background technology, the second aspect of the present application provides a method for manufacturing a SOI LDMOS device, which is used to manufacture the SOI LDMOS device described in the first aspect of the present application, and the method for manufacturing the SOI LDMOS device comprises the following steps:
[0014] Providing a first silicon layer, and forming a plurality of spaced grooves on an upper surface of a drift region of the first silicon layer by an etching process;
[0015] forming an oxide layer on the first silicon layer, wherein the oxide layer covering the first silicon layer fills the groove;
[0016] The upper surface of the oxide layer is planarized by a chemical mechanical polishing process to form a buried oxide layer, and the oxide layer located in the groove is a buried oxide extension protrusion;
[0017] Bonding a second silicon layer on the buried oxide layer to form an SOI structure including the first silicon layer, the buried oxide layer and the second silicon layer;
[0018] flipping the SOI structure so that the first silicon layer is located on top of the SOI structure;
[0019] A first conductive type drift region and a second conductive type body region are formed in the first silicon layer, wherein the first conductive type drift region and the second conductive type body region are laterally adjacent to each other in the first silicon layer, the buried oxide extension protrusion extends from the junction into the first conductive type drift region, and a first conductive type drift region portion is spaced between two adjacent buried oxide extension protrusions;
[0020] forming a drain at one end of the first conductive type drift region away from the second conductive type body region;
[0021] forming a source in the second conductivity type body region;
[0022] A gate is formed, wherein the gate is connected between the first conductive type drift region and the second conductive type body region.
[0023] Optionally, the step of providing a first silicon layer and forming a plurality of spaced grooves on an upper surface of a drift region of the first silicon layer by an etching process comprises:
[0024] Providing a silicon-based layer, the silicon-based layer comprising a bottom silicon layer and a first silicon layer bonded to each other, the first silicon layer being located on the bottom silicon layer;
[0025] A plurality of grooves spaced apart from each other are formed on the upper surface of the drift region of the first silicon layer by an etching process.
[0026] Optionally, the step of flipping the SOI structure so that the first silicon layer is located on the top of the SOI structure includes:
[0027] flipping the SOI structure;
[0028] peeling off the bottom silicon layer;
[0029] The first silicon layer is located on the top of the SOI structure.
[0030] Optionally, in the step of forming an oxide layer on the first silicon layer and filling the groove with the oxide layer covering the first silicon layer, the groove has a width of 200 nm to 300 nm and a height of 75 nm to 100 nm.
[0031] The technical solution of the present application includes at least the following advantages: as the drain voltage increases, the depletion region between the laterally adjacent N-type drift region and the P-type body region will expand toward the N-type drift region and connect to the inversion layer. In this embodiment, a plurality of buried oxide extension protrusions are formed at the junction of the N-type drift region and the buried oxide layer, and a charge slot is formed between two adjacent buried oxide extension protrusions. More electrons are easily accumulated in the charge slot, and more electrons are located in the N-type drift region in the charge slot, thereby attracting holes in the buried oxide layer to accumulate near the interface, so as to increase the potential barrier at the interface, increase the electric field strength of the buried oxide layer, and can also modulate the electric field of the drift region, which can greatly increase the withstand voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0033] Figure 1 A schematic cross-sectional structure diagram of a SOI LDMOS device provided in an embodiment of the present application is shown;
[0034] Figure 2 A flow chart of a method for manufacturing a SOI LDMOS device provided in an embodiment of the present application is shown;
[0035] Figure 3 A schematic diagram of a cross-sectional structure of the device after step S1 is completed is shown;
[0036] Figure 4 A schematic diagram of the cross-sectional structure of the device after step S3 is completed is shown;
[0037] Figure 5 A schematic diagram of the cross-sectional structure of the device after step S4 is completed is shown;
[0038] Figure 6 A schematic diagram of the cross-sectional structure of the device after step S5 is completed is shown;
[0039] Figure 7 The relationship between the vertical depth of a device and the electric field strength in the related art is shown. DETAILED DESCRIPTION
[0040] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0041] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0042] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0043] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0044] In the present application, the first conductivity type is opposite to the second conductivity type. In the following embodiments, the first conductivity type is N-type, and the second conductivity type is P-type for explanation. In other embodiments, the first conductivity type may also be P-type, and the first conductivity type is N-type.
[0045] Figure 1 FIG. 1 shows a schematic cross-sectional structure diagram of a SOI LDMOS device provided in an embodiment of the present application, from Figure 1 As can be seen in FIG. 1 , the SOI LDMOS device includes: a first silicon layer 110 , a buried oxide layer 120 , and a second silicon layer 130 stacked in sequence from top to bottom.
[0046] An N-type drift region 210 and a P-type body region 220 are formed in the first silicon layer 110, and the N-type drift region 210 and the P-type body region 220 are laterally adjacent to each other in the first silicon layer 110. A lateral PN junction formed between the laterally adjacent N-type drift region 210 and the P-type body region 220 is reverse-biased and depleted to form a depletion region.
[0047] The N-type drift region 210 is vertically adjacent to the buried oxide layer 120. A plurality of buried oxide extension protrusions 121 are formed at the interface between the N-type drift region 210 and the buried oxide layer 120. The buried oxide extension protrusions 121 extend from the interface into the N-type drift region 210. A charge slot 122 is formed between two adjacent buried oxide extension protrusions 121. The charge slot 122 is part of the N-type drift region 210. The N-type drift region 210 forms an inversion layer in a region close to the buried oxide layer 120.
[0048] A drain 400 is formed at one end of the N-type drift region 210 away from the P-type body region 220 .
[0049] A source 500 is formed in the P-type body region 220 .
[0050] The gate 300 is connected between the N-type drift region 210 and the P-type body region 220 .
[0051] As the drain voltage increases, the depletion region between the laterally adjacent N-type drift region and the P-type body region will expand toward the N-type drift region and connect to the inversion layer. In this embodiment, a plurality of buried oxide extension protrusions are formed at the junction of the N-type drift region and the buried oxide layer, and a charge slot is formed between two adjacent buried oxide extension protrusions. More electrons are easily accumulated in the charge slot, and more electrons are located in the N-type drift region in the charge slot, thereby attracting holes in the buried oxide layer to accumulate near the interface, so as to increase the potential barrier at the interface, increase the electric field strength of the buried oxide layer, and modulate the electric field in the drift region, thereby greatly improving the withstand voltage of the device.
[0052] Exemplarily, the buried oxide extension protrusion 121 extends from the boundary into the N-type drift region to a height of 75 nm to 100 nm.
[0053] The width of the interval between two adjacent buried oxide extension protrusions 121 is 200 nm to 300 nm.
[0054] Figure 2 FIG. 1 is a flowchart of a method for manufacturing a SOI LDMOS device according to an embodiment of the present application. Figure 2 As can be seen from the flowchart of the method for manufacturing the SOI LDMOS device, the process includes the following steps:
[0055] Step S1: providing a first silicon layer, and forming a plurality of spaced grooves on an upper surface of a drift region of the first silicon layer by an etching process.
[0056] The drift region of the first silicon layer is a region where a drift region is formed in a subsequent process.
[0057] The groove formed on the upper surface of the drift region of the first silicon layer by the etching process has a width of 200 nm to 300 nm and a height of 75 nm to 100 nm.
[0058] For example, in order to avoid the problem of broken pieces due to subsequent processes on the thinner first silicon layer, the first silicon layer and the bottom silicon layer can be bonded to form a silicon-based layer, and the first silicon layer is located on the bottom silicon layer. The bonded first silicon layer and the bottom silicon layer can increase the thickness of the silicon-based layer, thereby avoiding the problem of broken pieces on the silicon-based layer in subsequent processes.
[0059] Reference Figure 3 , which shows a schematic diagram of the cross-sectional structure of the device after step S1 is completed, from Figure 1 As can be seen in the figure, the first silicon layer 110 and the bottom silicon layer 101 are bonded to form the silicon-based layer 100. A plurality of grooves 111 are formed on the upper surface of the first silicon layer 110 at intervals.
[0060] Step S2: forming an oxide layer on the first silicon layer, wherein the oxide layer covering the first silicon layer fills the groove.
[0061] The oxide layer may be formed on the upper surface of the first silicon layer by a deposition process or a thermal oxidation process.
[0062] Step S3: planarizing the upper surface of the oxide layer through a chemical mechanical polishing process to form a buried oxide layer, and the oxide layer located in the groove is a buried oxide extension protrusion.
[0063] Reference Figure 4 , which shows a schematic diagram of the cross-sectional structure of the device after step S3 is completed, from Figure 4 As can be seen from the figure, the upper surface of the buried oxide layer 120 is flattened. Figure 3 The buried oxide layer 120 in the groove 111 is a buried oxide extension protrusion 121 .
[0064] Step S4: bonding a second silicon layer on the buried oxide layer to form an SOI structure including the first silicon layer, the buried oxide layer and the second silicon layer.
[0065] Reference Figure 5 , which shows a schematic diagram of the cross-sectional structure of the device after step S4 is completed, from Figure 5 It can be seen that in Figure 4 Based on the structure shown, a second silicon layer 130 is bonded to the buried oxide layer.
[0066] Step S5: turning over the SOI structure so that the first silicon layer is located on the top of the SOI structure.
[0067] For example, in order to avoid the problem of breakage caused by performing subsequent processes on a thinner first silicon layer in step S1, the first silicon layer and the bottom silicon layer can be bonded to form a silicon-based layer. When implementing step S5, after flipping the SOI structure, the bottom silicon layer 101 is peeled off so that the first silicon layer 110 is located on the top of the SOI structure.
[0068] Reference Figure 6 , which shows a schematic diagram of the cross-sectional structure of the device after step S5 is completed. Figure 6 It can be seen that the buried oxide extension protrusion 121 extends from the boundary between the buried oxide layer 120 and the first silicon layer 110 into the first silicon layer 110 , and a charge groove 122 is formed between two adjacent buried oxide extension protrusions 121 .
[0069] Step S6: forming an N-type drift region and a P-type body region in the first silicon layer, wherein the N-type drift region and the P-body region are laterally adjacent to each other in the first silicon layer, and the buried oxide extension protrusion extends from the junction into the N-type drift region, and an N-type drift region portion is spaced between two adjacent buried oxide extension protrusions.
[0070] Step S7: forming a drain at one end of the N-type drift region away from the P-type body region.
[0071] Step S8: forming a source in the P-type body region.
[0072] Step S9: forming a gate, wherein the gate is connected between the N-type drift region and the P-type body region.
[0073] After step S9 is completed, Figure 1 The SOI LDMOS device shown.
[0074] As the drain voltage increases, the depletion region between the laterally adjacent N-type drift region and the P-type body region will expand toward the N-type drift region and connect to the inversion layer. In this embodiment, a plurality of buried oxide extension protrusions are formed at the junction of the N-type drift region and the buried oxide layer, and a charge slot is formed between two adjacent buried oxide extension protrusions. More electrons are easily accumulated in the charge slot, and more electrons are located in the N-type drift region in the charge slot, thereby attracting holes in the buried oxide layer to accumulate near the interface, so as to increase the potential barrier at the interface, increase the electric field strength of the buried oxide layer, and modulate the electric field in the drift region, thereby greatly improving the withstand voltage of the device.
[0075] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A SOI LDMOS device, characterized in that: The SOI LDMOS device comprises: a first silicon layer, a buried oxide layer and a second silicon layer stacked in sequence from top to bottom; A first conductivity type drift region and a second conductivity type body region are formed in the first silicon layer, and the first conductivity type drift region and the second conductivity type body region are laterally adjacent to each other in the first silicon layer; The first conductive type drift region is vertically adjacent to the buried oxide layer, a plurality of buried oxide extension protrusions are formed at the junction of the first conductive type drift region and the buried oxide layer, the buried oxide extension protrusions extend from the junction into the first conductive type drift region, and a charge slot is formed between two adjacent buried oxide extension protrusions, and the charge slot is a portion of the first conductive type drift region; One end of the first conductive type drift region away from the second conductive type body region forms a drain; A source is formed in the second conductive type body region; The gate is connected between the first conductive type drift region and the second conductive type body region.
2. The SOI LDMOS device according to claim 1, wherein: The buried oxide extension protrusion extends from the junction into the first conductive type drift region to a height of 75 nm to 100 nm.
3. The SOI LDMOS device according to claim 1, wherein: The width of the interval between two adjacent buried oxide extension protrusions is 200nm to 300nm.
4. A method for manufacturing a SOI LDMOS device, characterized in that: The method for manufacturing the SOI LDMOS device is used to manufacture the SOI LDMOS device according to any one of claims 1 to 3, and the method for manufacturing the SOI LDMOS device comprises the following steps: Providing a first silicon layer, and forming a plurality of spaced grooves on an upper surface of a drift region of the first silicon layer by an etching process; forming an oxide layer on the first silicon layer, wherein the oxide layer covering the first silicon layer fills the groove; The upper surface of the oxide layer is planarized by a chemical mechanical polishing process to form a buried oxide layer, and the oxide layer located in the groove is a buried oxide extension protrusion; Bonding a second silicon layer on the buried oxide layer to form an SOI structure including the first silicon layer, the buried oxide layer and the second silicon layer; flipping the SOI structure so that the first silicon layer is located on top of the SOI structure; A first conductive type drift region and a second conductive type body region are formed in the first silicon layer, wherein the first conductive type drift region and the second conductive type body region are laterally adjacent to each other in the first silicon layer, the buried oxide extension protrusion extends from the junction into the first conductive type drift region, and a first conductive type drift region portion is spaced between two adjacent buried oxide extension protrusions; forming a drain at one end of the first conductive type drift region away from the second conductive type body region; forming a source in the second conductivity type body region; A gate is formed, wherein the gate is connected between the first conductive type drift region and the second conductive type body region.
5. The method for manufacturing a SOI LDMOS device according to claim 4, characterized in that: The step of providing a first silicon layer and forming a plurality of spaced grooves on the upper surface of the drift region of the first silicon layer by an etching process comprises: Providing a silicon-based layer, the silicon-based layer comprising a bottom silicon layer and a first silicon layer bonded to each other, the first silicon layer being located on the bottom silicon layer; A plurality of grooves spaced apart from each other are formed on the upper surface of the drift region of the first silicon layer by an etching process.
6. The method for manufacturing a SOI LDMOS device according to claim 5, wherein: The step of flipping the SOI structure so that the first silicon layer is located on the top of the SOI structure comprises: flipping the SOI structure; peeling off the bottom silicon layer; The first silicon layer is located on the top of the SOI structure.
7. The method for manufacturing a SOI LDMOS device according to claim 5, wherein: In the step of forming an oxide layer on the first silicon layer and filling the groove with the oxide layer covering the first silicon layer, the groove has a width of 200nm to 300nm and a height of 75nm to 100nm.