Dual-gate MOS structure and preparation method thereof

Abstract

The present application relates to the field of semiconductor manufacturing process technology, and provides a dual-gate MOS structure and a manufacturing method thereof, the manufacturing method comprising: providing a substrate; the substrate comprising a substrate precursor and a shallow trench isolation structure; wherein the substrate precursor comprises an active area defined by the shallow trench isolation structure; a recessed hole is formed on the surface of the active area; a first gate structure precursor is formed in the recessed hole, and a second gate structure is formed on the surface of the active area between the first gate structure precursor and the shallow trench isolation structure; the first gate structure precursor and the substrate precursor are cut using a plane perpendicular to the arrangement direction of the active area as a cutting plane to obtain the substrate, first gate structure, and second gate structure of the dual-gate MOS structure; wherein the contact surface between the first gate structure and the substrate is non-planar. In this way, the short channel effect problem can be improved without occupying additional wafer area.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing process technology, and in particular to a dual-gate MOS structure and a manufacturing method thereof. Background Art

[0002] With the continuous advancement of semiconductor manufacturing technology, the size of transistors continues to shrink, allowing more transistors to be accommodated per unit area, thereby greatly improving the integration and performance of chips, and promoting the improvement of computing power and processing speed.

[0003] However, as transistor size continues to shrink, the resulting technical challenges become increasingly complex. This is particularly true in MOSFETs (metal-oxide-semiconductor field-effect transistors, MOS), where the short channel effect (SCE) is becoming increasingly prominent. SCE refers to the weakening of the gate's influence on the channel when the transistor's channel length is shortened to a certain extent, leading to unstable switching characteristics and increased leakage current. This not only affects the MOSFET's operating efficiency but can also reduce its reliability in high-density integrated circuits. As MOSFET size continues to decrease, the impact of SCE on performance will become increasingly significant. Therefore, effectively mitigating or eliminating SCE is a pressing issue in related technologies. Summary of the Invention

[0004] In view of this, multiple embodiments of the present application are dedicated to providing a dual-gate MOS structure and a preparation method thereof, which can improve the short channel effect problem existing in the related art to a certain extent.

[0005] One embodiment of the present application provides a dual-gate MOS structure, comprising: a substrate, a surface of the substrate having a recessed portion, and the recessed portion also having a recess formed on a side surface adjacent to the substrate surface; a first gate structure, the first gate structure being embedded in the recessed portion; and a second gate structure, the second gate structure being located on the surface of the substrate between the first gate structure and a shallow trench isolation structure; wherein a contact surface formed between the first gate structure and the sidewall of the recessed portion is non-planar.

[0006] Optionally, the substrate and the first gate structure of the dual-gate MOS structure are obtained by cutting the first gate structure precursor and the substrate precursor; wherein the substrate precursor has an active area defined by a shallow trench isolation structure; a recessed hole is formed on the surface of the active area, and the gate structure precursor is filled in the recessed hole; wherein the recessed portion is formed by part of the side wall and part of the bottom of the recessed hole after being cut.

[0007] Optionally, a contact contour line is formed at the interface between the contact surface and the substrate surface; the contact contour line has a bent shape, or the contact contour line is in an arc shape.

[0008] Optionally, source and drain regions are further formed in the substrate and are located on both sides of the first gate structure and the second gate structure; wherein the first gate structure and the second gate structure correspond to different channels respectively; wherein the extension direction of the channel corresponding to the first gate structure is consistent with the extension direction of the contact surface between the source and drain regions, so that the length of the channel corresponding to the first gate structure is greater than the spacing between the source and drain regions.

[0009] Optionally, the first gate structure and the second gate structure respectively form a first MOS structure and a second MOS structure with the substrate; wherein the first MOS structure and the second MOS structure respectively have different threshold voltages.

[0010] Optionally, contact holes are respectively provided on the source and drain regions, the first gate structure and the second gate structure; wherein the contact holes are filled with metal material, and a connection layer covered by the metal material is formed on the sidewalls and bottom of the contact holes; wherein a contact connection layer is also provided between the contact holes on the source and drain regions and the source and drain regions.

[0011] Optionally, an extension direction of the channel is parallel to the surface of the substrate.

[0012] Another embodiment of the present application provides a method for preparing a dual-gate MOS structure, which is used to prepare the dual-gate MOS structure as described above; the preparation method includes: providing a substrate; the substrate includes a substrate precursor and a shallow trench isolation structure; wherein the substrate precursor includes an active area defined by the shallow trench isolation structure; a recessed hole is formed on the surface of the active area; a first gate structure precursor is filled in the recessed hole, and a second gate structure is formed on the surface of the active area, located between the first gate structure precursor and the shallow trench isolation structure; using a plane perpendicular to the arrangement direction of the active area as a cutting plane, the first gate structure precursor and the substrate precursor are cut to obtain the substrate, first gate structure and second gate structure of the dual-gate MOS structure; wherein part of the sidewall and part of the bottom of the recessed hole form the recessed portion.

[0013] Optionally, in the step of cutting the first gate structure precursor and the substrate precursor using a plane perpendicular to the arrangement direction of the active regions as a cutting plane, the cutting plane passes through the center of the first gate structure precursor.

[0014] Optionally, the active area includes an outer area surrounding the recessed hole; the steps of filling the recessed hole to form a first gate structure precursor and forming a second gate structure located between the first gate structure precursor and the shallow trench isolation structure on the surface of the active area include: setting a dielectric layer in the active area; wherein the dielectric layer located in the outer area has a different thickness and / or material from the dielectric layer located in the recessed hole; filling the recessed hole with the dielectric layer formed therein with a first gate material to form a first gate structure precursor, and setting a second gate material on the dielectric layer in the outer area to form a second gate structure.

[0015] Optionally, the preparation method of the dual-gate MOS structure also includes: forming source and drain regions on both sides of the first gate structure and the second gate structure in the substrate; wherein the first gate structure and the second gate structure correspond to different channels respectively; the extension direction of the channel corresponding to the first gate structure is consistent with the extension direction of the contact surface between the source and drain regions, so that the length of the channel corresponding to the first gate structure is greater than the spacing between the source and drain regions; forming a contact connection layer on the surface of the source and drain region, and making contact holes on the surface of the contact connection layer, the first gate structure and the second gate structure respectively; forming a connection layer on the sidewall and bottom of the contact hole, and filling it with metal material; wherein the connection layer is covered by the metal material.

[0016] The unexpected effect of the multiple embodiments provided in this application is that, by forming a recessed hole on the surface of the active area of the substrate precursor, and forming a first gate structure and a second gate structure within the recessed hole and on the surface of the active area between the recessed hole and the shallow trench isolation structure, respectively, a dual-gate MOS structure consisting of the second gate structure, the first sub-gate structure, and the substrate can be obtained after cutting. In the dual-gate MOS structure thus prepared, while the electric field control capability is improved by the second gate structure, the contact surface between the first gate structure and the substrate is part of the sidewall of the recessed hole, thereby increasing the length of the channel corresponding to the first gate structure without occupying additional wafer area, thereby improving the short channel effect and enhancing the performance of the dual-gate MOS structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of a method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0018] Figures 2 to 4 A schematic diagram of a substrate is provided in the method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0019] Figure 5 A schematic diagram of forming a dielectric layer in the method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0020] Figure 6 This is a schematic diagram of forming a preliminary body of a first gate structure in the method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0021] Figure 7 This is a schematic diagram of forming a second gate structure in the method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0022] Figure 8 This is a schematic diagram of forming a dual-gate MOS structure in the preparation method of the dual-gate MOS structure provided in an embodiment of the present application.

[0023] Figure 9 A schematic cross-sectional view of a substrate in a method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0024] Figure 10 This is a three-dimensional reference schematic diagram of a substrate in the method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0025] Figure 11 A cross-sectional view of a dual-gate MOS structure in a method for preparing the dual-gate MOS structure provided in an embodiment of the present application.

[0026] Figure 12 This is a three-dimensional reference schematic diagram of a dual-gate MOS structure in the method for preparing the dual-gate MOS structure provided in an embodiment of the present application.

[0027] Figure 13 Schematic diagram of forming source and drain regions in the method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0028] Figure 14 This is a schematic diagram of fabricating a contact layer and contact holes in a method for fabricating a dual-gate MOS structure according to an embodiment of the present application.

[0029] Description of reference numerals:

[0030] 10. Base; 11. Shallow trench isolation structure; 12. Substrate precursor; 121. Substrate; 13. Active area; 14. Recessed hole; 141. Part of the sidewall; 142. Part of the bottom; 15. Area outside the hole; 16. Dielectric layer; 161. Dielectric layer in the recessed hole; 162. Dielectric layer in the area outside the hole; 17. First gate material; 18. First gate structure precursor; 181. First gate structure; 19. Second gate material; 20. Dual-gate MOS structure; 21. Second gate structure; 22. Contact outline; 23. Recessed portion; 24. Source and drain region; 122. Deep well region; 123. Well region; 25. Contact layer; 26. Metal material; 27. Connecting layer; aa. Active area arrangement direction; bb. Extension direction of the channel corresponding to the first gate structure. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0032] In this application, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show details of the local features.

[0033] Unless otherwise indicated, all technical and scientific terms used in this application have the same meaning as those generally understood by those skilled in the art in the technical field of this application. The terms used in this application are only for the purpose of describing the specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms "a", "above" and "the" used in the embodiments of this application are also intended to include plural forms, unless the context clearly indicates other meanings.

[0034] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0035] In the description of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of a simplified description of this application, and do not indicate that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation to this application.

[0036] In the description of this application, unless otherwise expressly defined, the terms "installed," "connected," "connect," "fixed," and "disposed" should be understood broadly. For example, "connection" can mean fixed, removable, or integrated; it can mean mechanical or electrical; it can mean direct or indirect connection through an intermediary; it can also mean internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0037] To achieve higher integration and improved performance within limited chip area, the continuous shrinking of semiconductor manufacturing process nodes has become a trend. This trend has led to increasingly smaller transistor sizes, significantly increasing the number of transistors that can be accommodated per unit area, significantly improving chip computing power and operating speed. However, the technical challenges brought about by the shrinking transistor size have also become increasingly severe, particularly the short channel effect. This problem weakens the gate's ability to influence the channel, increasing leakage current, and severely affecting and limiting transistor performance and reliability.

[0038] To effectively mitigate the short-channel effect, new dual-gate or multi-gate MOSFET structures, such as FinFET and GAA (Gate-All-Around), have emerged. Compared to traditional MOSFETs, dual-gate or multi-gate MOSFET structures can effectively reduce leakage current by enhancing the gate's influence on the channel's electric field, while maintaining good switching characteristics at a smaller size, thereby mitigating the negative impact of the short-channel effect.

[0039] However, although these new dual-gate or multi-gate MOSFET structures can effectively improve transistor performance and mitigate the impact of short channel effects to a certain extent, they are also accompanied by more complex manufacturing processes. Taking FinFET as an example, its fin-shaped structure requires the precise engraving of multiple vertical fins on the wafer and the control of their spacing and height. This not only requires more photolithography and etching process steps, but also requires additional wafer area. The wafer utilization rate under the same size conditions is not high, which increases the manufacturing cost and difficulty, leading to higher requirements for semiconductor manufacturing processes.

[0040] Therefore, it is necessary to provide a method for preparing a dual-gate MOS structure, which can prepare a dual-gate MOS structure that can improve the short channel effect while occupying the same wafer area.

[0041] See also Figures 1-14 One embodiment of the present application provides a method for preparing a dual-gate MOS structure. The dual-gate MOS structure may be a basic structure consisting of a substrate and a gate formed on the substrate, or it may be a semiconductor structure formed after a back-end process such as an ion implantation process, a contact hole process, etc. The method for preparing the dual-gate MOS structure may include the following steps.

[0042] S110: providing a substrate.

[0043] In this embodiment, if Figure 4As shown in FIG, a substrate 10 includes a substrate body 12 and a shallow trench isolation structure 11. The substrate body 12 includes an active area 13 defined by the shallow trench isolation structure 11. A recessed hole 14 is formed on the surface of the active area 13. The active area 13 also includes an outer region 15 surrounding the recessed hole 14.

[0044] In this embodiment, the substrate precursor 12 serves as the foundation of the dual-gate MOS structure, providing not only mechanical support but also, through ion doping, affecting the electrical properties of the dual-gate MOS structure, such as threshold voltage and carrier mobility. Specifically, the substrate precursor 12 can be made of silicon (Si) or, as required, other semiconductor materials such as silicon carbide (SiC) or gallium nitride (GaN).

[0045] In this embodiment, a shallow trench isolation (STI) structure 11 is used to form effective electrical isolation between different active regions 13 by etching a shallow trench in a substrate bulk 12 and filling it with an insulating material, such as silicon dioxide SiO2, thereby reducing parasitic capacitance and leakage current and improving the performance and reliability of the dual-gate MOS structure.

[0046] In this embodiment, reference Figure 2 and Figure 3 , a shallow trench isolation structure 11 can be first made on the surface of the wafer, the position and size of the active area can be defined by the shallow trench isolation structure 11, and then the well region can be formed by ion doping. Depending on the type of MOS structure prepared, the ion doping type of the well region is different. For example, for an NMOS structure, the ion doping type of the well region is P-type. For a PMOS structure, the ion doping type of the well region is N-type. In some embodiments, before forming the well region, a deep well region can also be formed by doping ions of the opposite ion doping type to the well region. The well region can be located on the deep well region. For example, for an NMOS structure, the ion doping type of the deep well region is N-type. For a PMOS structure, the ion doping type of the deep well region is P-type.

[0047] Then, if Figure 3 and Figure 4 As shown in , a recessed lower hole 14 can be etched on the surface of the active area 13 through photolithography and etching processes to obtain the substrate 10. Specifically, the size of the lower hole 14 can be flexibly set according to actual needs, and this application does not impose specific restrictions on this. In this embodiment, an active area 13 (Active Area) can be defined on the substrate precursor 12 through the shallow trench isolation structure 11. The area of the substrate precursor 12 between adjacent shallow trench isolation structures 11 is the active area 13. The active area 13 can be used as a specific area for manufacturing transistors and other active devices.

[0048] In this embodiment, the lower recessed hole 14 may be formed with a hole outline on the surface of the active area 13. The hole outline of the lower recessed hole 14 may serve as a boundary to divide the active area 13 into an inner hole area and an outer hole area 15 surrounding the lower recessed hole 14. Specifically, the shape of the hole outline may be elliptical, polygonal, etc. In some embodiments, the depth of the lower recessed hole 14 relative to the surface of the active area 13 may be less than the thickness of the well region, that is, the lower recessed hole 14 does not penetrate the well region. In some embodiments, the hole outline of the lower recessed hole 14 is circular, and the diameter of the hole outline of the lower recessed hole 14 may be three times the gate width in a conventional MOS structure.

[0049] S120: Filling the recessed hole to form a first gate structure precursor, and forming a second gate structure on the surface of the active area between the first gate structure precursor and the shallow trench isolation structure.

[0050] In this embodiment, the steps of filling the lower recessed hole to form a preliminary body of a first gate structure, and forming a second gate structure located between the lower recessed hole and the shallow trench isolation structure on the surface of the active area may include: providing a dielectric layer in the active area; wherein the dielectric layer located in the area outside the hole has a different thickness and / or material from the dielectric layer located in the lower recessed hole; filling the lower recessed hole with the dielectric layer formed therein with a first gate material to form a preliminary body of the first gate structure, and providing a second gate material on the dielectric layer in the area outside the hole to form a second gate structure.

[0051] In some embodiments, reference Figure 4 and Figure 5 , a furnace tube process can be used to grow oxide on the surface of the active area 13 to form a dielectric layer 16. The areas where oxide growth is not required are blocked with a hard mask. The dielectric layer 16 covers the surface of the area outside the hole 15 and the sidewalls and bottom of the lower recessed hole 14. The duration of the furnace tube process can be controlled to have different thicknesses between the dielectric layer 162 in the area outside the hole and the dielectric layer 161 located within the lower recessed hole. Of course, in some embodiments, the thickness of the dielectric layer 16 formed on the surface of the active area 13 can also be uniform, that is, the thickness of the dielectric layer 162 in the area outside the hole and the dielectric layer 161 located within the lower recessed hole can also be the same. Specifically, the thickness of the dielectric layer 16 can be flexibly set according to actual needs by controlling the duration of the furnace tube process. For example, if a dual-gate MOS structure for a high-voltage device needs to be prepared, the furnace tube process can be applied for a longer time to make the dielectric layer 16 thicker.

[0052] In some embodiments, the dielectric layer 162 located in the area outside the hole may not completely cover the surface of the area outside the hole 15, but only cover part of the surface of the area outside the hole 15, such as covering the surface of the area outside the hole 15 between the recessed hole 14 and the shallow trench isolation structure 11, or only covering the surface of the area outside the hole 15 where the second gate structure is subsequently set.

[0053] In some embodiments, as Figure 6 As shown in , by filling the first gate material 17, such as polysilicon or metal, into the lower recess 14 formed with the dielectric layer and polishing it by CMP, a first gate structure precursor 18 consisting of the first gate material 17 and the dielectric layer 161 located in the lower recess on the side wall of the lower recess, is formed. The dielectric layer 161 located in the lower recess on the side wall of the lower recess serves as the gate dielectric layer of the first gate structure precursor 18. Specifically, in the first gate structure precursor 18, the height of the first gate material 17 can be level with the substrate surface or higher than the substrate surface. Then, as shown in FIG. Figure 7 As shown in , a second gate material 19 can be formed between the first gate structure precursor 18 and the shallow trench isolation structure 11 by depositing a certain thickness (e.g., 800Å) of polysilicon on the dielectric layer 162 in the region outside the hole and using photolithography and etching processes. This forms a second gate structure 21 composed of the second gate material 19 and the dielectric layer 162 in the region outside the hole. The dielectric layer 162 in the region outside the hole covered by the second gate material 19 serves as the gate dielectric layer of the second gate structure. In some embodiments, the second gate material 19 can be the same material as the first gate material 17, or a different material. For example, in addition to polysilicon, the second gate material 19 can also be other materials such as metal.

[0054] In this embodiment, the size of the second gate material 19 along the active area arrangement direction may be consistent with the spacing between the first gate structure precursor 18 and the shallow trench isolation structure 11, or may be smaller than the spacing between the first gate structure precursor 18 and the shallow trench isolation structure 11. Specifically, for example, along the active area arrangement direction, the second gate material 19 may have a spacing with both the first gate structure precursor 18 and the shallow trench isolation structure 11, or may have a spacing with only one of them, for example Figure 7 As shown in the figure, the second gate material 19 is only spaced apart from the first gate structure 18 , and the spacing can be flexibly set according to specific requirements.

[0055] S130: Using a plane perpendicular to the arrangement direction of the shallow trench isolation structure as a cutting plane, the first gate structure precursor and the substrate precursor are cut to obtain a dual-gate MOS structure consisting of the first gate structure, the second gate structure and the substrate; wherein the substrate includes a recessed portion formed by part of the sidewalls and part of the bottom of the recessed hole; the first gate structure contacts the sidewalls of the recessed portion, and the contact surface is non-planar.

[0056] In this embodiment, reference Figure 7 and Figure 8, a cutting process is performed perpendicular to the arrangement direction aa of the shallow trench isolation structure 11, wherein the cutting plane is a plane perpendicular to the arrangement direction aa of the active area and passes through the substrate precursor 12 and the first gate structure precursor 18 at the same time, so as to simultaneously cut the gate structure and the substrate precursor 12. Specifically, for example, for the first gate material 17 of polysilicon, a poly-cut process can be used to define the shape of a poly-cut at the center of the first gate structure precursor 18, and then cut to obtain two independent dual-gate MOS structures 20. Each dual-gate MOS structure 20 is respectively composed of the cut second gate structure 21, the first gate structure 181 and the substrate 121.

[0057] In this embodiment, the cutting plane for cutting the first gate structure precursor 18 and the substrate precursor 12 can pass through the center of the first gate structure precursor 18 to obtain a dual-gate MOS structure 20 with a first gate structure 181 of the same size, or can pass through other positions of the gate structure to obtain a dual-gate MOS structure 20 with a first gate structure 181 of different sizes. The specific cutting plane can be flexibly adjusted according to actual needs.

[0058] In this embodiment, please refer to Figure 4 as well as Figures 8 to 12 , Figure 9 and Figure 10 For the Figure 8 The cross-sectional diagram at the dotted line position, where Figure 9 is a schematic diagram of the substrate 121, Figure 11 FIG. 1 is a schematic diagram of a dual-gate MOS structure 20 composed of a second gate structure 21 , a first gate structure 181 , and a substrate 121 . In some embodiments, a well region 123 and a deep well region 122 may be formed on the substrate 121 . Figure 10 and Figure 12 They are three-dimensional reference diagrams of the substrate 121 and the dual-gate MOS structure 20 respectively.

[0059] In this embodiment, since the first gate structure precursor 18 is cut while the lower recessed hole 14 filled with the first gate structure precursor 18 is also cut, in the cut substrate 121, as shown in FIG. Figure 9 As shown, part of the sidewall 141 and part of the bottom 142 of the recessed hole 14 can form a recessed portion 23. In the double-gate MOS structure 20 obtained by cutting, Figure 4 as well as Figures 8 to 10 The first gate structure 181 is embedded in the recess 23 of the substrate 121. The contact surface between the first gate structure 181 and the recess 23 is the sidewall of the recess 23, that is, part of the sidewall 141 of the recess hole 14. It can be understood that this contact surface is non-planar.

[0060] In this embodiment, an unexpected effect is that by forming a recessed hole 14 on the surface of the active area 13 of the substrate precursor 12, and forming a first gate structure precursor 18 and a second gate structure 21 within the recessed hole 14 and on the surface of the active area 13 between the recessed hole 14 and the shallow trench isolation structure 11, respectively, a dual-gate MOS structure 20 consisting of the second gate structure 21, the first gate structure 181, and the substrate 121 can be obtained after dicing. In the dual-gate MOS structure 20 thus prepared, while the second gate structure 21 improves the electric field control capability, because the contact surface between the first gate structure 181 and the substrate 121 is a portion of the sidewall 141 of the recessed hole 14, the length of the channel corresponding to the first gate structure 181 is increased without occupying additional wafer area, thereby improving the short channel effect and enhancing the performance of the dual-gate MOS structure 20.

[0061] Furthermore, compared to some dual-gate or multi-gate structures in related arts, the dual-gate MOS structure 20 provided in this embodiment has a higher utilization rate of the active area, given a pre-defined active area size. Furthermore, the manufacturing process is less complex, and the process flexibility is greater, given the same wafer area utilization rate.

[0062] In addition, the dual-gate process used in this embodiment can not only reduce the leakage current Ioff of the subsequently manufactured product, but also achieve efficient integration of circuits with different requirements, thereby improving product performance and the flexibility of process integration.

[0063] In some embodiments, the dielectric layer in the region outside the hole and the dielectric layer in the recessed hole are made of different materials; and / or the first gate material and the second gate material are made of different materials.

[0064] In some embodiments, as Figure 6 and Figure 7 As shown in , since the dielectric layer 162 in the outer region of the hole and the dielectric layer 161 in the lower recessed hole are respectively used as gate dielectric layers corresponding to different gates in the dual-gate MOS structure after being cut, the two are differentiated by different material designs, which can further improve the electric field control capability of the dual-gate MOS structure, reduce leakage current, and enhance the adjustability and flexibility of the threshold voltage. Specifically, for example, the dielectric layer 161 in the lower recessed hole can be silicon dioxide, and the dielectric layer 162 in the outer region of the hole can be silicon nitride or a high-k material such as hafnium oxide or zirconium oxide. In some embodiments, based on similar principles, the use of first gate materials 17 and second gate materials 19 of different materials can also improve the performance and flexibility of the dual-gate MOS structure.

[0065] In some embodiments, a contact contour line is formed at the interface between the contact surface and the surface of the sub-substrate, and the contact contour line has a bend.

[0066] In some embodiments, as Figure 8 As shown in FIG, in the dual-gate MOS structure 20 obtained, the contact surface between the first gate structure 181 and the substrate 121 can form a contact contour line 22 at the interface with the substrate 121. Figure 9 Because the contact surface is a portion of the sidewall 141 of the recessed hole formed during fabrication, the shape of the contact contour line 22 can be determined by the shape of the recessed hole's hole profile. Specifically, the contact contour line 22 can have a zigzag morphology, such as a single bend or multiple bends. This allows the channel corresponding to the first gate structure 181 to extend along the contact contour line 22, thereby increasing the channel length while maintaining the same dimensions.

[0067] In some embodiments, the contact contour line 22 may be in the shape of an arc.

[0068] In some embodiments, when the hole contour of the recessed hole is circular, it can be understood that in the dual-gate MOS structure 20 obtained after cutting, the contact contour line 22 of the contact surface between the first gate structure 181 and the substrate 121 can be arc-shaped.

[0069] In some embodiments, when the contact contour line 22 is in an arc shape, the channel corresponding to the first gate structure 181 can be smoother. Compared with shapes such as a broken line, this can reduce the occurrence of tip discharge due to an unsmooth channel.

[0070] In some embodiments, the preparation method of the dual-gate MOS structure may further include: forming source and drain regions located on both sides of the first gate structure and the second gate structure in the sub-substrate; wherein the first gate structure and the second gate structure correspond to different channels respectively; the extension direction of the channel corresponding to the first gate structure is consistent with the extension direction of the contact surface between the source and drain regions, so that the length of the channel corresponding to the first gate structure is greater than the spacing between the source and drain regions.

[0071] In some embodiments, reference Figure 13 ,against Figure 8 The dual-gate MOS structure 20 shown in the figure can also form source and drain regions 24 in the substrate 121 on both sides of the first gate structure 181 and the second gate structure 21 through an ion implantation process. In some embodiments, lightly doped regions (LDD) and pocket regions (Pocket) can also be formed. In this way, the length of the channel corresponding to the first gate structure 181 can be greater than the spacing between the source and drain regions 24, that is, the channel length under the same size conditions is increased, thereby improving the short channel effect. Figure 4Taking the preparation process of a lower recessed hole 14 with a circular profile and a cut plane passing through the center of the first gate structure precursor 18 as an example, the diameter of the profile can be 40 nm. Thus, the channel length of the first gate structure 181 can be 62.8 nm, a 57% increase in channel length. In some embodiments, the extension direction bb of the channel corresponding to the first gate structure 181 can be parallel to the surface of the substrate 121.

[0072] In some embodiments, the channel corresponding to the second gate structure 21 is different from the channel corresponding to the first gate structure 181. The channel direction corresponding to the second gate structure 21 can be the same as the arrangement direction of the source and drain regions 24. In this way, in the dual-gate MOS structure 20, since the channels corresponding to each gate structure are different, the first gate structure 181 and the second gate structure 21 can respectively serve as components of two independent MOSs with different threshold voltages. Specifically, the first gate structure 181 and the second gate structure 21 respectively constitute the first MOS structure and the second MOS structure with the substrate 121, and the first MOS structure and the second MOS structure have different threshold voltages. Among them, the source and drain regions 24 are common areas of the first MOS structure and the second MOS structure. In this way, the performance of the dual-gate MOS structure 20 and the flexibility of integration for different needs can be further improved.

[0073] In some embodiments, the preparation method of the dual-gate MOS structure may further include: forming a contact bonding layer on the surface of the source and drain regions, and making contact holes on the surfaces of the contact bonding layer, the first gate structure, and the second gate structure respectively; forming a connecting layer on the sidewalls and bottom of the contact hole, and filling it with metal material; wherein the connecting layer is covered with the metal material.

[0074] In some embodiments, after forming the source and drain regions 24, as shown in FIG. Figure 14 As shown, a contact layer 25 may be further formed on the surface of the source / drain region 24 to serve as a contact between the metal material 26 and the source / drain region 24. Specifically, the contact layer may be made of metal silicide, such as silicon nickel.

[0075] Then, contact holes are formed on the surface of the contact layer 25 corresponding to the source and drain regions 24, as well as on the surfaces of the first gate structure 181 and the second gate structure 21, and the contact holes are filled with a metal material 26, such as tungsten. In some embodiments, a connection layer 27 may be provided on the sidewalls and bottom of the contact hole to encapsulate the metal material. Specifically, the connection layer 27 may be located between the contact hole and the metal material 26. The connection layer 27 may be composed of titanium and titanium nitride. The connection layer 27 can prevent the diffusion of the metal material 26 and can increase adhesion.

[0076] An embodiment of the present application provides a dual-gate MOS structure, which is manufactured using the method for manufacturing the dual-gate MOS structure described in any of the aforementioned embodiments.

[0077] Specifically, in this embodiment, Figures 8 to 12 As shown, the dual-gate MOS structure 20 may specifically include: a substrate 121 , a first gate structure 181 and a second gate structure 21 .

[0078] In this embodiment, a concave lower portion 23 is formed on the surface of the substrate 121, and the lower portion 23 also has a depression on the side surface adjacent to the surface of the substrate 121. It should be noted that the direction of the depression of the lower portion 23 on the surface of the substrate 121 is different from that of the depression formed on the side surface. The depression formed by the lower portion 23 on the surface of the substrate 121 extends from the surface of the substrate 121 to the bottom of the lower portion 23 (partial bottom 142 of the lower recessed hole 14), while the depression formed by the lower portion 23 on the side surface adjacent to the surface of the substrate 121 extends from that side surface along the side wall of the lower portion 23 (partial side wall 141 of the lower recessed hole 14).

[0079] In this embodiment, the shape of the first gate structure 181 can match the concave portion 23 so as to be embedded in the concave portion 23. The contact surface formed by the first gate structure 181 and the sidewall of the concave portion 23 is non-planar.

[0080] In this embodiment, the second gate structure 21 may be disposed on the substrate surface between the first gate structure 181 and the shallow trench isolation structure 11 .

[0081] In some embodiments, the substrate and the first gate structure of the dual-gate MOS structure are obtained by cutting the first gate structure precursor and the substrate precursor; wherein the substrate precursor has an active area defined by a shallow trench isolation structure; a recessed hole is formed on the surface of the active area, and the gate structure precursor is filled in the recessed hole; wherein the recessed portion is formed by part of the sidewall and part of the bottom of the recessed hole after being cut.

[0082] In some embodiments, a contact contour line is formed at the interface between the contact surface and the substrate surface; the contact contour line has a bent shape, or the contact contour line is in an arc shape.

[0083] In some embodiments, source and drain regions are further formed in the substrate and are located on both sides of the first gate structure and the second gate structure; wherein the first gate structure and the second gate structure correspond to different channels respectively; wherein the extension direction of the channel corresponding to the first gate structure is consistent with the extension direction of the contact surface between the source and drain regions, so that the length of the channel corresponding to the first gate structure is greater than the spacing between the source and drain regions.

[0084] In some embodiments, the first gate structure and the second gate structure respectively form a first MOS structure and a second MOS structure with the substrate; wherein the first MOS structure and the second MOS structure respectively have different threshold voltages.

[0085] In some embodiments, contact holes are respectively provided on the source and drain regions, the first gate structure, and the second gate structure; wherein the contact holes are filled with metal material, and a connection layer covered by the metal material is formed on the sidewalls and bottom of the contact holes; wherein a contact connection layer is also provided between the contact holes on the source and drain regions and the source and drain regions.

[0086] In some embodiments, an extension direction of the channel is parallel to a surface of the substrate.

[0087] It should be noted that, in this embodiment, the explanation of the dual-gate MOS structure and its various parts can refer to the above embodiments and will not be repeated here.

[0088] In this embodiment, an unexpected effect is that while the dual-gate MOS structure 20 improves the electric field control capability through the second gate structure 21, since the contact surface between the first gate structure 181 and the substrate 121 is a portion of the side wall 141 of the lower recess 14, the length of the channel corresponding to the first gate structure 181 is increased without occupying additional wafer area, thereby improving the short channel effect and enhancing the performance of the dual-gate MOS structure 20.

[0089] In this embodiment, the dual-gate MOS structure can also be applied to high-voltage devices, and can improve the breakdown voltage of the high-voltage devices under the same size conditions.

[0090] It should be understood that the specific examples in this article are only intended to help those skilled in the art better understand the embodiments of the present application, and are not intended to limit the scope of the present invention.

[0091] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0092] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0093] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the application. The terms used in this application are just for the purpose of describing specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above" and "the" used in the embodiments of the present application are also intended to include plural forms, unless the context clearly indicates other meanings.

[0094] The above is only a specific embodiment of the present application, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in this application, and they should all be covered by the scope of protection of this application.

Claims

1. A dual-gate MOS structure, characterized in that: include: A substrate, wherein a concave portion is formed on a surface of the substrate, and a concave portion is also formed on a side surface adjacent to the substrate surface; a first gate structure embedded in the recess; a second gate structure, the second gate structure being located on the substrate surface between the first gate structure and the shallow trench isolation structure; wherein a contact surface formed between the first gate structure and the sidewall of the recessed portion is non-planar; The substrate and first gate structure of the dual-gate MOS structure are obtained by cutting the first gate structure precursor and the substrate precursor; the substrate precursor has an active area defined by a shallow trench isolation structure; a recessed hole is formed on the surface of the active area, and the gate structure precursor is filled in the recessed hole; the recessed portion is formed by a portion of the sidewall and bottom of the recessed hole after cutting; and, under the premise of pre-defined active area dimensions, two independent dual-gate MOS structures can be obtained after cutting the first gate structure precursor and the substrate precursor. The substrate also has source and drain regions formed on both sides of the first gate structure and the second gate structure; wherein the first gate structure and the second gate structure correspond to different channels respectively; wherein the extension direction of the channel corresponding to the first gate structure is consistent with the extension direction of the contact surface between the source and drain regions, so that the length of the channel corresponding to the first gate structure is greater than the spacing between the source and drain regions; wherein the source and drain regions extend to the shallow trench isolation structure along the arrangement direction of the active area in the substrate bulk; the first gate structure and the second gate structure respectively constitute a first MOS structure and a second MOS structure with the substrate; wherein the first MOS structure and the second MOS structure have different threshold voltages respectively.

2. The dual-gate MOS structure according to claim 1, wherein: A contact contour line is formed at the interface between the contact surface and the substrate surface; the contact contour line has a bent shape, or the contact contour line is in an arc shape.

3. The dual-gate MOS structure according to claim 1, wherein: Contact holes are respectively provided on the source and drain regions, the first gate structure and the second gate structure; wherein the contact holes are filled with metal material, and a connection layer covered by the metal material is formed on the sidewalls and bottom of the contact holes; wherein a contact connection layer is also provided between the contact holes on the source and drain regions and the source and drain regions.

4. The dual-gate MOS structure according to claim 1, wherein: An extension direction of the channel is parallel to the surface of the substrate.

5. A method for preparing a dual-gate MOS structure, characterized in that: Used for preparing a dual-gate MOS structure according to any one of claims 1 to 4; the preparation method comprises: Providing a substrate; the substrate comprises a substrate body and a shallow trench isolation structure; wherein the substrate body comprises an active area defined by the shallow trench isolation structure; a recessed hole is formed on the surface of the active area; Filling the recessed hole with a first gate structure precursor, and forming a second gate structure between the first gate structure precursor and the shallow trench isolation structure on the surface of the active area; The first gate structure precursor and the substrate precursor are cut using a plane perpendicular to the active area arrangement direction as a cutting plane to obtain the substrate, first gate structure, and second gate structure of the dual-gate MOS structure; wherein a portion of the sidewall and a portion of the bottom of the recessed hole form the recessed portion; wherein, under the premise of a pre-defined active area size, the first gate structure precursor and the substrate precursor can be cut to obtain two independent dual-gate MOS structures; Source and drain regions are formed in the substrate on both sides of the first gate structure and the second gate structure; wherein the first gate structure and the second gate structure correspond to different channels respectively; an extension direction of the channel corresponding to the first gate structure is consistent with an extension direction of the contact surface between the source and drain regions, so that the length of the channel corresponding to the first gate structure is greater than the spacing between the source and drain regions; wherein the source and drain regions extend to a shallow trench isolation structure along the arrangement direction of the active region in the substrate bulk; the first gate structure and the second gate structure respectively constitute a first MOS structure and a second MOS structure with the substrate; wherein the first MOS structure and the second MOS structure have different threshold voltages respectively.

6. The method for preparing a dual-gate MOS structure according to claim 5, wherein: In the step of cutting the first gate structure precursor and the substrate precursor by taking a plane perpendicular to the arrangement direction of the active regions as a cutting plane, the cutting plane passes through the center of the first gate structure precursor.

7. The method for preparing a dual-gate MOS structure according to claim 5, wherein: The active area includes an outer area surrounding the recessed hole; the steps of filling the recessed hole to form a first gate structure precursor, and forming a second gate structure between the first gate structure precursor and a shallow trench isolation structure on the surface of the active area include: A dielectric layer is provided in the active area; wherein the dielectric layer located in the area outside the hole is different from the dielectric layer located in the recessed hole in thickness and / or material; A first gate material is filled in the recessed hole formed with the dielectric layer to form a first gate structure precursor, and a second gate material is disposed on the dielectric layer in the area outside the hole to form a second gate structure.

8. The method for preparing a dual-gate MOS structure according to claim 7, wherein: The preparation method of the dual-gate MOS structure further includes: forming a contact layer on the surface of the source / drain region, and making contact holes on the surface of the contact layer, the first gate structure, and the second gate structure respectively; A connection layer is formed on the sidewall and bottom of the contact hole and filled with metal material; wherein the connection layer is covered by the metal material.

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