Wide bandgap semiconductor composite high-voltage vertical power chip and manufacturing process

Abstract

The invention discloses a wide bandgap semiconductor composite high-voltage vertical power chip and a manufacturing process thereof. The chip comprises at least one cellular structure unit, the cellular structure unit comprises a substrate, a transversely-integrated high-voltage-resistant layer made of a wide bandgap thin-layer material, a silicon thin-film layer, a silicon CMOS logic and switch control unit connected to the silicon thin-film layer, and a first multilayer dielectric layer, wherein the transversely-integrated high-voltage-resistant layer and the silicon thin-film layer are vertically arranged; the P + buried layer and the P-Top layer are located on the upper side and the lower side of the high-voltage-withstanding structural region respectively, and the transversely-integrated high-voltage-withstanding layer and the silicon thin film layer are connected through an interface bonding dielectric layer; the silicon CMOS logic and switch control unit comprises a silicon switch control unit and a silicon CMOS low-voltage logic unit, the silicon switch control unit is arranged in a first area of an upper tube arm of the high-voltage power tube, and the silicon CMOS low-voltage logic unit is arranged in a first area of a lower tube arm of the high-voltage power tube. According to the invention, the architecture of the high-voltage integrated chip can be optimized, and lower chip area and process cost can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a wide bandgap semiconductor composite high-voltage vertical power chip and a manufacturing process thereof. Background Art

[0002] High-voltage power integrated chips based on the 8-inch / 12-inch Fab platform BCD process (Bipolar, CMOS and DMOS) are widely used in various power management and power chip fields, and can realize the production of bipolar, CMOS and DMOS devices on the same chip. The development of BCD process does not completely follow Moore's law, but is differentiated in the three directions of high voltage, high power and high density. In recent years, the industry's demand requires higher voltage levels, up to 500-700V or even higher, and higher power density monolithic integrated PMIC (power management IC) chips. However, the voltage resistance of silicon materials themselves is limited. The silicon epitaxial layer of each μm thickness / length can only withstand a voltage of about 10V. The voltage resistance length of the silicon epitaxial layer in the high-voltage tube area of ​​the BCD process, especially above 700V, often requires more than 70μm. The process structure development is difficult and the process is complex. There is no large-scale effective technical implementation solution for silicon-based BCD processes above 1200V. In addition, in existing high-voltage BCD power chips, due to the voltage resistance limitation of silicon materials, a large area is required, and the high and low voltage isolation scheme is also very complicated, resulting in the high-voltage tube DMOS or LDMOS part occupying a very large area in the chip, and the process is complex and costly.

[0003] In recent years, wide bandgap semiconductor materials such as SiC, GaN, Ga2O3, and AlN have attracted much attention due to their superior properties such as high voltage resistance, high temperature resistance, and radiation resistance compared to silicon materials. If wide bandgap semiconductor whole wafer substrates (1) and epitaxial wafers are directly used to make high-voltage BCD process integrated chips, one is that the wide bandgap semiconductor materials themselves are not mature, and the cost of complete wafers of many materials is high. In addition, the devices made of wide bandgap semiconductor materials each have their own problems. For example, the gate oxide layer of the silicon carbide MOSFET structure has many defects, and the threshold voltage is prone to drift and other reliability problems. In addition, large special process equipment is required, and the process is complicated. GaN and Ga2O3 materials have poor P-type mobility or lack of effective P-type ion implantation activation structure problems; AlN has the problem of small material crystal size, less than 6 inches, and very high cost. However, these wide bandgap semiconductor thin film materials can be grown on the surface of different substrate (1) wafers through high-temperature CVD or MOCVD or MBE and other process methods, and large-scale wafer-level wide bandgap semiconductor thin film materials with a thickness of several hundred nanometers to more than ten microns can be constructed at low cost and with high quality; The industry still lacks effective chip architecture and process methods to combine mature silicon-based CMOS chip technology with the high voltage resistance of wide bandgap semiconductors to construct more effective, higher performance and lower cost composite power integrated chip solutions. In the future, as the industry technology demands higher voltage levels, 1200V or even higher, and higher power density monolithic integrated PMIC (power management IC) chips, it is urgent to explore new composite high-voltage power chip construction technologies.

[0004] In the existing all-silicon CMOS and BCD process technology solutions, in order to produce medium-high voltage and high-voltage power chip integration, it is often necessary to develop complex BCD high-voltage power unit processes and complex medium-high voltage and low-voltage logic area isolation process technology solutions. Especially for high-voltage DMOS and LDMOS, the voltage-resistant area not only occupies a large amount of precious chip area (such as Figure 1 As shown in the figure, the medium and high voltage power areas and the high voltage power chip area often account for more than 50% of the entire chip area), and it is necessary to produce expensive and complex isolation process structures such as junction isolation (JI), deep isolation (DTI), SOI isolation, and develop supporting high-uniformity ultra-deep hole etching, ultra-deep through-hole metal filling and planarization processes, which poses challenges to the process development of each module, such as the supporting thick oxide layer growth stress control, ultra-deep hole etching wafer uniformity control, ultra-deep through-hole metallization filling control, planarization process stop point and grinding uniformity control, etc., which brings about process complexity, various device characteristic problems, and yield problems.

[0005] Wide bandgap semiconductor materials such as SiC, GaN, Ga2O3, and AlN have excellent properties such as high voltage resistance, high temperature resistance, and radiation resistance that are superior to silicon materials. Whether some new chip architectures, device structures, and process manufacturing methods can be used to make the silicon CMOS logic unit area and the silicon switch control unit components in the power device structure still use traditional silicon materials, while the wide bandgap semiconductor drift area is integrated as a voltage-resistant unit to form a composite device chip technology, optimize the high-voltage integrated chip architecture, achieve better performance, lower chip area and process cost, and make a new type of composite high-voltage BCD power integrated chip is the technical problem to be solved by the present invention. Summary of the invention

[0006] Based on the above description, the present invention provides a wide bandgap semiconductor composite high-voltage vertical power chip and a manufacturing process to solve the technical problem that the chips in the prior art are made based on all-silicon and require the development of complex BCD high-voltage power unit processes and complex isolation process solutions for medium-high voltage and low-voltage logic areas. The solution of the present invention can optimize the high-voltage integrated chip architecture to achieve better performance, lower chip area and process costs.

[0007] The technical solution of the present invention to solve the above technical problems is as follows: On the one hand, the present invention provides a wide bandgap semiconductor composite high-voltage vertical power chip, which is a high-voltage BCD chip; The chip includes at least one cellular structure unit, which includes a substrate, a laterally integrated high-voltage-withstand layer made of a wide-bandgap thin layer material, a silicon thin film layer, a silicon CMOS logic and switch control unit connected to the silicon thin film layer, and a first multi-layer dielectric layer. The laterally integrated high-voltage-withstand layer and the silicon thin film layer are vertically arranged to enable the high-voltage power tube area and the low-voltage logic area to be in different physical layers to achieve self-isolation; The horizontally integrated high voltage-resistant layer comprises a horizontally integrated high voltage-resistant structure region made of a wide bandgap thin layer material, a P + buried layer and P-Top layer, the P + The buried layer and the P-Top layer are located at upper and lower sides of the laterally integrated high-voltage-withstand structure area, and the laterally integrated high-voltage-withstand layer and the silicon thin film layer are connected via an interface bonding dielectric layer; The silicon thin film layer is divided into a high-voltage power tube upper arm 1 region, a high-voltage power tube lower arm 1 region, and high-voltage power tube other arm regions by a first isolation trench and a second isolation trench filled with a multi-layer dielectric layer; The silicon CMOS logic and switch control unit includes a silicon switch control unit and a silicon CMOS low-voltage logic unit, wherein the silicon switch control unit is arranged in the upper tube arm 1 area of ​​the high-voltage power tube, and the silicon CMOS low-voltage logic unit is arranged in the lower tube arm 1 area of ​​the high-voltage power tube; The periphery of the silicon CMOS logic and switch control unit is isolated by partially or completely etching the silicon thin film layer to form a surrounding isolation trench and filling it with a first multi-layer dielectric layer.

[0008] Based on the above technical solution, the present invention can also be improved as follows.

[0009] Furthermore, in the above-mentioned wide bandgap semiconductor composite high-voltage vertical power chip, the silicon switch control unit includes a source, a first gate used to control the switch, a drain, a first P well region, a first N + Region, second N+ region, third N+ region, fourth N+ region, P connection column, first connection metal, second connection metal, third connection metal, the drain is arranged in other tube arm regions of the high voltage power tube.

[0010] Furthermore, in the above-mentioned wide bandgap semiconductor composite high-voltage vertical power chip, the laterally integrated high-voltage-withstand layer is connected between the silicon thin film layer and the substrate, and the side of the silicon thin film layer close to the substrate is connected to the high-voltage-withstand structure area through the interface bonding dielectric layer, and the P-Top layer is connected to the high-voltage-withstand structure area at the junction with the interface bonding dielectric layer, one end of which is located below the tube arm 1 area on the high-voltage power tube, and the other end is located below the other tube arm areas of the high-voltage power tube.

[0011] Furthermore, in the above-mentioned wide bandgap semiconductor composite high-voltage vertical power chip, the silicon thin film layer is connected between the laterally integrated high-voltage-withstand layer and the substrate, and the silicon CMOS logic and switch control unit on the side of the silicon thin film layer away from the substrate is isolated by partially or completely etching the silicon thin film layer to form an enclosing isolation groove and filling the first multi-layer dielectric layer, and is connected to the P+ buried layer through an interface bonding dielectric layer, and the P-Top layer side of the laterally integrated high-voltage-withstand layer is connected to the second multi-layer dielectric layer.

[0012] Furthermore, in the above-mentioned wide bandgap semiconductor composite high-voltage vertical power chip, a first metal through hole is opened on the tube arm 1 region of the high-voltage power tube near the first isolation trench, a first P well region is provided on the side of the tube arm 1 region of the high-voltage power tube away from the first metal through hole, and a first N+ region is provided on the other side, a second N+ region is provided on the first P well region, and both N+ regions are connected with ohmic contacts, a first gate oxide layer is provided in the first multi-layer dielectric layer at the junction with the two N+ regions, one end of the first gate oxide layer close to the first N+ region is connected to the ohmic contact on the first N+ region, and the first gate oxide layer is connected to the first gate on the side away from the high-resistance substrate; A first connection metal is connected in the first metal through hole, a source is connected above the tube arm 1 region on the high-voltage power tube on the side of the first multi-layer dielectric layer away from the substrate, one end of the source is connected to the ohmic contact on the second N+ region, and the other end is connected to the upper end of the first connection metal, and the lower end of the first connection metal is connected to the ohmic contact on one end of the P-Top layer away from the second isolation trench; A second metal through hole is provided on one side of the first N+ region near the first metal through hole and connected to the first N+ region, the lower end of the second metal through hole is located in the laterally integrated high-voltage-resistant structure region, a second connecting metal is connected in the second metal through hole, a P connecting column is connected below the second metal through hole on the high-voltage-resistant structure region, a side of the P connecting column near the second isolation trench is connected to the third N+ region, a side of the third N+ region near the second isolation trench exceeds the P connecting column, a lower end of the second connecting metal is connected to an ohmic contact that simultaneously connects the P connecting column and the third N+ region, and an upper end is connected to an ohmic contact on the first N+ region, a third metal through hole is provided in other tube arm regions of the high-voltage power tube, a third connecting metal is connected in the third metal through hole, a fourth N+ region having an ohmic contact is connected below the third metal through hole on the high-voltage-resistant structure region, and the drain is connected to the ohmic contact in the fourth N+ region through the third connecting metal; The hole walls of the first metal through hole, the second metal through hole and the third metal through hole are covered with a dielectric isolation layer with a thickness of 10nm-800nm.

[0013] Furthermore, the above-mentioned wide bandgap semiconductor composite high voltage vertical power chip, The silicon switch control unit includes a source, a first gate used for controlling the switch, a drain, a first P well region, a first N + District, Second N + District, Third N + District, Fourth N + Region, P connection column, fourth connection metal, fifth connection metal, sixth connection metal, seventh connection metal, the drain is arranged in other tube arm regions of the high voltage power tube; A fourth metal through hole extending to the silicon thin film layer is provided above the tube arm 1 region of the high-voltage power tube on the horizontally integrated high-voltage withstand layer, a first P well region is provided on one side of the tube arm 1 region of the high-voltage power tube away from the fourth metal through hole, a first N+ region is provided on the other side, a second N+ region is provided on the first P well region, both N+ regions are connected with ohmic contacts, a first gate oxide layer is provided in the first multi-layer dielectric layer at a junction with the two N+ regions, one end of the first gate oxide layer close to the first N+ region is connected to the ohmic contact on the first N+ region, and a side of the first gate oxide layer away from the high-resistance substrate is connected to the first gate; A source is connected above the second multi-layer dielectric layer, one end of the source is connected to the ohmic contact on the second N+ region through a fifth connection metal, and the other end is connected to the ohmic contact at one end of the P-Top layer away from the second isolation trench through a sixth connection metal; The fourth metal through hole is connected with a fourth connection metal, the end of the horizontally integrated high voltage-withstand layer away from the second isolation groove is connected with a P connection column, the side of the P connection column close to the second isolation groove is connected to the third N+ region, the side of the third N+ region close to the second isolation groove exceeds the P connection column, the lower end of the fourth connection metal is connected to the ohmic contact on the first N+ region, and the upper end is connected to the ohmic contact that simultaneously connects the P connection column and the third N+ region, the other tube arm regions of the high-voltage power tube on the horizontally integrated high voltage-withstand layer are connected to the fourth N+ region with an ohmic contact, the other tube arm regions of the high-voltage power tube on the second multi-layer dielectric layer are connected to the drain, and the drain is connected to the ohmic contact in the fourth N+ region through the seventh connection metal; The hole wall of the fourth metal through hole is covered with a dielectric isolation layer with a thickness of 10nm-800nm.

[0014] Furthermore, in the above-mentioned wide bandgap semiconductor composite high-voltage vertical power chip, the substrate is a high-resistance substrate arranged on a side of the P+ buried layer away from the laterally integrated high-voltage structural region, or the substrate includes a high-resistance SiC single crystal thin film layer connected to the side of the P+ buried layer away from the laterally integrated high-voltage structural region and a polycrystalline silicon carbide layer connected to the side of the high-resistance SiC single crystal thin film layer away from the laterally integrated high-voltage structural region, and the bottom of the isolation trench penetrates the P+ buried layer and is located in the high-resistance SiC single crystal thin film layer; The high-resistance substrate is high-resistance SiC, sapphire or high-resistance silicon wafer, and the thickness of the polycrystalline silicon carbide layer is 100-500 μm.

[0015] Furthermore, in the above-mentioned wide bandgap semiconductor composite high-voltage vertical power chip, the laterally integrated high-voltage layer is a wide bandgap thin layer material, which is an N-type doped semiconductor material; the wide bandgap thin layer material is made of SiC, GaN, Ga2O3 or AlN, with a thickness of 100nm-50μm, preferably 2μm, when the wide bandgap thin layer material is made of SiC, the ohmic contact metal is a nickel metal layer or a titanium-nickel-aluminum composite metal layer; and / or, The material of the interface bonding dielectric layer is SiO2 or benzocyclobutene resin, and the thickness of the interface bonding dielectric layer is 1nm-10μm; and / or, The multi-layer dielectric layer is formed by compounding SiO2 and SiN by CVD chemical vapor deposition method, and the thickness of the silicon thin film layer is 100nm-10μm; and / or, The silicon thin film layer is N-type doped and has a thickness of 100 nm-10 μm; and / or, The laterally integrated high voltage-resistant layer is formed by epitaxy or bonding.

[0016] Furthermore, in the above-mentioned wide bandgap semiconductor composite high-voltage vertical power chip, the silicon CMOS low-voltage logic unit includes a second P well region, an N well region, a second gate, a third gate, a second gate oxide layer, and a third gate oxide layer; A fifth N+ region and a sixth N+ region are respectively provided on both sides of the second P well region, and ohmic contacts are connected to the two N+ regions. A second gate oxide layer is connected to the connection between the multilayer dielectric layer and the second P well region, and both ends of the second gate oxide layer are respectively connected to the ohmic contacts; P+ buried layers are respectively provided on both sides of the N well region, and ohmic contacts are connected to the two P+ buried layers. A third gate oxide layer is connected to the connection between the multilayer dielectric layer and the N well region, and both ends of the third gate oxide layer are respectively connected to the ohmic contacts; a side of the second gate oxide layer away from the high-resistance substrate is connected to the second gate, and a side of the third gate oxide layer away from the high-resistance substrate is connected to the third gate.

[0017] On the other hand, the present invention also provides a process for manufacturing a wide bandgap semiconductor composite high voltage vertical power chip, comprising the following steps: S1. epitaxially or bonding a layer of N-type doped wide bandgap thin layer material on the substrate as a high voltage-resistant layer for lateral integration, wherein a P+ buried layer is connected to one side of the wide bandgap thin layer material close to the high-resistance substrate; S2, forming a third N+ region, a fourth N+ region, a P connection column and a P-Top withstand voltage field plate region in the wide bandgap thin layer material by ion implantation, and annealing and activation; S3, depositing ohmic contact metal in the area that needs to be connected to the device through hole of the upper silicon thin film layer in the future, and annealing to form ohmic contact; S4, depositing an interface bonding dielectric layer on the side of the high voltage withstand layer made of the wide bandgap thin layer material away from the high resistance substrate by CVD, ALD or spin coating process; S5, bonding a layer of N-type doped silicon thin film layer through wafer-level bonding process; S6, using CMOS technology in the silicon thin film layer to produce a silicon switch control unit and a silicon CMOS low voltage logic unit; S7. Etch metal vias and isolation grooves in the silicon thin film layer. The hole wall of the metal via is covered with a dielectric isolation layer with a thickness of 10nm-800nm. The center of the metal via is filled with connecting metal. The bottom of the connecting metal contacts the ohmic contact metal area of ​​the wide bandgap semiconductor to play an electrical connection role.

[0018] Furthermore, in the above-mentioned process for manufacturing a wide bandgap semiconductor composite high-voltage vertical power chip, steps S5, S6, and S7 are replaced by steps S5-1 and S6-1; S5-1, using a carrier wafer for temporary bonding and grinding the back silicon substrate to 2-10 μm, and then bonding it at the wafer level to the side of the high voltage-resistant layer made of a wide bandgap thin layer material away from the high-resistance substrate; the carrier wafer is a silicon thin film layer that integrates silicon CMOS logic and a switch control unit; S6-1. Etch metal vias and isolation grooves in the silicon thin film layer. The hole wall of the metal via is covered with a dielectric isolation layer with a thickness of 10nm-800nm. The center of the metal via is filled with connecting metal. The bottom of the connecting metal contacts the ohmic contact metal area of ​​the wide bandgap semiconductor to play an electrical connection role.

[0019] Compared with the prior art, the technical solution of the present invention has the following beneficial technical effects: First, the architecture and manufacturing process of the new high-voltage BCD power chip of this scheme combines the high-voltage and high-power characteristics of wide-bandgap semiconductors with the mature process platform of traditional silicon-based CMOS processes. Wide-bandgap semiconductor WBG (wide bandgap) materials such as SiC, GaN, Ga2O3, and AlN have excellent characteristics such as high voltage resistance, high temperature resistance, and radiation resistance that are superior to silicon materials. The voltage resistance of the wide-bandgap semiconductor epitaxial layer per μm thickness / length can reach more than 100V, which is more than 10 times higher than the silicon epitaxial layer per μm thickness. This scheme uses a new chip architecture, device structure and process manufacturing method to make the traditional silicon CMOS logic unit area and the silicon switch control unit components in the power device structure still use silicon materials, and integrate the wide-bandgap semiconductor drift area as a voltage-resistant unit to form a composite high-voltage device chip technology, optimize the high-voltage integrated chip architecture, and achieve a composite new high-voltage BCD power integrated chip with better performance, lower chip area and process cost; Second, it avoids the difficulties in constructing special processes such as high-voltage power DMOS or LDMOS die production and high-voltage isolation in the production of traditional silicon-based high-voltage BCD chips, as well as the difficulties in the subsequent evolution to high-voltage BCD processes above 1200V. For example, the existing silicon-based high-voltage BCD process requires the production of expensive and complex isolation process structures such as junction isolation (JI), deep isolation (DTI), and SOI isolation, and the development of supporting high-uniformity ultra-deep hole etching, ultra-deep through-hole metal filling and flattening processes, which poses challenges to the process development of each module, such as the supporting thick oxide layer growth stress control, ultra-deep hole etching uniformity control, ultra-deep through-hole metal filling control, flattening process stop point and grinding uniformity control, etc., which brings about process complexity, various device characteristic problems, and yield problems. Moreover, since the voltage resistance of the silicon epitaxial layer of silicon material per μm thickness / length is only about 10V, it is very difficult to continue to evolve to a high-voltage BCD process of 1200V and above, and the industry does not have a process solution suitable for large-scale production. The architecture and manufacturing process of the new high-voltage BCD power chip utilizes a method of combining a silicon CMOS logic and switch control unit with a wide-bandgap semiconductor voltage-resistant unit. The voltage resistance of the wide-bandgap semiconductor epitaxial layer of wide-bandgap semiconductor material per μm thickness / length can reach more than 100V. It can easily evolve to high-voltage power integrated chip technology above 1200V in the future, and it has a simple and easy isolation solution for self-isolation of the high-voltage tube area and the low-voltage logic area. The high-voltage voltage-resistant area of ​​the high-voltage power tube is in the wide-bandgap semiconductor material layer, which is not in the same physical layer as the silicon-based low-voltage logic unit layer, and is naturally isolated by an interface bonding dielectric layer in the middle. There is no need for the additional production of various complex isolation designs and complex processes in the traditional silicon-based BCD process. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A typical PMIC chip based on silicon BCD process (left) and a structural schematic diagram of ST's actual chip area analysis diagram (right) provided as background technology; Figure 2 This is a schematic diagram of the overall structure of a wide bandgap semiconductor composite high-voltage vertical power chip according to Embodiment 1 of the present invention; Figure 3 A schematic diagram of a current conduction path (pointed by a green dotted arrow) of a high-voltage power MOS tube device of a wide bandgap semiconductor composite high-voltage vertical power chip of the present invention when a positive voltage is applied to the gate relative to the source and a positive voltage is also applied to the drain relative to the source in Example 1 of the present invention when the device is turned on; Figure 4 A schematic diagram of a structure in which a high-voltage power MOS tube device of a wide-bandgap semiconductor composite high-voltage vertical power chip of Embodiment 1 of the present invention is turned off, that is, a negative voltage or 0V is applied to the gate of the silicon switch control unit relative to the source, and the drain of the device is at a positive high voltage relative to the source, the P-Top layer and the N drift region reversely bias the depletion region to expand and pinch off the drift region channel, thereby forming an effective reverse withstand voltage; at the same time, the bottom P+ layer of the wide-bandgap semiconductor thin layer is connected to the upper silicon switch control unit through a P connecting column, and its potential is at a low potential, and it will also form a reverse PN structure with the N-type drift region, which will assist the reverse depletion to pinch off the N drift region and assist in improving the withstand voltage capability; Figure 5 A schematic structural diagram of the connection relationship between the substrate (including a high-resistance SiC single crystal thin film layer and a polycrystalline silicon carbide layer), a lateral high-voltage withstand layer made of a wide-bandgap thin layer material, and a silicon thin film layer according to Example 2 of the present invention; Figure 6 It is a schematic structural diagram of the isolation trench, the upper tube arm 1 region of the high-voltage power tube, the lower tube arm 1 region of the high-voltage power tube, and other tube arm regions of the high-voltage power tube according to Embodiment 2 of the present invention (the P-Top layer is not shown); Figure 7 This is a schematic diagram of the overall structure of a wide bandgap semiconductor composite high-voltage vertical power chip according to Embodiment 3 of the present invention; Figure 8 A schematic structural diagram of the connection relationship between the substrate (high-resistance SiC, sapphire or high-resistance silicon wafer), the lateral high-voltage-withstand layer made of a wide-bandgap thin layer material and the silicon thin film layer according to Example 1 of the present invention; Figure 9-Figure 16 It is a structural schematic diagram of each step of a manufacturing process of a wide bandgap semiconductor composite high-voltage vertical power chip according to Embodiment 1 of the present invention; Fig.17 A schematic diagram comparing the layout of a CMOS low-voltage logic unit in the upper region of the P-Top layer of the high-voltage-withstand layer of the high-voltage power tube region (left) and the layout in the region outside the high-voltage power tube core (right); Fig.18This is a schematic diagram of the structure of a carrier wafer for manufacturing a silicon CMOS logic and switch control unit in step S5-1 of Example 5.

[0021] In the accompanying drawings, the components represented by the reference numerals are listed as follows: 1. Substrate; 2. High voltage withstand layer, 201. High voltage withstand structure area, 202. P+ buried layer, 203. P-Top layer; 3. Silicon thin film layer, 301. First isolation groove, 302. Second isolation groove, 303. High voltage power tube upper arm 1 area, 304. High voltage power tube lower arm 1 area, 305. High voltage power tube other arm areas; 4. First multi-layer dielectric layer; 5. Second multi-layer dielectric layer; 6. Silicon switch control unit, 601. Source, 602. First gate, 603. Drain, 604. First P well region, 605, first N+ region, 606, second N+ region, 607, third N+ region, 608, fourth N+ region, 609, P connection column, 610, first metal through hole, 6101, first connection metal, 611, second metal through hole, 6111, second connection metal, 612, third metal through hole, 6121, third connection metal, 613, fourth metal through hole, 6131, fourth connection metal, 614, fifth connection metal, 615, sixth connection metal, 616, seventh connection metal; 7, CMOS low voltage logic unit, 701, second P well region, 702, N well region, 703, second gate, 704, third gate, 705, second gate oxide layer, 706, third gate oxide layer; 8, interface bonding dielectric layer; 9, ohmic contact. DETAILED DESCRIPTION

[0022] In order to facilitate understanding of the present application, the present application will be described more comprehensively below. The present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0024] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. The "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0025] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0026] In the existing all-silicon CMOS and BCD process technology solutions, in order to produce medium-high voltage and high-voltage power chip integration, it is often necessary to develop complex BCD high-voltage power unit processes and complex isolation process technology solutions for medium-high voltage and low-voltage logic areas. In particular, the following three technical pain points: 1. The high-voltage DMOS or LDMOS power chip area accounts for a large proportion; the voltage resistance of the silicon material itself is limited. The silicon epitaxial layer of each μm thickness / length can only withstand a voltage of about 10V. The voltage resistance length of the silicon epitaxial layer in the high-voltage tube area of ​​the BCD process, especially above 700V, often needs to be more than 70μm. The process structure development is difficult, the process is complex, and the process cost is high; 2. The high-voltage power tube area, CMOS logic chip area and low-voltage tube area require complex isolation design and various expensive and complex isolation process technologies; 3. The development of high-power PMIC chips and BCD processes does not completely follow Moore's Law, but develops in three directions: high voltage, high power, and high density. In particular, in recent years, the industry has required monolithic integrated PMIC (power management IC) chips with higher voltage levels and higher power densities. However, the voltage resistance of silicon materials themselves is limited. The silicon epitaxial layer with a thickness / length of μm can only withstand a voltage of about 10V. There is no scale-effective technical implementation solution for silicon-based BCD processes above 1200V.

[0027] Wide bandgap semiconductor WBG (wide bandgap) materials such as SiC, GaN, Ga2O3, and AlN have excellent properties such as high voltage resistance, high temperature resistance, and radiation resistance that are superior to silicon materials. The voltage resistance of a wide bandgap semiconductor epitaxial layer per μm thickness / length can reach more than 100V, which is more than 10 times higher than the silicon epitaxial layer per μm thickness. This solution uses a new chip architecture, device structure, and process manufacturing method to ensure that the silicon CMOS low-voltage logic unit and the silicon switch control unit components in the power device structure are still made of traditional silicon materials, while the wide bandgap semiconductor drift region is integrated as a voltage-resistant unit to form a composite high-voltage device chip technology, optimize the high-voltage integrated chip architecture, achieve better performance, and lower chip area and process cost, thereby obtaining a new composite high-voltage BCD power integrated chip.

[0028] Example 1 The chip schematic diagram of this scheme is as follows Figure 2 As shown, a new type of high-voltage BCD chip technology is used that uses silicon CMOS logic and switch control units and a laterally integrated wide bandgap WBG thin layer material with a vertical arrangement of high-voltage resistant areas. The specific plan is as follows.

[0029] A wide bandgap semiconductor composite high-voltage vertical power chip, which is a high-voltage BCD chip; The chip includes at least one cellular structure unit, which includes a substrate 1, a laterally integrated high-voltage withstand layer 2 made of a wide bandgap thin layer material, a silicon thin film layer 3, a silicon CMOS logic and switch control unit connected to the silicon thin film layer 3, and a first multi-layer dielectric layer 4. The laterally integrated high-voltage withstand layer 2 and the silicon thin film layer 3 are vertically arranged to enable the high-voltage power tube area and the low-voltage logic area to be in different physical layers to achieve self-isolation; The laterally integrated high voltage-resistant layer 2 comprises a laterally integrated high voltage-resistant structure region 201 made of a wide bandgap thin layer material, a P+ buried layer 202 and a P-Top layer 203. + The buried layer 202 and the P-Top layer 203 are located at the upper and lower sides of the laterally integrated high voltage withstand structure area 201, and the laterally integrated high voltage withstand layer 2 and the silicon thin film layer 3 are connected via an interface bonding dielectric layer 8; The silicon thin film layer 3 is divided into a high-voltage power tube upper arm 1 region 303, a high-voltage power tube lower arm 1 region 304, and a high-voltage power tube other arm region 305 by a first isolation trench 301 and a second isolation trench 302 filled with a multi-layer dielectric layer; The silicon CMOS logic and switch control unit includes a silicon switch control unit 6 and a silicon CMOS low-voltage logic unit 7. The silicon switch control unit 6 is arranged in the upper arm 1 area 303 of the high-voltage power tube, and the silicon CMOS low-voltage logic unit 7 is arranged in the lower arm 1 area 304 of the high-voltage power tube. The periphery of the silicon CMOS logic and switch control unit is isolated by partially or completely etching the silicon thin film layer 3 to form a surrounding isolation trench and filling the first multi-layer dielectric layer 4 .

[0030] Furthermore, the laterally integrated high voltage-withstand layer 2 is connected between the silicon thin film layer 3 and the substrate 1, and the side of the silicon thin film layer 3 close to the substrate 1 is connected to the high voltage-withstand structure area 201 through the interface bonding dielectric layer 8, and the P-Top layer 203 is connected to the high voltage-withstand structure area 201 at the junction with the interface bonding dielectric layer 8, one end of which is located below the tube arm 1 area 303 on the high-voltage power tube, and the other end is located below the other tube arm area 305 of the high-voltage power tube.

[0031] Further, a first metal through hole 610 is formed on the arm 1 region 303 of the high-voltage power tube near the first isolation trench 301, a first P well region 604 is formed on one side of the arm 1 region 303 of the high-voltage power tube away from the first metal through hole 610, and a first N+ region 605 is formed on the other side, a second N+ region 606 is formed on the first P well region 604, both N+ regions are connected with an ohmic contact 9, a first gate oxide layer is formed in the first multi-layer dielectric layer 4 at a position connected with the two N+ regions, one end of the first gate oxide layer close to the first N+ region 605 is connected to the ohmic contact 9 on the first N+ region 605, and a side of the first gate oxide layer away from the high-resistance substrate is connected to the first gate 602; A first connection metal 6101 is connected in the first metal through hole 610, a source 601 is connected above the tube arm 1 region 303 of the high-voltage power tube on the side of the first multi-layer dielectric layer 4 away from the substrate, one end of the source 601 is connected to the ohmic contact 9 on the second N+ region 606, and the other end is connected to the upper end of the first connection metal 6101, and the lower end of the first connection metal 6101 is connected to the ohmic contact 9 at one end of the P-Top layer 203 away from the second isolation trench 302; A second metal through hole 611 is provided on one side of the first N+ region 605 near the first metal through hole 610 and connected to the first N+ region 605. The lower end of the second metal through hole 611 is located in the laterally integrated high voltage resistance structure region 201. A second connection metal 6111 is connected in the second metal through hole 611. A P connection column 609 is connected below the second metal through hole 611 on the high voltage resistance structure region 201. The P connection column 609 is connected to the third N+ region 607 on one side near the second isolation trench 302. The third N+ region 607 is beyond the P connection column 609 on one side near the second isolation trench 302. The lower end of the second connection metal 6111 is connected to the ohmic contact 9 that simultaneously connects the P connection column 609 and the third N+ region 607, and the upper end is connected to the ohmic contact 9 on the first N+ region 605. The other tube arm region 305 of the high-voltage power tube is provided with a third metal through hole 612, and the third metal through hole 612 is connected to the third connection metal 6121. The fourth N+ region 608 with the ohmic contact 9 is connected below the third metal through hole 612 on the high voltage withstand structure region 201, and the drain 603 is connected to the ohmic contact 9 in the fourth N+ region 608 through the third connection metal 6121. The hole walls of the first metal via 610, the second metal via 611 and the third metal via 612 are covered with a dielectric isolation layer with a thickness of tens of nanometers to hundreds of nm, such as silicon dioxide, and the size can be 10nm, 50nm, 100nm, 500nm, 800nm, etc.

[0032] Furthermore, the silicon switch control unit 6 includes a source 601, a first gate 602 used for controlling the switch, a drain 603, a first P well region 604, a first N+ region 605, a second N+ region 606, a third N+ region 607, a fourth N+ region 608, a P connection column 609, a first connection metal 6101, a second connection metal 6111, and a third connection metal 6121. The drain 603 is arranged in the other tube arm region 305 of the high-voltage power tube. The first gate 602 is the switch control gate of the composite power MOSFET tube.

[0033] Furthermore, the substrate 1 is a high-resistance substrate arranged on a side of the P+ buried layer 202 away from the laterally integrated high-voltage-resistant structure region 201 , and the high-resistance substrate is high-resistance SiC, sapphire or high-resistance silicon wafer.

[0034] Furthermore, in the above-mentioned wide bandgap semiconductor composite high-voltage vertical power chip, the silicon CMOS low-voltage logic unit 7 includes a second P well region 701, an N well region 702, a second gate 703, a third gate 704, a second gate oxide layer 705, and a third gate oxide layer 706; A fifth N+ region and a sixth N+ region are respectively provided on both sides of the second P well region 701, and ohmic contacts are connected to the two N+ regions. A second gate oxide layer 705 is connected to the connection between the multilayer dielectric layer and the second P well region 701, and both ends of the second gate oxide layer 705 are respectively connected to the ohmic contacts; P+ buried layers are respectively provided on both sides of the N well region 702, and ohmic contacts are connected to the two P+ buried layers. A third gate oxide layer 706 is connected to the connection between the multilayer dielectric layer and the N well region 702, and both ends of the third gate oxide layer 706 are respectively connected to the ohmic contacts; the second gate oxide layer 705 is connected to the second gate 703 on the side away from the high-resistance substrate, and the third gate oxide layer 706 is connected to the third gate 704 on the side away from the high-resistance substrate.

[0035] The working principle of the high-voltage power MOS tube device of this chip is as follows: (a) If Figure 3 As shown, when the device is turned on, that is, the silicon switch control unit 6 controls the silicon CMOS logic and the switch control unit gate to apply a positive voltage relative to the source 601 Source, and the device drain 603 Drain also applies a positive voltage relative to the source 601, the current conduction path of the high-voltage power MOS tube device of the composite structure chip when it is turned on is as indicated by the green dotted arrow; (b) If Figure 4As shown, when the device is turned off, that is, the silicon switch control unit 6 controls the gate of the silicon CMOS logic and the switch control unit to apply a negative voltage or 0V relative to the source 601 Source, and the device drain 603 Drain is at a positive high voltage relative to the source 601, the P-Top layer and the N drift region reverse bias depletion region expand to pinch off the drift region channel, forming an effective reverse withstand voltage; at the same time, the bottom P- + The buried layer 202 is connected to the upper silicon switch control unit 6 region through the P connection column 609, and the potential is at a low potential. It also forms a reverse PN structure with the N-type drift region, which helps reverse depletion to pinch off the N drift region and help improve the withstand voltage capability. What is described above is a cellular structure unit of a novel wide bandgap semiconductor composite high voltage vertical power chip. The actual power chip can be formed by connecting countless such cellular structures in parallel.

[0036] Example 2 This embodiment is basically the same as embodiment 1, except that Figure 5 As shown, the substrate 1 includes a high-resistance SiC single crystal thin film layer connected to the P+ buried layer 202 on the side away from the laterally integrated high-voltage-resistant structure area 201 and a polycrystalline silicon carbide layer connected to the high-resistance SiC single crystal thin film layer on the side away from the laterally integrated high-voltage-resistant structure area 201, and the bottom of the isolation trench penetrates the P+ buried layer 202 and is located in the high-resistance SiC single crystal thin film layer; the thickness of the polycrystalline silicon carbide layer is 100-500μm.

[0037] The advantage of this replacement solution is that the polycrystalline silicon carbide substrate has a low wafer substrate cost and excellent heat dissipation characteristics, which can further optimize the chip cost and heat dissipation capacity; like Figure 6 As shown, when multiple high-voltage and high-power tube cores are subsequently integrated, the high-resistance SiC single crystal thin film layer can provide a simple trench isolation technology for the upper arm high-voltage tube side and the lower arm high-voltage tube side. It only needs to etch the trench to the P on the upper surface of the high-resistance SiC single crystal thin film layer. + The buried layer 202 is etched and disconnected, thereby achieving high voltage isolation between different circuit structures of the high voltage die.

[0038] The manufacturing process of subsequent high-voltage integrated BCD power chips is exactly the same.

[0039] Example 3 The novel high-voltage BCD composite power chip can also be constructed with a wide bandgap voltage-resistant layer on top and silicon CMOS on the bottom. The chip structure is as follows: Figure 7 shown.

[0040] A wide bandgap semiconductor composite high-voltage vertical power chip, which is a high-voltage BCD chip; The chip includes at least one cellular structure unit, which includes a substrate 1, a laterally integrated high-voltage withstand layer 2 made of a wide bandgap thin layer material, a silicon thin film layer 3, a silicon CMOS logic and switch control unit connected to the silicon thin film layer 3, and a first multi-layer dielectric layer 4. The laterally integrated high-voltage withstand layer 2 and the silicon thin film layer 3 are vertically arranged to enable the high-voltage power tube area and the low-voltage logic area to be in different physical layers to achieve self-isolation; The laterally integrated high voltage-resistant layer 2 comprises a laterally integrated high voltage-resistant structure region 201 made of a wide bandgap thin layer material, + The buried layer 202 and the P-Top layer 203, the P + The buried layer 202 and the P-Top layer 203 are located at the upper and lower sides of the laterally integrated high voltage withstand structure area 201, and the laterally integrated high voltage withstand layer 2 and the silicon thin film layer 3 are connected via an interface bonding dielectric layer 8; The silicon thin film layer 3 is divided into a high-voltage power tube upper arm 1 region 303, a high-voltage power tube lower arm 1 region 304, and a high-voltage power tube other arm region 305 by a first isolation trench 301 and a second isolation trench 302 filled with a multi-layer dielectric layer; The silicon CMOS logic and switch control unit includes a silicon switch control unit 6 and a silicon CMOS low-voltage logic unit 7. The silicon switch control unit 6 is arranged in the upper arm 1 area 303 of the high-voltage power tube, and the silicon CMOS low-voltage logic unit 7 is arranged in the lower arm 1 area 304 of the high-voltage power tube. The periphery of the silicon CMOS logic and switch control unit is isolated by partially or completely etching the silicon thin film layer 3 to form a surrounding isolation trench and filling the first multi-layer dielectric layer 4 .

[0041] Furthermore, the silicon thin film layer 3 is connected between the laterally integrated high voltage-withstand layer 2 and the substrate 1, and the silicon CMOS logic and switch control unit periphery on the side of the silicon thin film layer 3 away from the substrate 1 is isolated by partially or completely etching the silicon thin film layer 3 to form an enclosing isolation groove and filling the first multi-layer dielectric layer 4, and is connected to the P+ buried layer 202 through the interface bonding dielectric layer 8, and the P-Top layer 203 side of the laterally integrated high voltage-withstand layer 2 is connected to the second multi-layer dielectric layer 5.

[0042] Furthermore, the silicon switch control unit 6 includes a source 601, a first gate 602 used as a control switch, a drain 603, a first P well region 604, a first N + Area 605, Second N + Area 606, Third N + District 607, Fourth N +Region 608 , P connection column 609 , fourth connection metal 6131 , fifth connection metal 614 , sixth connection metal 615 , seventh connection metal 616 , the drain 603 is arranged in other tube arm region 305 of the high voltage power tube.

[0043] Furthermore, a fourth metal through hole 613 extending to the silicon thin film layer 3 is provided above the tube arm 1 region 303 of the high voltage power tube on the horizontally integrated high voltage layer 2, and a first P well region 604 is provided on one side of the tube arm 1 region 303 of the high voltage power tube away from the fourth metal through hole 613, and a first N well region 604 is provided on the other side. + Region 605, the first P well region 604 is provided with a second N + Area 606, two N + The regions are connected to ohmic contacts 9, and the first multi-layer dielectric layer 4 is connected to two N + A first gate oxide layer is provided at the junction of the first N + One end of the region 605 is connected to the first N + The ohmic contact 9 on the region 605 is connected, and the side of the first gate oxide layer away from the high-resistance substrate is connected to the first gate 602; A source electrode 601 is connected to the second multi-layer dielectric layer 5. One end of the source electrode 601 is connected to the second N electrode 601 through a fifth connection metal 614. + The ohmic contact 9 on the region 606 is connected, and the other end is connected to the ohmic contact 9 at one end of the P-Top layer 203 away from the second isolation trench 302 through the sixth connection metal 615; The fourth metal through hole 613 is connected to the fourth connection metal 6131, and the end of the horizontally integrated high voltage layer 2 away from the second isolation groove 302 is connected to the P connection column 609, and the side of the P connection column 609 close to the second isolation groove 302 is connected to the third N + District 607, 3rd N + The side of the region 607 close to the second isolation trench 302 exceeds the P connection column 609, and the lower end of the fourth connection metal 6131 is connected to the first N + The ohmic contact 9 on the region 605 is connected, and the upper end is connected to the P connection column 609 and the third N + The ohmic contact 9 of the region 607 is connected, and the other tube arm region 305 of the high-voltage power tube on the horizontally integrated high-voltage layer 2 is connected to the fourth N having the ohmic contact 9. + Region 608, the second multi-layer dielectric layer 5 is connected to the drain 603 above the other tube arm region 305 of the high-voltage power tube, and the drain 603 is connected to the fourth N + Ohmic contact 9 in region 608 is connected; The hole wall of the fourth metal through hole 613 is covered with a dielectric isolation layer with a thickness of tens of nanometers to hundreds of nanometers.

[0044] Furthermore, the substrate 1 is provided on P + The buried layer 202 is away from the high-resistance substrate on one side of the laterally integrated high-voltage-withstand structure region 201 , and the high-resistance substrate is high-resistance SiC, sapphire or high-resistance silicon wafer.

[0045] Compared with the main scheme of Example 1, the scheme of this embodiment has a silicon CMOS logic and switch control unit in the area close to the substrate 1, and the isolation of high and low voltage areas is more thorough, and is less affected by the high-voltage large signal interference of the top high-voltage part. However, it is necessary to add more through-hole connections and metal layer processes, which will increase the process cost.

[0046] Furthermore, in the above-mentioned wide bandgap semiconductor composite high-voltage vertical power chip, the silicon CMOS low-voltage logic unit 7 includes a second P well region 701, an N well region 702, a second gate 703, a third gate 704, a second gate oxide layer 705, and a third gate oxide layer 706; A fifth N+ region and a sixth N+ region are respectively provided on both sides of the second P well region 701, and ohmic contacts are connected to the two N+ regions. A second gate oxide layer 705 is connected to the connection between the multilayer dielectric layer and the second P well region 701, and both ends of the second gate oxide layer 705 are respectively connected to the ohmic contacts; P+ buried layers are respectively provided on both sides of the N well region 702, and ohmic contacts are connected to the two P+ buried layers. A third gate oxide layer 706 is connected to the connection between the multilayer dielectric layer and the N well region 702, and both ends of the third gate oxide layer 706 are respectively connected to the ohmic contacts; the second gate oxide layer 705 is connected to the second gate 703 on the side away from the high-resistance substrate, and the third gate oxide layer 706 is connected to the third gate 704 on the side away from the high-resistance substrate.

[0047] In the above embodiments, the laterally integrated high-voltage-withstand layer 2 is a wide bandgap thin layer material, which is an N-type doped semiconductor material; the wide bandgap thin layer material is made of SiC, GaN, Ga2O3 or AlN, and has a thickness of 100nm-50μm, preferably 2μm. When the wide bandgap thin layer material is made of SiC, the ohmic contact 9 metal is a nickel metal layer (Ni) or a titanium-nickel-aluminum composite metal layer (Ti, Ni, Al); The material of the interface bonding dielectric layer 8 is SiO2 or benzocyclobutene resin, and the thickness of the interface bonding dielectric layer 8 is 1nm-10μm, preferably 300nm; The multi-layer dielectric layer is composited by SiO2 and SiN through CVD chemical vapor deposition method, and the thickness of the silicon thin film layer 3 is 100nm-10μm, preferably 600nm; The silicon thin film layer 3 is N-type doped; the laterally integrated high voltage resistance layer 2 is formed by epitaxy or bonding.

[0048] Example 4: A manufacturing process of a wide bandgap semiconductor composite high voltage vertical power chip of Example 1 The new composite BCD power chip of this scheme can be manufactured using the following process technologies: 1. Silicon and wide bandgap film composite wafer technology used in chips The BCD power chip is made of a composite wafer stacked with silicon wafers and wide bandgap semiconductor thin film materials; the silicon thin film layer 3 (usually 100nm-10μm thick) is bonded to a wide bandgap semiconductor thin film material such as SiC, GaN, Ga2O3, AlN, etc. (usually 100nm-50μm thick) on a high-resistance substrate through a silicon dioxide interface bonding dielectric layer or other dielectric layer materials such as BCB, and integrated through wafer-level bonding to form a composite wafer; typical composite wafer parameter specifications are as follows Figure 8 As shown: 2. A manufacturing process for a wide bandgap semiconductor composite high voltage vertical power chip: S1, such as Fig. 9 As shown, a high-resistance SiC, sapphire, high-resistance silicon wafer or other high-resistance substrate is purchased, and then a wide bandgap thin layer material is epitaxially or bonded as a high-voltage structural region, generally an N-type doped layer with a thickness of 100nm-50μm, preferably 2μm thick; the high-voltage structural region made of the wide bandgap thin layer material has a thin layer of P on one side close to the high-resistance substrate + The buried layer 202 is 10nm-500nm, preferably 100nm; the P + The buried layer 202 can be obtained by peeling off and bonding after epitaxy or P-type ion implantation; S2, such as Fig.10 As shown, a third N is formed by ion implantation in the high voltage withstand structure region made of wide bandgap thin layer material. + District, Fourth N + Region 608, P connection column 609 and P-Top voltage-resistant field plate region, and annealing activation; S3, such as Fig.11 As shown, in the area that needs to be connected to the through hole of the device area of ​​the upper silicon thin film layer 3 in the future, a suitable ohmic contact 9 metal is deposited and annealed to form the ohmic contact 9; for example, if the wide bandgap material is SiC, the ohmic contact 9 metal can be a nickel metal layer (Ni) or a titanium-nickel-aluminum composite metal layer (Ti, Ni, Al); S4, such as Fig.12As shown, an interface bonding dielectric layer is deposited on the surface of the horizontally integrated high-voltage-withstand layer 2 that has been ion-implanted and ohmic-contacted 9 by CVD, ALD or spin coating. The dielectric layer material can be silicon dioxide, or BCB and other materials; BCB (Benzocyclobutene) is an active resin, and its chemical name is benzocyclobutene resin. Under specific heat treatment conditions, BCB can form a thermosetting polymer. This material has low dielectric constant, low dielectric loss, low moisture absorption rate, high thermal stability and good chemical stability; the interface bonding dielectric layer material is generally 1nm-10μm, and the optimized interface bonding dielectric layer 8 is 300nm SiO2; S5, such as Fig.12 As shown, a silicon thin film layer 3 is bonded by a wafer-level bonding process, with a thickness of 100nm-10μm, which is generally an N-type doped layer, preferably 600nm; S6, such as Fig.13 As shown, the silicon switch control unit 6 of the high-voltage power chip and the CMOS low-voltage logic unit are then manufactured in the silicon thin film layer 3 using the CMOS process; Preferably, Fig.14 As shown, the silicon CMOS low-voltage logic unit 7 can be arranged in the upper area of ​​the high-voltage withstand structure area P-Top layer 203 made of a wide bandgap thin layer material in the high-voltage power tube area to save the entire chip area; the process cross-sectional diagram when the silicon CMOS low-voltage logic unit 7 is arranged in the upper area of ​​the wide bandgap material P-Top layer 203 in the high-voltage power tube area, as shown in Fig.15 As shown: Alternatively, the silicon CMOS low-voltage logic unit 7 may also be arranged in a region outside the high-voltage power die. S7, such as Fig.15 As shown, metal vias and isolation trenches are etched in the silicon thin film layer 3, and metal vias Via are filled with metal in the area where electrical connection is required between the silicon CMOS logic and switch control unit and the high withstand voltage layer 2 of the underlying wide bandgap semiconductor lateral integration; the metal vias Via are preferably filled with metals such as titanium (Ti), titanium nitride (TiN), tungsten (W), or aluminum or copper; these are all processes commonly used in CMOS processes and will not be described in detail; The structure of the metal through hole is to etch a via through hole that penetrates the silicon thin film layer 3 and the bonding interface dielectric layer. The bottom of the metal through hole contacts the ohmic contact 9 metal area on the surface of the wide bandgap semiconductor material. The hole wall of the metal through hole is covered with a dielectric isolation layer with a thickness of tens of nanometers to hundreds of nanometers. The center of the metal through hole is filled with metal via material, which contacts the ohmic contact 9 metal area of ​​the wide bandgap semiconductor to play an electrical connection role. The cross-sectional schematic diagram of the chip after the high-voltage power tube area is completed is shown in the figure. Fig.15As shown: When the CMOS low-voltage logic unit is arranged in the upper area of ​​the P-Top layer 203 of the high-voltage withstand layer of the high-voltage power tube area, the process cross-sectional diagram is as follows Fig.16 shown. Schematic diagram of the comparison of two CMOS low-voltage logic unit chip area optimization layouts, such as Fig.17 shown.

[0049] Example 5: A manufacturing process of a wide bandgap semiconductor composite high voltage vertical power chip of Example 2 This embodiment is basically the same as Embodiment 4, except that process steps S5-S7 can also be implemented by another process alternative.

[0050] That is, S5-1, after the wide bandgap semiconductor voltage-resistant structure region is fabricated and the interface bonding dielectric layer 8 is deposited in step S4 of embodiment 4, as shown in FIG. Fig.18 As shown, the top bonded silicon film layer 3 can be a wafer that has been made of silicon CMOS logic and switch control unit using another silicon epitaxial wafer and CMOS process. Then, the carrier wafer with silicon CMOS logic and switch control unit is temporarily bonded and back-ground to thin and remove the silicon substrate, that is, generally thinned to 2-10μm, and then bonded at the wafer level to the composite wafer surface after the wide bandgap semiconductor withstand voltage structure area is made and the interface bonding dielectric layer 8 is deposited.

[0051] S6-1, then similar to the above step S7 process, metal vias and isolation trenches are etched in the silicon thin film layer 3, and metal vias Via metal filling is performed in the area where electrical connection is required between the silicon CMOS logic and switch control unit and the high withstand voltage layer 2 of the underlying wide bandgap semiconductor lateral integration; the preferred via connection metal filling adopts titanium (Ti), titanium nitride (TiN), tungsten (W) and other metals, and can also be aluminum or copper metals; these are all processes commonly used in CMOS processes and will not be described in detail. At this point, the process is completed, and the completed chip is as follows Fig.16 shown.

[0052] The key technical points of the present invention are as follows: 1. The chip is made of a composite wafer stacked with a high-resistance substrate and a wide-bandgap semiconductor material; the silicon thin film layer 3 (generally 100nm-10μm thick) is integrated with a wide-bandgap semiconductor material such as SiC, GaN, Ga2O3, AlN, etc. (generally 100nm-50μm thick) on a high-resistance substrate through a silicon dioxide dielectric or other dielectric layer materials such as BCB, and is integrated through wafer-level bonding to form a composite wafer; 2. The silicon switch control unit 6 and the silicon CMOS low-voltage logic unit 7 of the chip are manufactured in the silicon thin film layer; the periphery of the low-voltage logic area can be isolated by partially or completely etching the silicon thin film layer 3 to form an isolation groove surrounding it and filling it with SiO2 / SiN and other dielectrics, which is a simple and convenient process; 3. The high-voltage power DMOS or LDMOS tube part of the chip adopts a composite structure. The silicon switch control unit 6 of the power tube is completed in the silicon thin film layer. The MOS switch control area is constructed using conventional silicon-based CMOS technology, and then connected to the high-voltage withstand area of ​​the wide bandgap semiconductor material under the bonding interface dielectric layer through a metal through hole; the typical structure of the high-voltage withstand area is constructed by combining the lateral P-Top layer 203 of the wide bandgap semiconductor region and the P+ buried layer, which can effectively provide lateral voltage withstand shutdown in reverse and good forward conduction characteristics; the P-Top layer 203 on the top of the wide bandgap semiconductor thin film layer is connected to the source 601 of the upper silicon switch control unit through a metal through hole The Source metal field plate is connected to construct a lateral equipotential P-type field plate to achieve more reliable lateral withstand voltage capability; the metal through hole is constructed by etching a Via through hole that penetrates the silicon thin film layer 3 and the bonding interface dielectric layer, the bottom of the through hole contacts the ohmic contact 9 metal area on the surface of the wide bandgap semiconductor material, the hole wall of the metal through hole is covered with a dielectric isolation layer with a thickness of tens of nanometers to hundreds of nanometers, the center of the metal through hole is filled with a metal Via material, which contacts the ohmic contact 9 metal area of ​​the wide bandgap semiconductor and plays an electrical connection role; 4. Optionally, the silicon CMOS logic and switch control unit of the chip can be placed above the voltage-resistant structure P-Top layer of the high-voltage power DMOS or LDMOS in the chip top view layout to save the chip layout area; or it can be placed separately in the area outside the high-voltage power tube; 5. This solution has a simple and easy isolation solution for self-isolation of the high-voltage power tube area and the low-voltage logic area. The high-voltage withstand voltage area of ​​the high-voltage power tube is in a wide-bandgap semiconductor thin layer material, which is not in the same physical layer as the silicon CMOS logic and switch control unit, and is naturally isolated by an interface bonding dielectric layer 8 in the middle; it does not require the additional production of various complex isolation designs and complex processes in the traditional silicon-based BCD process; 6. This solution can also be made of a composite wafer of a high-resistance SiC single crystal thin film layer and a polycrystalline silicon carbide layer. The advantage of this replacement solution is that the polycrystalline silicon carbide substrate has a low wafer substrate cost and excellent heat dissipation characteristics, which can further optimize the chip cost and heat dissipation capacity; at the same time, when multiple high-voltage and high-power tube cores are subsequently integrated, the high-resistance SiC single crystal thin film layer can provide a simple trench isolation technology for the high-voltage power tube upper arm 1 area 303, the high-voltage power tube lower arm 1 area 304, and the high-voltage power tube other arm areas 305. It only needs to etch the isolation trench to the P on the upper surface of the high-resistance SiC single crystal thin film layer. + The buried layer 202 is etched and disconnected, thereby achieving high voltage isolation between different circuit structures of the high voltage die.

[0053] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A wide bandgap semiconductor composite high voltage vertical power chip, characterized in that: It is a high voltage BCD chip; The chip comprises at least one cellular structure unit, the cellular structure unit comprising a substrate (1), a laterally integrated high-voltage withstand layer (2) made of a wide-bandgap thin layer material, a silicon thin film layer (3), a silicon CMOS logic and switch control unit connected to the silicon thin film layer (3), and a first multi-layer dielectric layer (4), wherein the laterally integrated high-voltage withstand layer (2) and the silicon thin film layer (3) are arranged vertically; The laterally integrated high voltage-resistant layer (2) comprises a laterally integrated high voltage-resistant structure region (201) made of a wide bandgap thin layer material, + The buried layer (202) and the P-Top layer (203), the P + The buried layer (202) and the P-Top layer (203) are located at upper and lower sides of the laterally integrated high-voltage-withstand structure region (201), and the laterally integrated high-voltage-withstand layer (2) and the silicon thin film layer (3) are connected via an interface bonding dielectric layer (8); The silicon thin film layer (3) is divided into a high-voltage power tube upper arm 1 region (303), a high-voltage power tube lower arm 1 region (304), and high-voltage power tube other arm regions (305) by a first isolation groove (301) and a second isolation groove (302) filled with a multi-layer dielectric layer; The silicon CMOS logic and switch control unit comprises a silicon switch control unit (6) and a silicon CMOS low-voltage logic unit (7), wherein the silicon switch control unit (6) is arranged in an upper tube arm 1 region (303) of the high-voltage power tube, and the silicon CMOS low-voltage logic unit (7) is arranged in a lower tube arm 1 region (304) of the high-voltage power tube; The periphery of the silicon CMOS logic and switch control unit is isolated by partially or completely etching the silicon thin film layer (3) to form a surrounding isolation groove and filling the first multi-layer dielectric layer (4).

2. The wide bandgap semiconductor composite high voltage vertical power chip according to claim 1, characterized in that: The silicon switch control unit (6) comprises a source (601), a first gate (602) used for controlling the switch, a drain (603), a first Pwell region (604), a first N + Area (605), Second N + District (606), Third N + District (607), Fourth N + Region (608), P connection column (609), first connection metal (6101), second connection metal (6111), third connection metal (6121), the drain (603) is arranged in other tube arm regions (305) of the high-voltage power tube.

3. The wide bandgap semiconductor composite high voltage vertical power chip according to claim 2, characterized in that: The laterally integrated high voltage-resistant layer (2) is connected between the silicon thin film layer (3) and the substrate (1), and the side of the silicon thin film layer (3) close to the substrate (1) is connected to the high voltage-resistant structure region (201) via an interface bonding dielectric layer (8), and the P-Top layer (203) is connected to the high voltage-resistant structure region (201) at the junction with the interface bonding dielectric layer (8), with one end located below the tube arm 1 region (303) on the high-voltage power tube, and the other end located below the other tube arm regions (305) of the high-voltage power tube.

4. The wide bandgap semiconductor composite high voltage vertical power chip according to claim 1, characterized in that: The silicon thin film layer (3) is connected between the laterally integrated high voltage withstand layer (2) and the substrate (1), and the silicon CMOS logic and switch control unit periphery on the side of the silicon thin film layer (3) away from the substrate (1) is isolated by partially or completely etching the silicon thin film layer (3) to form an enclosing isolation groove and filling the first multi-layer dielectric layer (4), and is connected to the P+ buried layer (202) via an interface bonding dielectric layer (8), and the P-Top layer (203) side of the laterally integrated high voltage withstand layer (2) is connected to the second multi-layer dielectric layer (5).

5. The wide bandgap semiconductor composite high voltage vertical power chip according to claim 3, characterized in that: A first metal through hole (610) is provided on the tube arm 1 region (303) on the high-voltage power tube near the first isolation groove (301); a first P well region (604) is provided on one side of the tube arm 1 region (303) on the high-voltage power tube away from the first metal through hole (610); and a first N + Area (605), the first P well area (604) is provided with a second N + Area (606), two N + The regions are connected to ohmic contacts (9), and the first multilayer dielectric layer (4) is connected to two N + A first gate oxide layer is provided at the junction of the first N + One end of the area (605) is connected to the first N + The ohmic contact (9) on the region (605) is connected, and the side of the first gate oxide layer away from the high-resistance substrate is connected to the first gate (602); A first connection metal (6101) is connected in the first metal through hole (610), a source electrode (601) is connected above the tube arm 1 region (303) on the high-voltage power tube on the side of the first multi-layer dielectric layer (4) away from the substrate, and one end of the source electrode (601) is connected to the second N + The first connection metal (6101) is connected to the ohmic contact (9) on the region (606), and the other end is connected to the upper end of the first connection metal (6101), and the lower end of the first connection metal (6101) is connected to the ohmic contact (9) at one end of the P-Top layer (203) away from the second isolation groove (302); First N + The region (605) is close to one side of the first metal through hole (610) and is adjacent to the first N + A second metal through hole (611) is provided at the junction of the two regions (605), the lower end of the second metal through hole (611) is located in the laterally integrated high voltage resistance structural region (201), a second connection metal (6111) is connected in the second metal through hole (611), a P connection column (609) is connected below the second metal through hole (611) on the high voltage resistance structural region (201), and a side of the P connection column (609) close to the second isolation groove (302) is connected to a third N + District (607), Third N + The side of the region (607) close to the second isolation trench (302) exceeds the P connection column (609), and the lower end of the second connection metal (6111) is connected to the P connection column (609) and the third N + The ohmic contact (9) of the region (607) is connected to the upper end of the first N + The high voltage power tube is connected to an ohmic contact (9) on the region (605); the other tube arm region (305) of the high voltage power tube is provided with a third metal through hole (612); the third metal through hole (612) is connected to a third connecting metal (6121); the third metal through hole (612) on the high voltage withstand structure region (201) is connected to a fourth N+ region (608) having an ohmic contact (9) below; the drain (603) is connected to the fourth N+ region (608) through the third connecting metal (6121). + The ohmic contact (9) in the region (608) is connected; The hole walls of the first metal through hole (610), the second metal through hole (611) and the third metal through hole (612) are covered with a dielectric isolation layer with a thickness of 10 nm to 800 nm.

6. The wide bandgap semiconductor composite high voltage vertical power chip according to claim 4, characterized in that: The silicon switch control unit (6) comprises a source (601), a first gate (602) used for controlling the switch, a drain (603), a first P well region (604), a first N + Area (605), Second N + District (606), Third N + District (607), Fourth N + region (608), a P connection column (609), a fourth connection metal (6131), a fifth connection metal (614), a sixth connection metal (615), and a seventh connection metal (616), wherein the drain (603) is arranged in other tube arm regions (305) of the high-voltage power tube; A fourth metal through hole (613) extending to the silicon film layer (3) is provided above the tube arm 1 region (303) of the high-voltage power tube on the horizontally integrated high-voltage layer (2), and a first P well region (604) is provided on one side of the tube arm 1 region (303) of the high-voltage power tube away from the fourth metal through hole (613), and a first N well region (604) is provided on the other side. + Area (605), the first P well area (604) is provided with a second N + Area (606), two N + The regions are connected to ohmic contacts (9), and the first multilayer dielectric layer (4) is connected to two N + A first gate oxide layer is provided at the junction of the first N + One end of the area (605) is connected to the first N + The ohmic contact (9) on the region (605) is connected, and the side of the first gate oxide layer away from the high-resistance substrate is connected to the first gate (602); A source electrode (601) is connected above the second multi-layer dielectric layer (5), and one end of the source electrode (601) is connected to the second N + The ohmic contact (9) on the region (606) is connected, and the other end is connected to the ohmic contact (9) at one end of the P-Top layer (203) away from the second isolation trench (302) through a sixth connection metal (615); The fourth metal through hole (613) is internally connected to a fourth connection metal (6131); an end of the horizontally integrated high voltage resistance layer (2) away from the second isolation groove (302) is internally connected to a P connection column (609); and a side of the P connection column (609) close to the second isolation groove (302) is connected to a third N + District (607), Third N + The side of the region (607) close to the second isolation trench (302) exceeds the P connection column (609), and the lower end of the fourth connection metal (6131) is connected to the first N + The ohmic contact (9) on the region (605) is connected, and the upper end is connected to the P connection column (609) and the third N + The ohmic contact (9) of the region (607) is connected, and the other tube arm region (305) of the high-voltage power tube on the horizontally integrated high-voltage layer (2) is connected to the fourth N having the ohmic contact (9) above. + Region (608), the second multi-layer dielectric layer (5) is connected to the drain (603) above the other tube arm region (305) of the high-voltage power tube, and the drain (603) is connected to the fourth N through the seventh connecting metal (616). + The ohmic contact (9) in the region (608) is connected; The hole wall of the fourth metal through hole (613) is covered with a dielectric isolation layer with a thickness of 10nm-800nm.

7. The wide bandgap semiconductor composite high voltage vertical power chip according to claim 1, characterized in that: The substrate (1) is arranged on a P + The buried layer (202) is far away from the high-resistance substrate on one side of the laterally integrated high-voltage-resistant structural region (201); or the substrate (1) includes a high-resistance substrate connected to P + The buried layer (202) is a high-resistance SiC single crystal thin film layer on a side away from the lateral integrated high-voltage withstand structure region (201) and a polycrystalline silicon carbide layer connected to the high-resistance SiC single crystal thin film layer on a side away from the lateral integrated high-voltage withstand structure region (201), wherein the bottom of the isolation trench penetrates the P + The buried layer (202) is located in the high-resistance SiC single crystal thin film layer; The high-resistance substrate is high-resistance SiC, sapphire or high-resistance silicon wafer, and the thickness of the polycrystalline silicon carbide layer is 100-500 μm.

8. The wide bandgap semiconductor composite high voltage vertical power chip according to claim 1, characterized in that: The laterally integrated high voltage-resistant layer (2) is a wide bandgap thin layer material, which is an N-type doped semiconductor material; the wide bandgap thin layer material is made of SiC, GaN, Ga2O3 or AlN, and has a thickness of 100nm-50μm; and / or, The material of the interface bonding medium layer (8) is SiO2 or benzocyclobutene resin, and the thickness of the interface bonding medium layer (8) is 1 nm-10 μm; and / or, The multi-layer dielectric layer is composited by SiO2 and SiN through CVD chemical vapor deposition method, and the thickness of the silicon thin film layer (3) is 100nm-10μm; and / or, The silicon thin film layer (3) is N-type doped and has a thickness of 100 nm-10 μm; and / or, The laterally integrated high voltage-resistant layer (2) is formed by epitaxy or bonding.

9. The manufacturing process of a wide bandgap semiconductor composite high voltage vertical power chip according to claim 5, characterized in that: The following steps are involved: S1. epitaxially or bondedly on a substrate (1) a layer of N-type doped wide bandgap thin layer material as a lateral integrated high voltage resistance layer (2), wherein the wide bandgap thin layer material is connected to a P layer on one side close to the high resistance substrate. + buried layer (202); S2, forming the third N in the wide bandgap thin layer material by ion implantation + District (607), Fourth N + Region (608), P connecting column (609) and P-Top voltage-resistant field plate region, and annealing and activation; S3, depositing ohmic contact (9) metal in the area that needs to be connected to the device through hole of the upper silicon thin film layer (3) in the future, and annealing to form the ohmic contact (9); S4, depositing an interface bonding dielectric layer on the side of the high voltage withstand layer made of the wide bandgap thin layer material away from the high resistance substrate by CVD, ALD or spin coating process; S5, bonding a layer of N-type doped silicon thin film layer (3) through a wafer-level bonding process; S6, using CMOS technology to manufacture a silicon switch control unit (6) and a silicon CMOS low-voltage logic unit (7) in the silicon thin film layer (3); S7. Etching metal vias and isolation grooves in the silicon thin film layer (3). The hole wall of the metal via is covered with a dielectric isolation layer with a thickness of 10nm-800nm. The center of the metal via is filled with connecting metal. The bottom of the connecting metal contacts the ohmic contact (9) metal region of the wide bandgap semiconductor to play an electrical connection role.

10. The manufacturing process of a wide bandgap semiconductor composite high voltage vertical power chip according to claim 9, characterized in that: Replace steps S5, S6, and S7 with steps S5-1 and S6-1; S5-1, using a carrier wafer for temporary bonding and grinding the back silicon substrate to 2-10 μm, and then bonding it at the wafer level to the side of the high voltage-resistant layer made of a wide bandgap thin layer material away from the high-resistance substrate; the carrier wafer is a silicon thin film layer that integrates silicon CMOS logic and a switch control unit; S6-1. Etch metal vias and isolation grooves in the silicon thin film layer. The hole wall of the metal via is covered with a dielectric isolation layer with a thickness of 10nm-800nm. The center of the metal via is filled with connecting metal. The bottom of the connecting metal contacts the ohmic contact (9) metal region of the wide bandgap semiconductor to play an electrical connection role.

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