An inverted LED chip resistant to thimble and its preparation method

Abstract

The present invention relates to the technical field of LEDs. The present invention discloses an anti-pin-through flip-chip LED chip and a preparation method thereof. The anti-pin-through flip-chip LED chip includes a substrate and an epitaxial layer stacked in sequence; a groove is provided on the epitaxial layer, an N-type electrode is provided in the groove, a current blocking layer and a transparent conductive layer are further provided on the epitaxial layer, a P-type electrode, a passivation layer and a pad are provided on the transparent conductive layer, and the pad includes a P-type pad and an N-type pad; an anti-pin-through layer in contact with the passivation layer is further included, the anti-pin-through layer is provided between the P-type pad and the N-type pad, and the anti-pin-through layer is composed of a plurality of metal layers arranged at a preset gap. Implementing the present invention can reduce the possibility of pin-through breaking the chip structure during the die bonding of the flip-chip LED chip, resulting in leakage, and the spaced arrangement of the metal layers in the pin protection also effectively avoids the leakage problem caused by the solder paste overflowing and connecting the P-type electrode and the N-type electrode.

Description

Technical Field

[0001] The present invention relates to the technical field of LEDs, and particularly relates to an anti-pin-poking flip-chip LED chip and a preparation method thereof. Background Art

[0002] Flip-chip LED chips have properties such as wire-free bonding and high current resistance, and are widely used in fields such as COB lighting, flexible light strips, backlighting, and displays. The encapsulation soldering and die bonding of flip-chip LED chips mainly transfer the chip to the substrate by means of a suction nozzle adsorbing the substrate and a pin poking the front of the chip, and then performing a reflow soldering operation. With the help of solder paste, the electrical connection between the pad and the substrate is achieved, and at the same time, the chip is fixed on the substrate.

[0003] Currently, the structure of a flip-chip LED chip basically includes a substrate 1, an epitaxial layer 2, a current blocking layer 3, a transparent conductive layer 4, a P-type electrode 5, an N-type electrode 6, a passivation layer 7, and pads 8. Among them, the epitaxial layer 2 includes an N-type semiconductor layer 21, a multi-quantum well layer 22, and a P-type semiconductor layer 23, and the pads 8 include a P-type pad 81 and an N-type pad 82, as Figure 1 shown. During the encapsulation and die bonding process of the flip-chip LED chip, the pin will poke the passivation layer 7 on the front of the LED chip, and the passivation layer 7 is mostly a brittle material and is extremely easy to be poked and broken by the pin, resulting in the surfaces of the underlying transparent conductive layer 4 and epitaxial layer 2 being easily damaged, causing leakage, and deteriorating the reliability of the flip-chip LED chip. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an anti-pin-poking flip-chip LED chip and a preparation method thereof, which are used to solve the problem that the pin pokes and breaks the chip structure during the encapsulation and die bonding of the flip-chip LED chip, reduce the possibility of leakage caused by chip damage, and effectively avoid the leakage problem caused by the solder paste overflowing and the P-type electrode and N-type electrode being connected.

[0005] To solve the above technical problem, in the first aspect of the present invention, an anti-pin-poking flip-chip LED chip is provided, including a substrate and an epitaxial layer stacked in sequence;

[0006] A groove is provided on the epitaxial layer, an N-type electrode is provided in the groove, a current blocking layer and a transparent conductive layer are further provided on the epitaxial layer, the transparent conductive layer covers the current blocking layer and exposes the groove, a P-type electrode, a passivation layer, and pads are provided on the transparent conductive layer, the passivation layer covers the P-type electrode and the groove, the pads include a P-type pad and an N-type pad, and the P-type pad and the N-type pad penetrate through the passivation layer and are electrically connected to the corresponding P-type electrode and N-type electrode;

[0007] The flip-chip LED chip with anti-pinching also includes an anti-pinching layer in contact with the passivation layer. The anti-pinching layer is disposed between the P-type pad and the N-type pad, and the anti-pinching layer is composed of a plurality of metal layers arranged at a preset gap.

[0008] As an improvement to the above solution, both the P-type electrode and the N-type electrode include an ohmic contact layer, a reflective layer, a cladding layer, a conductive layer, an etching stop layer, and an adhesion layer that are stacked in sequence. Among them,

[0009] The ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the ohmic contact layer is 5 Å to 100 Å;

[0010] The reflective layer includes at least one of an Al layer and an Ag layer, and the thickness of the reflective layer is 100 nm to 300 nm;

[0011] The cladding layer includes at least two of a Ti layer, a Ni layer, and a Pt layer, and the thickness of the cladding layer is 100 nm to 1000 nm;

[0012] The conductive layer includes at least one of an Au layer and a Cu layer, and the thickness of the conductive layer is 200 nm to 1500 nm;

[0013] The etching stop layer includes a Pt layer, and the thickness of the etching stop layer is 200 nm to 600 nm;

[0014] The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30 Å to 150 Å.

[0015] As an improvement to the above solution, the anti-pinching layer is disposed on the transparent conductive layer, and the passivation layer covers the anti-pinching layer.

[0016] As an improvement to the above solution, the anti-pinching layer includes an ohmic contact layer, a reflective layer, a cladding layer, a conductive layer, an etching stop layer, and an adhesion layer that are stacked in sequence. Among them,

[0017] The ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the ohmic contact layer is 5 Å to 100 Å;

[0018] The reflective layer includes at least one of an Al layer and an Ag layer, and the thickness of the reflective layer is 100 nm to 300 nm;

[0019] The cladding layer includes at least two of a Ti layer, a Ni layer, and a Pt layer, and the thickness of the cladding layer is 100 nm to 1000 nm;

[0020] The conductive layer includes at least one of an Au layer and a Cu layer, and the thickness of the conductive layer is 200 nm to 1500 nm;

[0021] The etching stop layer includes a Pt layer, and the thickness of the etching stop layer is 200 nm to 600 nm;

[0022] The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30 Å to 150 Å.

[0023] As an improvement to the above solution, the anti-pin layer is disposed on the passivation layer, and a protective layer is further disposed on the passivation layer. The protective layer covers the anti-pin layer, and the P-type pad and the N-type pad penetrate through the protective layer and the passivation layer and are electrically connected to the corresponding P-type electrode and N-type electrode.

[0024] As an improvement to the above solution, the anti-pin layer includes a contact layer, a buffer layer, and an adhesion layer stacked in sequence, wherein

[0025] The contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the contact layer is 30 Å to 500 Å;

[0026] The buffer layer includes at least one of an Au layer, an Al layer, and a Cu layer, and the thickness of the buffer layer is 200 nm to 1500 nm;

[0027] The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30 Å to 150 Å;

[0028] Alternatively, the anti-pin layer includes an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching stop layer, and an adhesion layer stacked in sequence, wherein

[0029] The ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the ohmic contact layer is 5 Å to 100 Å;

[0030] The reflective layer includes at least one of an Al layer and an Ag layer, and the thickness of the reflective layer is 100 nm to 300 nm;

[0031] The coating layer includes at least two of a Ti layer, a Ni layer, and a Pt layer, and the thickness of the coating layer is 100 nm to 1000 nm;

[0032] The conductive layer includes at least one of an Au layer and a Cu layer, and the thickness of the conductive layer is 200 nm to 1500 nm;

[0033] The etching stop layer includes a Pt layer, and the thickness of the etching stop layer is 200 nm to 600 nm;

[0034] The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30 Å to 150 Å.

[0035] As an improvement of the above solution, the preset gap between adjacent metal layers is L 1 , and the width of the metal layer is L 2 , satisfying: L 2 = 0.35L 1 ~ 10L 1 .

[0036] As an improvement of the above solution, the distance between the anti-ejector layer and the P-type pad is a 1 , and the distance between the anti-ejector layer and the N-type pad is a 2 , satisfying: a 1 = a 2 = 1.5L 1 ~ 33L 2 ;

[0037] The width of the anti-ejector layer is b; the width of the P-type pad or N-type pad is c, satisfying: b ≤ c

[0038] As an improvement of the above solution, the protective layer includes at least one of SiO 2 layer, Al 2 O 3 layer, and the thickness of the protective layer is 200 nm to 1000 nm

[0039] The second aspect of the present invention also provides a method for manufacturing the anti-ejector flip-chip LED chip, including:

[0040] Providing a substrate, preparing an epitaxial layer on the substrate, and etching a groove for setting an N-type electrode on the epitaxial layer

[0041] Preparing a current blocking layer and a transparent conductive layer on the epitaxial layer, so that the transparent conductive layer covers the current blocking layer and exposes the groove

[0042] Preparing a P-type electrode on the transparent conductive layer and an N-type electrode in the groove

[0043] Preparing a passivation layer on the transparent conductive layer

[0044] Preparing an anti-ejector layer on the transparent conductive layer or the passivation layer, so that the anti-ejector layer and the passivation layer are in contact

[0045] Etching the passivation layer until the P-type electrode and the N-type electrode are exposed to form a P-type through hole and an N-type through hole

[0046] Preparing a P-type pad and an N-type pad at the upper ends of the P-type through hole and the N-type through hole, and electrically connecting the P-type pad and the N-type pad to the corresponding P-type electrode and N-type electrode through the P-type through hole and the N-type through hole

[0047] Among them, the anti-pin layer is disposed between the P-type pad and the N-type pad, and the anti-pin layer is composed of a plurality of metal layers arranged at a preset gap.

[0048] Implementing the present invention has the following beneficial effects:

[0049] In the present invention, an anti-pin layer in contact with the passivation layer is provided on the flip-chip LED chip, which can play a buffering and isolating role, maintain the structural integrity of the flip-chip LED chip, and reduce the possibility of leakage caused by the pin piercing the chip structure during die bonding of the flip-chip LED chip package. In addition, the anti-pin layer can cooperate with the passivation layer to reduce the risk of chemical erosion, improve the electrical performance stability of the flip-chip LED chip, and increase the yield of the flip-chip LED chip.

[0050] Furthermore, by using a metal layer as the anti-pin layer and utilizing the ductility of the metal, a buffering effect can be achieved to prevent the pin from directly piercing the transparent conductive layer and the epitaxial layer. And by arranging the metal layers in a manner of a preset gap, it can be ensured that after the passivation layer is pierced by the pin, the solder pastes of the N-type pad and the P-type pad overflow and contact the anti-pin layer, the N-type pad and the P-type pad still remain in an open state, which will not cause chip short circuit. At the same time, it can also make the heat evenly distributed, reduce the occurrence of local overheating phenomenon, and improve the luminous brightness and uniformity. Description of the Drawings

[0051] Figure 1 : Schematic structural diagram of a flip-chip LED chip in the prior art;

[0052] Figure 2 : Schematic structural diagram of a flip-chip LED chip with an anti-pin provided in the first embodiment of the present invention;

[0053] Figure 3 : Schematic structural diagram of a flip-chip LED chip with an anti-pin provided in the second embodiment of the present invention;

[0054] Figure 4 : Schematic structural diagram of the anti-pin layer in the present invention;

[0055] Figure 5 : Top view of a flip-chip LED chip with an anti-pin provided in the first embodiment of the present invention;

[0056] Figure 6 : Top view of a flip-chip LED chip with an anti-pin provided in the second embodiment of the present invention.

[0057] Reference numerals: 1 - substrate; 2 - epitaxial layer; 21 - N-type semiconductor layer; 22 - multiple quantum well layer; 23 - P-type semiconductor layer; 3 - current blocking layer; 4 - transparent conductive layer; 5 - P-type electrode; 6 - N-type electrode; 7 - passivation layer; 8 - pad; 81 - P-type pad; 82 - N-type pad; 9 - anti-pin layer; 91 - metal layer; 10 - protective layer. Detailed implementation manners

[0058] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with specific embodiments.

[0059] To solve the above problems, a first aspect of the present invention provides an anti-pin flip-chip LED chip, as Figure 2 and Figure 3 shown, including a substrate 1 and an epitaxial layer 2 stacked in sequence; a groove is provided on the epitaxial layer 2, an N-type electrode 6 is provided in the groove, a current blocking layer 3 and a transparent conductive layer 4 are further provided on the epitaxial layer 2, the transparent conductive layer 4 covers the current blocking layer 3 and exposes the groove, a P-type electrode 5, a passivation layer 7 and a pad 8 are provided on the transparent conductive layer 4, the passivation layer 7 covers the P-type electrode 5 and the groove, the pad 8 includes a P-type pad 81 and an N-type pad 82, the P-type pad 81 and the N-type pad 82 penetrate through the passivation layer 7 and are electrically connected to the corresponding P-type electrode 5 and N-type electrode 6, and the anti-pin flip-chip LED chip further includes an anti-pin layer 9 in contact with the passivation layer 7.

[0060] In the present invention, an anti-pin layer 9 in contact with the passivation layer 7 is provided on the flip-chip LED chip, which can play a buffering and isolating role, maintain the structural integrity of the flip-chip LED chip, and reduce the possibility of the pin piercing the chip structure during the die bonding of the flip-chip LED chip packaging, resulting in leakage. In addition, the anti-pin layer 9 can cooperate with the passivation layer 7 to reduce the risk of chemical erosion and ensure the stable electrical performance of the flip-chip LED chip.

[0061] Specifically, the epitaxial layer 2 includes an N-type semiconductor layer 21, a multiple quantum well layer 22 and a P-type semiconductor layer 23 stacked in sequence, and the groove extends from the P-type semiconductor layer 23 to the N-type semiconductor layer 21, so that the N-type electrode 6 is provided on the N-type semiconductor layer 21. The current blocking layer 3 and the transparent conductive layer 4 are provided on the P-type semiconductor layer 23, and the transparent conductive layer 4 covers the current blocking layer 3 and exposes the groove.

[0062] It can be understood that the N-type semiconductor layer 21 can be an N-type GaN layer, an N-type AlGaN layer, an N-type GaAs layer, but is not limited thereto; the multiple quantum well layer 22 can be an InGaN / GaN type multiple quantum well layer, an InGaN / AlGaN type multiple quantum well layer, an AlGaN / AlGaN type multiple quantum well layer, but is not limited thereto; the P-type semiconductor layer 23 can be a P-type GaN layer, a P-type AlGaN layer, a P-type GaAs layer, but is not limited thereto; the current blocking layer 3 includes but is not limited to SiO 2 layer; the transparent conductive layer 4 includes but is not limited to an ITO layer.

[0063] Optionally, the material of the passivation layer 7 is SiO 2 , Ti 3 O 5 at least one of; the thickness of the passivation layer 7 is 1 μm to 6 μm; more preferably, the passivation layer 7 is a DBR structure, and the passivation layer 7 is a SiO 2 layer and a Ti 3 O 5 layer repeatedly stacked to obtain a multi-layer structure, which can not only play an insulating and protective role, but also serve as a high reflector to allow more light energy to penetrate from the chip surface. In some specific and preferred embodiments, the thickness of each SiO 2 layer is 1 / 4 optical thickness to 1 / 3 optical thickness, and the thickness of each Ti 3 O 5 layer is 1 / 4 optical thickness to 1 / 3 optical thickness.

[0064] Among them, the P-type electrode 5 and the N-type electrode 6 are both metal electrodes, which can be a single-layer structure or a multi-layer structure. Preferably, the raw material compositions of the P-type electrode 5 and the N-type electrode 6 are the same and both are multi-layer structures. Specifically, the P-type electrode 5 and the N-type electrode 6 both include an ohmic contact layer, a reflective layer, a cladding layer, a conductive layer, an etch stop layer, and an adhesion layer stacked in sequence. An ohmic contact with low resistance is formed between the ohmic contact layer and the semiconductor layer to ensure that current can be efficiently conducted between the semiconductor and the electrode. The reflective layer disposed above it can not only reflect light back to the light-emitting surface, but also prevent the erosion and oxidation of the ohmic contact layer by the external environment to a certain extent, thereby prolonging the service life of the ohmic contact layer and maintaining its good ohmic contact performance. The conductive layer is the key layer responsible for transmitting current in the electrode, ensuring that current can be efficiently transmitted in the electrode, and the cladding layer disposed between the reflective layer and the conductive layer plays a role of transition and protection, preventing the metals in the reflective layer and the conductive layer from directly contacting and diffusing or reacting with each other, thereby protecting the performance of the reflective layer and the conductive layer and enabling them to work independently. Finally, an etch stop layer and an adhesion layer are disposed on the conductive layer to protect the conductive layer and enhance the adhesion of the protective layer to the electrode.

[0065] Furthermore, the ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, which can effectively reduce the contact resistance between the electrode and the semiconductor, reduce the scattering and energy loss of carriers at the interface, and have good contact performance with the transparent conductive layer 4 and the N-type semiconductor layer 21. The reflective layer includes at least one of an Al layer and an Ag layer, which not only has good reflective performance but also excellent electrical and thermal conductivity. The coating layer includes at least two of a Ti layer, a Ni layer, and a Pt layer, which can protect the internal reflective layer, prevent the metal atoms in the reflective layer from migrating under the action of an electric field or other factors, and avoid problems such as electrical anomalies and short circuits caused by metal migration, thereby improving the stability and service life of the electrode and the entire device; more preferably, the coating layer is a periodic structure with the number of periods being 2 to 5. While enhancing the mechanical properties of the coating layer, it can realize the regulation of functions such as reflection, absorption, or scattering of light with specific wavelengths, and further optimize the optical performance of the chip. The conductive layer includes at least one of an Au layer and a Cu layer, which has a low resistivity, can effectively transmit current, reduce energy loss during the conduction process, and ensure that the electrode can still stably transmit current under high-current working conditions. The etching stop layer includes a Pt layer; the adhesion layer includes a Ti layer.

[0066] In some embodiments, the thickness of the ohmic contact layer is 5 Å to 100 Å; the thickness of the reflective layer is 100 nm to 300 nm; the thickness of the coating layer is 100 nm to 1000 nm; the thickness of the conductive layer is 200 nm to 1500 nm; the thickness of the etching stop layer is 200 nm to 600 nm; the thickness of the adhesion layer is 30 Å to 150 Å.

[0067] Furthermore, the anti-pin layer 9 is disposed between the P-type pad 81 and the N-type pad 82, and the anti-pin layer 9 is composed of a plurality of metal layers 91 arranged at a preset gap, as Figures 4 to 6 shown. Using the metal layer 91 as the anti-pin layer 9, with the ductility of the metal, it plays a buffering role to prevent the pin from directly piercing the transparent conductive layer 4 and the epitaxial layer 2. And by arranging the metal layers 91 in a gap arrangement, after the passivation layer 7 is pierced by the pin and the solder paste of the N-type pad 82 and the P-type pad 81 overflows and contacts the anti-pin layer 9, it can also ensure that the N-type pad 82 and the P-type pad 81 remain in an open state, will not cause a short circuit in the chip, and at the same time can make the heat evenly distributed and reduce the occurrence of local overheating.

[0068] The length and width of the anti-pin layer 9 need to be determined according to the size of the used pin and the possible contact area of the pin on the flip-chip LED chip. Preferably, please refer to Figure 4 , and the gap between adjacent metal layers 91 is L1 The width of the metal layer 91 is L 2 satisfying L 2 = 0.35L 1 ~ 10L 1 so that the anti - thimble layer 9 has a good protection effect on the chip, preventing the thimble from contacting the sensitive area of the chip during operation, and effectively avoiding short - circuits between adjacent metal layers 91, optimizing the light - emitting path, and improving the light - emitting uniformity and efficiency of the flip - chip. If L 2 <0.35L 1 in the entire anti - thimble layer 9, the metal layer 91 is relatively less and discontinuous. The light - shielding of the anti - thimble layer 9 is reduced, but at this time, the structure of the anti - thimble layer 9 is relatively loose, and the metal layer 91 is prone to displacement or deformation, affecting the protection effect of the anti - thimble layer 9, and even causing leakage. Moreover, it will increase the opacity of the anti - thimble layer 9, increasing the probability of light scattering and absorption in the anti - thimble layer 9, thereby reducing the light - emitting efficiency and optical uniformity of the chip; if L 2 >10L 1 the anti - thimble effect is good, but at this time, the width of the metal layer 91 is relatively wide, causing a certain degree of light - shielding, thereby reducing the light - emitting efficiency. At the same time, the stress between adjacent metal layers 91 may affect each other. During long - term use, the metal layer 91 is prone to problems such as fatigue and cracks, and it may also cause heat to accumulate locally and cannot be effectively dissipated to the surrounding environment, also leading to the problem of chip overheating.

[0069] In some specific embodiments, L 1 = 3μm to 15μm, for example, 3μm, 5μm, 7μm, 9μm, 11μm, 13μm, 15μm, but not limited thereto; L 2 = 5μm to 30μm, for example, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, but not limited thereto.

[0070] Furthermore, please refer to Figure 5 and Figure 6 the distance between the anti - thimble layer 9 and the P - type pad 81 is a 1 the distance between the anti - thimble layer 9 and the N - type pad 82 is a 2 satisfying a 1 = a 2 = 1.5L 2 ~ 33L 2 . If a 1 = a 2 <1.5L 2, the distance between the anti-pin layer 9 and the pad 8 is short, the area of the anti-pin layer 9 is large, and the anti-pin effect is good, but the light-shielding area increases. When the chip is subjected to external forces, stress may concentrate locally, easily causing mechanical damages such as cracks and fractures in the anti-pin layer 9 or the pad 8. Moreover, the anti-pin layer 9 will have a strong reflection and absorption effect on the light near the pad 8, thereby reducing the light flux emitted from the front of the chip; if a 1 =a 2 >33L 2 , the distance between the anti-pin layer 9 and the pad 8 is long, the area of the anti-pin layer 9 is small, the light-shielding area is reduced, but the anti-pin effect is reduced. Relative displacement or deformation is likely to occur between the anti-pin layer 9 and the pad 8, and then leakage occurs. Moreover, heat may be unevenly distributed in the anti-pin layer 9 during the conduction process, which is also likely to cause local overheating.

[0071] In some specific embodiments, a 1 =a 2 = 20μm to 100μm, exemplarily 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, but not limited thereto; b≥50μm.

[0072] Furthermore, the width of the anti-pin layer 9 is b, and the width of the P-type pad 81 or the N-type pad 82 is c, satisfying b≤c. At this time, the light-shielding area of the anti-pin layer 9 is small, and it can play a better reflection role, resulting in improved luminous efficiency. However, correspondingly, the anti-pin effect will be weakened, and then leakage occurs. In some specific embodiments, 50μm≤b≤c.

[0073] Specifically, the metal layer 91 in the anti-pin layer 9 can be a single-layer structure or a multi-layer structure. The raw material composition of the anti-pin layer 9 can be the same as that of the P-type electrode 5 and the N-type electrode 6, or can be different from that of the P-type electrode 5 and the N-type electrode 6.

[0074] In some specific and preferred embodiments, as Figure 5 shown, the anti-pin layer 9 is disposed on the transparent conductive layer 4, and the passivation layer 7 covers the anti-pin layer 9. At this time, the anti-pin layer 9 can directly protect the underlying transparent conductive layer 4 from pin damage. Covering the passivation layer 7 thereon can further assist in blocking the erosion of external moisture and impurities to the internal structure. If the anti-pin layer 9 is directly in contact with the outside world, it may be worn and corroded during long-term use and cause failure, and the transparent conductive layer 4 will be exposed to a harsh environment relatively quickly, reducing the life of the flip-chip LED chip. Moreover, the formed layer structure is simple, which simplifies the production difficulty to a certain extent.

[0075] More preferably, the material composition of the anti-pin layer 9 is the same as that of the P-type electrode 5 and the N-type electrode 6. That is, the anti-pin layer 9 is a multi-layer structure, including an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching barrier layer, and an adhesion layer stacked in sequence. Among them, the ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer; the reflective layer includes at least one of an Al layer and an Ag layer; the coating layer includes at least two of a Ti layer, a Ni layer, and a Pt layer. More preferably, the coating layer is a periodic structure with a period number of 2 to 5; the conductive layer includes at least one of an Au layer and a Cu layer; the etching barrier layer includes a Pt layer; the adhesion layer includes a Ti layer. At this time, the passivation layer 7 is in direct contact with the pin, and the anti-pin layer 9 has good adhesion on the transparent conductive layer 4. The overall structure and performance are consistent. When facing the pin operation, it can more effectively resist the pressure of the pin, reduce the risk of being damaged or punctured, protect the circuit structure and functional integrity inside the chip, and combine with the metal ductility in the anti-pin layer 9 to prevent the flip-chip LED chip from cracking under the action of the pin, thereby playing a role in protecting the layer structure below the anti-pin layer 9 and avoiding leakage. It can be understood that the anti-pin layer 9 and the P-type electrode 5 and the N-type electrode 6 can be completed in the same process step.

[0076] Optionally, the thickness of the ohmic contact layer is 5 Å to 100 Å; the thickness of the reflective layer is 100 nm to 300 nm; the thickness of the coating layer is 100 nm to 1000 nm; the thickness of the conductive layer is 200 nm to 1500 nm; the thickness of the etching barrier layer is 200 nm to 600 nm; the thickness of the adhesion layer is 30 Å to 150 Å.

[0077] In some other specific and preferred embodiments, as Figure 6 shown, the anti-pin layer 9 is disposed on the passivation layer 7, and a protective layer 10 is further disposed on the passivation layer 7. The protective layer 10 covers the anti-pin layer 9, and the P-type pad 81 and the N-type pad 82 penetrate through the protective layer 10 and the passivation layer 7 and are electrically connected to the corresponding P-type electrode 5 and N-type electrode 6. At this time, the passivation layer 7 provides basic protection for the transparent conductive layer 4 to block chemical erosion, while the anti-pin layer 9 specifically prevents physical damage caused by the pin operation. The outermost protective layer 10 further isolates external mechanical friction and chemical contamination. The multi-layer protection works together to provide a more durable and comprehensive protection effect, reducing the probability of chip failure due to various damages. In addition, the anti-pin layer 9 is located on the passivation layer 7 and will not cause light-shielding problems, so the light-emitting efficiency of the flip-chip LED chip will be correspondingly improved. However, compared with the anti-pin layer 9 disposed on the transparent conductive layer 4, the passivation layer 7 is relatively prone to breakage, resulting in damage to the transparent conductive layer 4 and the epitaxial layer 2, thereby increasing the leakage rate of the flip-chip LED chip.

[0078] Optionally, the raw material composition of the anti-pin layer 9 is different from that of the P-type electrode 5 and the N-type electrode 6. The anti-pin layer 9 includes a contact layer, a buffer layer, and an adhesion layer stacked in sequence. At this time, the adhesion layer contacts the pin through the protective layer 10, and can utilize its good adhesion characteristics to ensure close fitting with the pin, and perform preliminary buffering by its own elasticity and adhesiveness to protect the buffer layer and the contact layer, preventing delamination, peeling and other phenomena between the layers. Subsequently, the applied force is further dispersed through the buffer layer and then transmitted to the contact layer, effectively reducing the external force on the passivation layer 7, and having a good protection effect on the flip-chip LED chip.

[0079] Among them, the contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, which has strong adhesion on the passivation layer 7 and exhibits certain mechanical strength, playing a role in protecting the passivation layer 7; the buffer layer includes at least one of an Au layer, an Al layer, and a Cu layer, which can effectively absorb and disperse pressure; the adhesion layer includes a Ti layer, which enhances the adhesion between the protective layer 10 and the anti-pin layer 9, and also has good corrosion resistance, and can prevent the erosion of external chemical substances on the anti-pin layer 9 to a certain extent, ensuring the long-term stability of the anti-pin layer 9.

[0080] Furthermore, the thickness of the contact layer is 30 Å to 500 Å; the thickness of the buffer layer is 200 nm to 1500 nm; the thickness of the adhesion layer is 30 Å to 150 Å.

[0081] Optionally, the raw material composition of the anti-pin layer 9 is the same as that of the P-type electrode 5 and the N-type electrode 6. At this time, the structure of the anti-pin layer 9 contains a reflective layer, which can form ODR reflection with the underlying passivation layer 7, thereby further improving the light emission efficiency of the flip-chip LED chip.

[0082] Preferably, the protective layer 10 includes SiO 2 layer, Al 2 O 3 layer, etc. At least one of them has excellent wear resistance, hardness and insulation, can effectively resist the acting force and wear of the pin, and has high transparency and will not affect the emission of light inside the chip.

[0083] Further, the thickness of the protective layer 10 is 200 nm to 1000 nm, and exemplary values are 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, but not limited thereto.

[0084] Regarding the setting of the anti-pin layer 9, there are various implementation manners, for example Figure 2In the first embodiment provided, the anti-pin layer 9 is disposed on the transparent conductive layer 4, and the passivation layer 7 covers the anti-pin layer 9; or Figure 3 In the second embodiment provided, the anti-pin layer 9 is disposed on the passivation layer 7, and a protective layer 10 is further disposed on the passivation layer 7. The protective layer 10 covers the anti-pin layer 9. The P-type pad 81 and the N-type pad 82 are electrically connected to the corresponding P-type electrode 5 and N-type electrode 6 after passing through the protective layer 10 and the passivation layer 7.

[0085] The present invention will be further described below with specific embodiments:

[0086] First Embodiment

[0087] This embodiment provides an anti-pin flip-chip LED chip, as Figure 2 and Figure 5 shown, including a substrate 1 and an epitaxial layer 2 stacked in sequence;

[0088] A groove is provided on the epitaxial layer 2, an N-type electrode 6 is disposed in the groove, a current blocking layer 3 and a transparent conductive layer 4 are further disposed on the epitaxial layer 2. The transparent conductive layer 4 covers the current blocking layer 3 and exposes the groove. A P-type electrode 5, a passivation layer 7 and pads 8 are disposed on the transparent conductive layer 4. The passivation layer 7 covers the P-type electrode 5 and the groove. The pads 8 include a P-type pad 81 and an N-type pad 82. The P-type pad 81 and the N-type pad 82 are electrically connected to the corresponding P-type electrode 5 and N-type electrode 6 after passing through the passivation layer 7.

[0089] Both the P-type electrode 5 and the N-type electrode 6 include an ohmic contact layer, a reflective layer, a cladding layer, a conductive layer, an etch stop layer and an adhesion layer stacked in sequence. Among them, the ohmic contact layer is a Cr layer, the reflective layer is an Al layer, the cladding layer is a Ti layer / Pt layer / Ti layer / Pt layer, the conductive layer is an Au layer, the etch stop layer is a Pt layer, and the adhesion layer is a Ti layer. That is, both the P-type electrode 5 and the N-type electrode 6 are Cr layer / Al layer / Ti layer / Pt layer / Ti layer / Pt layer / Au layer / Pt layer / Ti layer stacked in sequence from bottom to top, with thicknesses of 30 Å / 100 nm / 100 nm / 200 nm / 100 nm / 200 nm / 500 nm / 300 nm / 50 Å respectively.

[0090] An anti-pin layer 9 is further disposed on the transparent conductive layer 4. The anti-pin layer 9 is disposed between the P-type pad 81 and the N-type pad 82. The passivation layer 7 covers the anti-pin layer 9. The anti-pin layer 9 is composed of a plurality of metal layers 91 arranged at a preset gap. Among them, the gap between adjacent metal layers 91 is L 1 , the width of the metal layer 91 is L 2 , L 1= 7μm, L 2 = 10μm; The distance between the anti - thimble layer 9 and the P - type pad 81 is a 1 and the distance between the anti - thimble layer 9 and the N - type pad 82 is a 2 , a 1 = a 2 = 20μm; The width of the anti - thimble layer 9 is b, and the width of the P - type pad 81 or N - type pad 82 is c, and b = c.

[0091] The structure of the anti - thimble layer 9 is the same as that of the P - type electrode 5 and the N - type electrode 6, including an ohmic contact layer, a reflective layer, a cladding layer, a conductive layer, an etch - stop layer, and an adhesion layer stacked in sequence. Among them, the ohmic contact layer is a Cr layer, the reflective layer is an Al layer, the cladding layer is a Ti layer / Pt layer / Ti layer / Pt layer, the conductive layer is an Au layer, the etch - stop layer is a Pt layer, and the adhesion layer is a Ti layer. That is, the anti - thimble layer 9 is a Cr layer / Al layer / Ti layer / Pt layer / Ti layer / Pt layer / Au layer / Pt layer / Ti layer stacked from bottom to top, with thicknesses of 30 Å / 100 nm / 100 nm / 200 nm / 100 nm / 200 nm / 500 nm / 300 nm / 50 Å respectively.

[0092] Correspondingly, a method for manufacturing a flip - chip LED chip with an anti - thimble includes:

[0093] (1) Provide a substrate 1, prepare an epitaxial layer 2 on the substrate 1, and etch a groove for setting the N - type electrode 6 on the epitaxial layer 2;

[0094] Preferably, the substrate 1 can be a sapphire substrate, a GaAs substrate, a silicon substrate, or a SiC substrate, but is not limited thereto.

[0095] Further, the epitaxial layer 2 includes an N - type semiconductor layer 21, a multi - quantum well layer 22, and a P - type semiconductor layer 23 arranged in sequence, and etch from the surface of the P - type semiconductor layer 23 downward until the N - type semiconductor layer 21 is exposed to form a groove. The etching includes but is not limited to dry etching.

[0096] (2) Prepare a current - blocking layer 3 and a transparent conductive layer 4 on the epitaxial layer 2, so that the transparent conductive layer 4 covers the current - blocking layer 3 and exposes the groove;

[0097] Specifically, setting the current - blocking layer 3 and the transparent conductive layer 4 on the P - type semiconductor layer 23 includes:

[0098] (21) Deposit the material of the current - blocking layer 3 on the P - type semiconductor layer 23, and then through a photolithography process and an etching process, prepare the current - blocking layer 3 and expose the groove;

[0099] Optionally, the thickness of the current blocking layer 3 is determined according to the actual situation, and the present invention does not make specific limitations thereto. The material of the current blocking layer 3 is deposited by a plasma enhanced chemical vapor deposition (PECVD) process, and the etching process includes but is not limited to wet etching.

[0100] (22) Deposit the material of the transparent conductive layer 4 on the P-type semiconductor layer 23 and the current blocking layer 3, and then prepare the transparent conductive layer 4 through a photolithography process and an etching process, and expose the groove.

[0101] Optionally, the material of the current blocking layer 3 is deposited by a PECVD process, and the etching process includes but is not limited to wet etching.

[0102] (3) Prepare a P-type electrode 5 on the transparent conductive layer 4, and prepare an N-type electrode 6 in the groove.

[0103] Optionally, the P-type electrode 5 and the N-type electrode 6 can be prepared by a yellow light process and a coating process.

[0104] It can be understood that the process of forming the groove can also be carried out in this step, that is, etching from the surface of the transparent conductive layer 4 downward until the N-type semiconductor layer 21 is exposed to form a groove, and then a P-type electrode 5 and an N-type electrode 6 are respectively arranged on the transparent conductive layer 4 and in the formed groove. The P-type electrode 5 and the N-type electrode 6 can be formed by the same process or can be formed in two steps by two processes. The present invention is not limited thereto, and any implementation form of the corresponding structure is within the protection scope of the present invention.

[0105] (4) Prepare an anti-pin layer 9 on the transparent conductive layer 4.

[0106] Preferably, the anti-pin layer 9 is located between the P-type electrode 5 and the N-type electrode 6. The anti-pin layer 9 is composed of a plurality of metal layers 91 arranged at a preset gap, and can be specifically prepared by a yellow light process and a coating process.

[0107] (5) Prepare a passivation layer 7 on the transparent conductive layer 4.

[0108] Specifically, deposit the material of the passivation layer 7 on the transparent conductive layer 4 and the anti-pin layer 9 to prepare a passivation layer 7 covering the anti-pin layer 9. It can be understood that the deposition process of the passivation layer 7 includes but is not limited to physical vapor deposition (PVD).

[0109] (6) Etch the passivation layer 7 until the P-type electrode 5 and the N-type electrode 6 are exposed to form a P-type through hole and an N-type through hole.

[0110] It can be understood that the P-type through-holes and N-type through-holes can be prepared by lithography and etching processes, where the etching process includes but is not limited to dry etching.

[0111] (7) Prepare a P-type pad 81 and an N-type pad 82 at the P-type through-hole and N-type through-hole, and electrically connect the P-type pad 81 and the N-type pad 82 to the corresponding P-type electrode 5 and N-type electrode 6 through the P-type through-hole and N-type through-hole.

[0112] Specifically, prepare the P-type pad 81 and the N-type pad 82 on the passivation layer 7, that is, deposit the materials of the P-type pad 81 and the N-type pad 82 at the corresponding positions of the P-type through-hole and the N-type through-hole on the protective layer 10 to form the P-type pad 81 and the N-type pad 82, preferably prepared by yellow light process and coating process.

[0113] Second Embodiment

[0114] This embodiment provides an anti-ejector flip-chip LED chip, as Figure 3 and Figure 6 shown, including a substrate 1 and an epitaxial layer 2 stacked in sequence;

[0115] A groove is provided on the epitaxial layer 2, an N-type electrode 6 is provided in the groove, a current blocking layer 3 and a transparent conductive layer 4 are further provided on the epitaxial layer 2, the transparent conductive layer 4 covers the current blocking layer 3 and exposes the groove, a P-type electrode 5, a passivation layer 7 and a pad 8 are provided on the transparent conductive layer 4, the passivation layer 7 covers the P-type electrode 5 and the groove, and the pad 8 includes a P-type pad 81 and an N-type pad 82.

[0116] Both the P-type electrode 5 and the N-type electrode 6 include an ohmic contact layer, a reflective layer, a cladding layer, a conductive layer, an etching stop layer and an adhesion layer stacked in sequence, where the ohmic contact layer is a Cr layer, the reflective layer is an Al layer, the cladding layer is a Ti layer / Pt layer / Ti layer / Pt layer, the conductive layer is an Au layer, the etching stop layer is a Pt layer, and the adhesion layer is a Ti layer, that is, both the P-type electrode 5 and the N-type electrode 6 are Cr layer / Al layer / Ti layer / Pt layer / Ti layer / Pt layer / Au layer / Pt layer / Ti layer stacked from bottom to top, with thicknesses of 30 Å / 100 nm / 100 nm / 200 nm / 100 nm / 200 nm / 500 nm / 300 nm / 50 Å respectively.

[0117] A thimble-proof layer 9 and a protective layer 10 are provided on the passivation layer 7. The thimble-proof layer 9 is disposed between the P-type pad 81 and the N-type pad 82. The protective layer 10 covers the thimble-proof layer 9. The P-type pad 81 and the N-type pad 82 penetrate through the protective layer 10 and the passivation layer 7 and are electrically connected to the corresponding P-type electrode 5 and N-type electrode 6. The thimble-proof layer 9 is composed of a plurality of metal layers 91 arranged at a preset gap. Among them, the gap between adjacent metal layers 91 is L 1 , and the width of the metal layer 91 is L 2 , L 1 = 7μm, L 2 = 10μm; the distance between the thimble-proof layer 9 and the P-type pad 81 is a 1 , and the distance between the thimble-proof layer 9 and the N-type pad 82 is a 2 , a 1 = a 2 = 20μm; the width of the thimble-proof layer 9 is b, and the width of the P-type pad 81 or the N-type pad 82 is c, and b = c.

[0118] The structure of the thimble-proof layer 9 is different from that of the P-type electrode 5 and the N-type electrode 6, and includes a contact layer, a buffer layer, and an adhesion layer stacked in sequence. Among them, the contact layer is a Cr layer, the buffer layer is an Al layer / Cu layer / Au layer, and the adhesion layer is a Ti layer. That is, the thimble-proof layer 9 is a Cr layer / Al layer / Cu layer / Au layer / Ti layer stacked on the passivation layer 7 in sequence, and the thicknesses are 50Å / 200nm / 300nm / 300nm / 50Å respectively.

[0119] Correspondingly, a preparation method for the flip-chip LED chip with a thimble-proof structure includes:

[0120] (1) Provide a substrate 1, prepare an epitaxial layer 2 on the substrate 1, and etch a groove for setting the N-type electrode 6 on the epitaxial layer 2;

[0121] Preferably, the substrate 1 can be a sapphire substrate, a GaAs substrate, a silicon substrate, or a SiC substrate, but is not limited thereto.

[0122] Further, the epitaxial layer 2 includes an N-type semiconductor layer 21, a multi-quantum well layer 22, and a P-type semiconductor layer 23 arranged in sequence, and etch downward from the surface of the P-type semiconductor layer 23 until the N-type semiconductor layer 21 is exposed to form a groove. The etching includes but is not limited to dry etching.

[0123] (2) Prepare a current blocking layer 3 and a transparent conductive layer 4 on the epitaxial layer 2, so that the transparent conductive layer 4 covers the current blocking layer 3 and exposes the groove;

[0124] Specifically, a current blocking layer 3 and a transparent conductive layer 4 are disposed on the P-type semiconductor layer 23, including:

[0125] (21) Deposit the material of the current blocking layer 3 on the P-type semiconductor layer 23, and then, through a photolithography process and an etching process, prepare the current blocking layer 3 and expose the groove;

[0126] Optionally, the thickness of the current blocking layer 3 is determined according to actual conditions, and the present invention does not make specific limitations thereto. The material of the current blocking layer 3 is deposited by a PECVD process, and the etching process includes but is not limited to wet etching.

[0127] (22) Deposit the material of the transparent conductive layer 4 on the P-type semiconductor layer 23 and the current blocking layer 3, and then, through a photolithography process and an etching process, prepare the transparent conductive layer 4 and expose the groove;

[0128] Optionally, the material of the current blocking layer 3 is deposited by a PECVD process, and the etching process includes but is not limited to wet etching.

[0129] (3) Prepare a P-type electrode 5 on the transparent conductive layer 4 and an N-type electrode 6 in the groove;

[0130] Optionally, the P-type electrode 5 and the N-type electrode 6 can be prepared by a yellow light process and a coating process.

[0131] It can be understood that the process of forming the groove can also be carried out in this step, that is, etching downward from the surface of the transparent conductive layer 4 until the N-type semiconductor layer 21 is exposed to form a groove, and then a P-type electrode 5 and an N-type electrode 6 are respectively disposed on the transparent conductive layer 4 and in the formed groove. The P-type electrode 5 and the N-type electrode 6 can be formed by the same process or can be formed in two steps by two processes. The present invention is not limited thereto, and any corresponding implementation form of the structure is within the protection scope of the present invention.

[0132] (4) Prepare a passivation layer 7 on the transparent conductive layer 4;

[0133] Specifically, deposit the material of the passivation layer 7 on the transparent conductive layer 4 to prepare the passivation layer 7. It can be understood that the deposition process of the passivation layer 7 includes but is not limited to PVD.

[0134] (5) Prepare an anti-pin layer 9 and a protective layer 10 on the passivation layer 7;

[0135] Specifically include:

[0136] (51) Prepare an anti-pin layer 9 on the passivation layer 7;

[0137] Preferably, the anti-pin layer 9 is located between the P-type electrode 5 and the N-type electrode 6. The anti-pin layer 9 is composed of a plurality of metal layers 91 arranged at a preset gap, and can be specifically prepared by a yellow light process and a coating process.

[0138] (52) Deposit a protective layer 10 on the passivation layer 7 and the anti-pin layer 9;

[0139] Specifically, deposit the material of the protective layer 10 on the passivation layer 7 and the anti-pin layer 9, and the deposition process includes but is not limited to PECVD.

[0140] (6) Etch the passivation layer 7 and the anti-pin layer 9 until the P-type electrode 5 and the N-type electrode 6 are exposed to form a P-type through hole and an N-type through hole;

[0141] Preferably, the P-type through hole and the N-type through hole can be prepared by a photolithography process and an etching process, wherein the etching process includes but is not limited to dry etching.

[0142] (7) Prepare a P-type pad 81 and an N-type pad 82 at the P-type through hole and the N-type through hole, and electrically connect the P-type pad 81 and the N-type pad 82 to the corresponding P-type electrode 5 and N-type electrode 6 through the P-type through hole and the N-type through hole.

[0143] Specifically, prepare the P-type pad 81 and the N-type pad 82 on the protective layer 10, that is, deposit the materials of the P-type pad 81 and the N-type pad 82 at the corresponding positions of the P-type through hole and the N-type through hole on the protective layer 10 to form the P-type pad 81 and the N-type pad 82, preferably prepared by a yellow light process and a coating process.

[0144] Third Embodiment

[0145] This embodiment provides an anti-pin flip-chip LED chip, which is basically the same as the first embodiment, except that:

[0146] The gap between adjacent metal layers 91 is L 1 , the width of the metal layer 91 is L 2 , L 1 = 7μm, L 2 = 15μm.

[0147] Fourth Embodiment

[0148] This embodiment provides an anti-pin flip-chip LED chip, which is basically the same as the first embodiment, except that:

[0149] The gap between adjacent metal layers 91 is L 1 , the width of the metal layer 91 is L 2 , L1 = 12 μm, L 2 = 10 μm.

[0150] The fifth embodiment

[0151] This embodiment provides an anti - thimble flip - chip LED chip, which is basically the same as the first embodiment, except that:

[0152] The distance between the anti - thimble layer 9 and the P - type pad 81 is a 1 and the distance between the anti - thimble layer 9 and the N - type pad 82 is a 2 , a 1 = a 2 = 40 μm.

[0153] The sixth embodiment

[0154] This embodiment provides an anti - thimble flip - chip LED chip, which is basically the same as the first embodiment, except that:

[0155] The width of the anti - thimble layer 9 is b, the width of the P - type pad 81 or the N - type pad 82 is c, and c - b = 30 μm.

[0156] The seventh embodiment

[0157] This embodiment provides an anti - thimble flip - chip LED chip, which is basically the same as the second embodiment, except that:

[0158] The structure of the anti - thimble layer 9 is the same as that of the P - type electrode 5 and the N - type electrode 6. The anti - thimble layer 9 includes an ohmic contact layer, a reflective layer, a cladding layer, a conductive layer, an etching barrier layer, and an adhesion layer stacked in sequence. Among them, the ohmic contact layer is a Cr layer, the reflective layer is an Al layer, the cladding layer is a Ti layer / Pt layer / Ti layer / Pt layer, the conductive layer is an Au layer, the etching barrier layer is a / Pt layer, and the adhesion layer is a Ti layer. That is, the anti - thimble layer 9 is a Cr layer / Al layer / Ti layer / Pt layer / Ti layer / Pt layer / Au layer / Pt layer / Ti layer stacked from bottom to top, with thicknesses of 30 Å / 100 nm / 100 nm / 200 nm / 100 nm / 200 nm / 500 nm / 300 nm / 50 Å respectively.

[0159] The first comparative example

[0160] This comparative example provides an anti - thimble flip - chip LED chip, which is basically the same as the first embodiment, except that:

[0161] The flip - chip LED chip does not contain the anti - thimble layer 9, and the structure is as Figure 1 shown.

[0162] Performance test

[0163] For the flip-chip LED chips with anti-ejector pins obtained in the examples and comparative examples, the leakage rate and luminous efficiency were tested. The test results are shown in Table 1 below, where the luminous efficiency was calculated based on the first comparative example.

[0164] Table 1 Performance test results of examples and comparative examples

[0165]

[0166] As can be seen from the above results, setting an anti-ejector pin layer in contact with the passivation layer on the flip-chip LED chip can play a buffering and isolating role, improve its luminous efficiency, and reduce the possibility of leakage caused by the ejector pin piercing the chip structure during die bonding of the flip-chip LED chip package. In addition, if the anti-ejector pin layer is composed of a plurality of metal layers arranged at a preset gap, the leakage rate of the flip-chip LED chip can be further reduced.

[0167] The above-disclosed is only a preferred embodiment of the present invention, and of course it cannot be used to limit the scope of the rights of the present invention. Therefore, equivalent changes made according to the claims of the present invention still fall within the scope covered by the present invention.

Claims

1. A flip-chip LED chip with an anti-ejection feature, characterized in that: comprising a substrate and an epitaxial layer stacked in sequence; The epitaxial layer is provided with a groove, an N-type electrode is provided in the groove, a current blocking layer and a transparent conductive layer are further provided on the epitaxial layer, the transparent conductive layer covers the current blocking layer and exposes the groove, a P-type electrode, a passivation layer and a pad are provided on the transparent conductive layer, the passivation layer covers the P-type electrode and the groove, the pad includes a P-type pad and an N-type pad, the P-type pad and the N-type pad penetrate the passivation layer and are electrically connected to the corresponding P-type electrode and N-type electrode; The anti-push-pin flip-chip LED chip further comprises an anti-push-pin layer in contact with the passivation layer, the anti-push-pin layer is arranged between the P-type pad and the N-type pad, and the anti-push-pin layer is composed of a plurality of metal layers arranged at a preset gap; The anti-thrust layer is disposed on the transparent conductive layer, and the passivation layer covers the anti-thrust layer; Alternatively, the anti-throwing layer is arranged on the passivation layer, a protective layer is further arranged on the passivation layer, the protective layer covers the anti-throwing layer, and the P-type pad and the N-type pad penetrate the protective layer and the passivation layer and are electrically connected to the corresponding P-type electrode and N-type electrode; The preset gap between adjacent metal layers is L1, and the width of the metal layer is L2, satisfying: L2=0.35L1~10L1.

2. The anti-thrust flip-chip LED chip according to claim 1, characterized in that: The P-type electrode and the N-type electrode each include an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching stop layer and an adhesion layer stacked in sequence, wherein: The ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the ohmic contact layer is 5Å to 100Å; The reflective layer includes at least one of an Al layer and an Ag layer, and the thickness of the reflective layer is 100nm to 300nm; The coating layer comprises at least two of a Ti layer, a Ni layer, and a Pt layer, and the thickness of the coating layer is 100 nm to 1000 nm; The conductive layer includes at least one of an Au layer and a Cu layer, and the thickness of the conductive layer is 200nm to 1500nm; The etch stop layer comprises a Pt layer, and the thickness of the etch stop layer is 200nm-600nm; The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30Å~150Å.

3. The anti-thrust flip-chip LED chip according to claim 2, characterized in that: The anti-thrust layer includes an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching barrier layer and an adhesion layer stacked in sequence, wherein: The ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the ohmic contact layer is 5Å to 100Å; The reflective layer includes at least one of an Al layer and an Ag layer, and the thickness of the reflective layer is 100nm to 300nm; The coating layer comprises at least two of a Ti layer, a Ni layer, and a Pt layer, and the thickness of the coating layer is 100 nm to 1000 nm; The conductive layer includes at least one of an Au layer and a Cu layer, and the thickness of the conductive layer is 200nm to 1500nm; The etch stop layer comprises a Pt layer, and the thickness of the etch stop layer is 200nm-600nm; The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30Å~150Å.

4. The anti-thrust flip-chip LED chip according to claim 2, characterized in that: The anti-thrust layer includes a contact layer, a buffer layer and an adhesion layer stacked in sequence, wherein: The contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the contact layer is 30Å to 500Å; The buffer layer includes at least one of an Au layer, an Al layer, and a Cu layer, and the thickness of the buffer layer is 200nm to 1500nm; The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30Å~150Å.

5. The anti-thrust flip-chip LED chip according to claim 1, characterized in that: The distance between the anti-ejection layer and the P-type pad is a1, and the distance between the anti-ejection layer and the N-type pad is a2, which satisfies: a1=a2=1.5L2~33L2; The width of the anti-thrust layer is b; the width of the P-type pad or the N-type pad is c, satisfying: b≤c.

6. The anti-thrust flip-chip LED chip according to claim 1, characterized in that: The protective layer includes at least one of a SiO2 layer and an Al2O3 layer, and the thickness of the protective layer is 200nm~1000nm.

7. A method for preparing a flip-chip LED chip with anti-ejection properties as claimed in any one of claims 1 to 6, characterized in that: include: Providing a substrate, preparing an epitaxial layer on the substrate, and etching the epitaxial layer to form a groove for arranging an N-type electrode; Preparing a current blocking layer and a transparent conductive layer on the epitaxial layer, so that the transparent conductive layer covers the current blocking layer and leaks out of the groove; Preparing a P-type electrode on the transparent conductive layer and preparing an N-type electrode in the groove; preparing a passivation layer on the transparent conductive layer; Preparing an anti-thrust layer on the transparent conductive layer or the passivation layer, so that the anti-thrust layer and the passivation layer are in contact with each other; Etching the passivation layer until the P-type electrode and the N-type electrode are exposed to form a P-type through hole and an N-type through hole; Preparing a P-type pad and an N-type pad at the upper ends of the P-type through hole and the N-type through hole, and electrically connecting the P-type pad and the N-type pad to the corresponding P-type electrode and the N-type electrode through the P-type through hole and the N-type through hole; Wherein, the anti-thrust layer is arranged between the P-type pad and the N-type pad, and the anti-thrust layer is composed of a plurality of metal layers arranged according to a preset gap.

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