Optical proximity correction method, device and equipment and storage medium

Abstract

The embodiment of the invention provides an optical proximity correction method and device, equipment and a storage medium, and the method comprises the steps: constructing a three-dimensional thin film stacking model according to the structural layout information of a target wafer; and performing photoetching simulation on the three-dimensional film stacking model based on the photoetching parameter information, and determining simulation size data and simulation photoresist three-dimensional data. The actual light intensity distribution of the three-dimensional wafer in the photoetching process is accurately simulated, and the simulated result provides a powerful reference basis for the subsequent correction process, so that the practicability of the correction process is improved. And performing optical proximity correction according to the standard size data and the standard photoresist three-dimensional data. According to the technical scheme provided by the embodiment of the invention, the multi-layer structure of the target wafer can be fully considered from the three-dimensional level in the optical proximity effect correction process, the authenticity and practicability of the subsequent photoetching simulation process are effectively improved, the real light intensity distribution is considered in combination with the wafer structure, and the optical proximity effect correction accuracy is improved. And the optical proximity correction effect and the production efficiency of compliant wafers are improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor manufacturing, and in particular, relates to an optical proximity correction method, device, equipment and storage medium. Background Art

[0002] In the field of semiconductor manufacturing, Optical Proximity Correction (OPC) is one of the important processes for manufacturing chip masks based on chip layout that can be used to lithographically produce compliant wafers.

[0003] At present, the chip optical proximity effect correction for chip masks is mainly carried out through wafer lithography simulation to determine the appropriate and specific correction method. However, at this stage, when performing wafer lithography simulation, most of them only simulate the two-dimensional section of the wafer. The simulation process of the traditional two-dimensional section cannot accurately simulate the actual light intensity distribution of the wafer during the lithography process. For example, when special process structures such as shallow trench isolation (STI) or polysilicon gate (Poly Gate) are stacked on the surface of the wafer, the lithography simulation of the two-dimensional section cannot fully consider the reflection problem of the special structure, which makes the optical proximity effect correction process have errors, which in turn affects the actual lithography process of the wafer. Summary of the invention

[0004] The embodiments of the present application provide an optical proximity correction method, device, and storage medium to effectively improve the accuracy and practicality of an optical proximity effect correction process for a wafer.

[0005] In a first aspect, an embodiment of the present application provides an optical proximity correction method, comprising:

[0006] Constructing a three-dimensional thin film stacking model corresponding to the target wafer according to the structural layout information corresponding to the target wafer;

[0007] Obtaining standard size data and standard photoresist three-dimensional data corresponding to the target wafer;

[0008] Performing photolithography simulation on the three-dimensional thin film stack model according to preset photolithography parameter information to determine simulated dimension data and simulated photoresist three-dimensional data corresponding to the three-dimensional thin film stack model;

[0009] An optical proximity correction is performed on the target wafer according to the simulated size data and the standard size data, as well as the simulated photoresist three-dimensional data and the standard photoresist three-dimensional data.

[0010] In a second aspect, an embodiment of the present application provides an optical proximity correction device, comprising:

[0011] A model building unit, used to build a three-dimensional thin film stacking model corresponding to the target wafer according to the structural layout information corresponding to the target wafer;

[0012] An acquisition unit, used for acquiring standard size data and standard photoresist three-dimensional data corresponding to a target wafer;

[0013] A photolithography simulation unit, used to perform photolithography simulation on the three-dimensional thin film stack model according to preset photolithography parameter information, and determine simulation dimension data and simulated photoresist three-dimensional data corresponding to the three-dimensional thin film stack model;

[0014] The optical proximity correction unit is used to perform optical proximity correction on the target wafer according to the simulated size data and the standard size data, as well as the simulated photoresist three-dimensional data and the standard photoresist three-dimensional data.

[0015] In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor, a memory, and a program or instruction stored in the memory and executable on the processor, which implements the steps of any optical proximity correction method of the embodiment of the present application when the program or instruction is executed by the processor.

[0016] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of any optical proximity correction method of the embodiment of the present application are implemented.

[0017] In a fifth aspect, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device can perform the steps of any optical proximity correction method of the embodiment of the present application.

[0018] The technical solution provided by the embodiments of the present application brings at least the following beneficial effects:

[0019] The optical proximity correction method provided in the embodiment of the present application can construct a three-dimensional thin film stacking model according to the structural layout information of the target wafer, fully consider the multi-level structure of the target wafer from the three-dimensional level, and effectively improve the authenticity and practicality of the subsequent lithography simulation process. Then, based on the lithography parameter information, the three-dimensional thin film stacking model is subjected to lithography simulation, the corresponding simulation size data and simulation photoresist three-dimensional data are determined, and the actual light intensity distribution of the three-dimensional wafer during the lithography process is accurately simulated. The simulation result provides a strong reference basis for the subsequent correction process, thereby improving the practicality of the correction process. Finally, according to the standard size data and the standard photoresist three-dimensional data, optical proximity correction is performed. Fully consider the wafer structure and light intensity distribution from the three-dimensional level to improve the optical proximity correction effect and the production efficiency of compliant wafers.

[0020] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 A schematic diagram of performing photolithography simulation on a two-dimensional cross section of a wafer provided in one embodiment of the present application;

[0023] Figure 2 A schematic flow chart of an optical proximity correction method provided in one embodiment of the present application;

[0024] FIG. 3( a ) is one of schematic diagrams of a three-dimensional thin film stacking model corresponding to a target wafer with uneven structural layout distribution provided by an embodiment of the present application;

[0025] FIG3( b ) is a second schematic diagram of a three-dimensional thin film stacking model corresponding to a target wafer with uneven structural layout distribution provided by an embodiment of the present application;

[0026] Figure 4 A schematic diagram of a process of performing lithography simulation using an optical analysis model and a photoresist analysis model provided in one embodiment of the present application;

[0027] FIG. 5( a ) is a schematic diagram of an optical proximity correction process of a target wafer having a shallow trench isolation structure provided by one embodiment of the present application;

[0028] FIG5( b ) is a second schematic diagram of an optical proximity correction process of a target wafer having a shallow trench isolation structure provided by an embodiment of the present application;

[0029] FIG. 6( a ) is a schematic diagram of an optical proximity correction process for a target wafer having a polysilicon gate structure provided by one embodiment of the present application;

[0030] FIG6( b ) is a second schematic diagram of an optical proximity correction process for a target wafer having a polysilicon gate structure provided by one embodiment of the present application;

[0031] Figure 7 A schematic diagram of the overall process of an optical proximity correction method provided by one embodiment of the present application;

[0032] Figure 8 is a schematic structural diagram of an optical proximity correction device provided by another embodiment of the present application;

[0033] Fig. 9 It is a schematic diagram of the structure of an optical proximity correction device provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0034] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0035] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0036] Currently, Optical Proximity Correction (OPC) is one of the important steps in the chip manufacturing process. At present, the correction is mainly determined by performing wafer lithography simulation.

[0037] However, most of the current optical proximity corrections only simulate lithography on the two-dimensional cross-section of the wafer, and cannot accurately simulate the actual light intensity distribution of the wafer during the lithography process. When facing target wafers with different stacking structures, the light intensity distribution has obvious errors compared to the actual situation, which leads to errors in the subsequent optical proximity correction process, thus affecting the actual lithography process of the wafer. The lithography simulation process for the two-dimensional cross-section of the wafer can be referred to Figure 1 as shown in .

[0038] Figure 1 A schematic diagram of performing photolithography simulation on a two-dimensional cross-section of a wafer is provided for one embodiment of the present application.

[0039] like Figure 1As shown in the figure, the top layer is the lithography light source and the mask corresponding to the wafer. The middle layer is a two-dimensional cross-sectional image containing multiple stacked layers constructed for the wafer, which may include Figure 1 The top anti-reflective coating (TARC), photoresist (PR) and substrate layer (Substrate) shown in FIG. The bottom layer is the development result after photolithography simulation.

[0040] The specific process is: Figure 1 The light source of the top layer is partially blocked by the mask, and partially illuminates the middle layer. After being irradiated by the light source, part of the photoresist in the photoresist layer in the middle layer undergoes chemical decomposition and dissolves in the developer. Finally, after the photolithography simulation is completed, the development result shown in the bottom layer can be obtained. It can be seen that there is only a part of the photoresist on the substrate that is not irradiated due to the shielding of the mask.

[0041] like Figure 1 The process of lithography simulation based on the two-dimensional cross-sectional image shown is relatively simple, and the wafer itself has no special process or structure. However, when there are special process structures such as shallow trench isolation (STI) or polysilicon gate (Poly Gate) in the wafer, Figure 1 The method shown can no longer perform lithography simulation more accurately.

[0042] The reason is that the different processes and structures in the wafer may reflect light when exposed to the light source due to the processing technology or material properties during the actual photolithography process, and a part of the photoresist layer that should not be decomposed is also decomposed due to the reflected light. As a result, the photoresist morphology obtained on the actual wafer surface has a significant error from the standard situation, which in turn affects the performance and yield of the wafer after photolithography. Figure 1 The method of lithography simulation based on two-dimensional cross-sectional images shown in cannot accurately simulate the light intensity distribution in the actual lithography process, and when there are special process structures, the specific images corresponding to different cross-sections of the wafer are also different. Only a single two-dimensional cross-sectional image cannot accurately cover the complete internal structure of the wafer.

[0043] Based on the technical problems mentioned in the above content, an optical proximity correction method, device, equipment and storage medium are provided in the embodiments of the present application, which can construct a three-dimensional thin film stacking model corresponding to the structural layout information of the target wafer, so as to fully consider the multi-level structure of the target wafer from a three-dimensional level, so as to improve the authenticity and practicality of the subsequent lithography simulation process.

[0044] A photolithography simulation is performed on a three-dimensional thin film stack model to determine the simulated size data and simulated photoresist three-dimensional data. During the simulation process, the actual light intensity distribution in the three-dimensional wafer is accurately simulated. The simulation results provide a strong theoretical basis for the subsequent correction process and improve the practicality of the correction process. Finally, optical proximity correction is performed based on the standard size data and standard photoresist three-dimensional data. The technical solution of the embodiment of the present application fully considers the wafer structure and light intensity distribution from a three-dimensional level, improves the practical effect of optical proximity correction and the production efficiency and yield of the wafer.

[0045] Among them, the execution subject adopted in the embodiment of the present application may be a terminal device, such as a desktop computer, a laptop computer, etc., or a remote device such as a server. In addition, the execution subject adopted in the embodiment of the present application may also be an execution subject in the form of software, such as a client installed in a terminal device, a software program, etc. There is no strict limitation on the execution subject of the technical solution provided in the embodiment of the present application, and it can be determined according to the actual application scenario and actual needs.

[0046] The specific application scenarios corresponding to the optical proximity correction method, device, equipment and storage medium provided in the embodiments of the present application are not strictly limited in this application and can be determined according to actual needs.

[0047] For example, in a scenario where optical proximity effect correction is performed on a target wafer having a shallow trench isolation structure, an execution entity (such as a terminal device, etc.) using an embodiment of the present application can construct a three-dimensional thin film stacking model having a shallow trench isolation structure.

[0048] Then, according to the preset lithography parameter information, the three-dimensional thin film stack model is subjected to lithography simulation, and the reflection of the shallow trench isolation structure to the light source during the lithography process is accurately simulated, thereby determining the simulated size data and simulated photoresist three-dimensional data corresponding to the target wafer with the shallow trench isolation structure.

[0049] Optical proximity correction is further performed based on the simulation data to effectively overcome the negative impact of the reflection problem of the shallow trench isolation structure on the three-dimensional morphology of the photoresist on the wafer, thereby ensuring wafer quality and production yield.

[0050] It should be noted that the application scenarios described in the above embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art will appreciate that, with the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems. The optical proximity correction method provided in the embodiments of the present application can be applied to various scenarios where optical proximity correction of wafers is required.

[0051] Figure 2 A schematic flow chart of an optical proximity correction method provided for one embodiment of the present application.

[0052] like Figure 2 As shown in , the optical proximity correction method provided by the embodiment of the present application includes steps S201 to S204.

[0053] S201: constructing a three-dimensional thin film stacking model corresponding to the target wafer according to the structural layout information corresponding to the target wafer.

[0054] In step S201, an execution entity (such as a terminal device, etc.) that applies the technical solution provided by the embodiment of the present application can construct a three-dimensional thin film stacking model corresponding to the target wafer according to the structural layout information corresponding to the target wafer.

[0055] The structural layout information may specifically indicate the structure type corresponding to the target wafer, such as Shallow Trench Isolation (STI) or Polysilicon Gate (PolyGate) mentioned in the above example.

[0056] Regarding the specific construction process of the three-dimensional thin film stacking model, in an embodiment provided in the present application, the three-dimensional thin film stacking model can be constructed according to preset lithography process data and structural layout information corresponding to the target wafer.

[0057] Specifically, the photolithography process data may include but is not limited to coating parameters (Coating), deposition parameters (Deposit), chemical mechanical polishing parameters (Chemical Mechanical Planarization or Polishing, CMP) and etching parameters (Etch).

[0058] The spraying parameters can specifically indicate the speed, thickness, uniformity, etc. of photoresist coating in a three-dimensional thin film stack model. The deposition parameters can indicate the deposition temperature, pressure, gas flow rate, deposition rate, etc. of a three-dimensional thin film stack model of a component, and can be specifically divided into different deposition technologies, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. The chemical mechanical polishing parameters can specifically be used to indicate data such as polishing pressure, slurry composition, rotation speed, flatness, etc. The etching parameters can specifically indicate data such as etching gas type, etching time, temperature, plasma power, etc.

[0059] Based on the above data and the structural layout of the target wafer, a three-dimensional thin film stacking model corresponding to the target wafer can be accurately constructed. It should be noted that when the structural layout is unevenly distributed inside the target wafer, the two-dimensional sections at different positions in the three-dimensional thin film stacking model are not exactly the same.

[0060] Therefore, the technical solution provided by the embodiment of the present application can provide a three-dimensional thin film stacking model that can simulate the actual light intensity distribution for the subsequent lithography simulation process, and can also fully consider the impact of uneven structural distribution on lithography simulation. Rather than only performing lithography simulation of the entire three-dimensional wafer based on a single two-dimensional section of target experience, a specific example of a three-dimensional thin film stacking model is shown in FIG3(a) and FIG3(b) , where the structural layout information corresponding to the target wafer includes two bottom anti-reflection layers and the presence of an etching structure and a deposition process.

[0061] FIG. 3( a ) and FIG. 3( b ) are schematic diagrams of a three-dimensional thin film stacking model corresponding to a target wafer with an unevenly distributed structural layout provided by an embodiment of the present application.

[0062] Figure 3(a) is a schematic diagram of a three-dimensional thin film stacking model corresponding to a target wafer with uneven structure layout. As can be seen from Figure 3(a), the distribution of the etched structure and the corresponding deposition in the target wafer of this example is not uniform, and there are different sizes of etching and deposition in the middle of the left side, the lower middle part, and the upper right side.

[0063] Fig. 3(b) is a schematic diagram of multi-position cross-sections of a three-dimensional thin film stack model corresponding to a target wafer with uneven structural layout distribution in Fig. 3(a). As shown in Fig. 3(b), the structural layouts represented in the cross-section image of the front side, the cross-section image of the back side, and the cross-section image in the middle of the three-dimensional thin film stack model corresponding to the target wafer in this example are completely different.

[0064] The technical solution provided by the embodiment of the present application can simulate the three-dimensional thin film stack model as a whole as shown in FIG3(b) in the subsequent lithography simulation process, rather than simulating a certain cut surface. It fully considers the influence of each structural layout on the light intensity distribution, and also fully considers the influence of the uneven layout distribution on the overall lithography simulation process of the target wafer. It provides a strong basis for subsequent optical proximity correction, thereby ensuring the accuracy of the actual lithography process and improving the wafer production yield and quality.

[0065] S202: Obtain standard size data and standard photoresist three-dimensional data corresponding to the target wafer.

[0066] In step S202, the technical solution provided in the embodiment of the present application can obtain standard size data and standard photoresist three-dimensional data corresponding to the target wafer.

[0067] Among them, the standard size data can be used to represent the size scanning data (Critical Dimension, CD) determined by a critical dimension scanning electron microscope (Critical Dimension Scanning Electron Microscope, CD-SEM) corresponding to a target wafer with a standard size. The standard photoresist three-dimensional data can be used to represent the three-dimensional morphology of the photoresist on the surface of a target wafer that meets the standard.

[0068] Regarding the specific determination process of standard size data and standard photoresist three-dimensional data, in an embodiment provided in the present application, based on the design layout data corresponding to the target wafer, the size scanning data corresponding to the target wafer under theoretical conditions can be determined as the standard size data.

[0069] Then, the three-dimensional data of multiple sample wafers corresponding to the target wafer can be obtained. The sample wafers can be wafers produced in the past corresponding to the target wafer, and the corresponding size scanning data needs to be further determined whether it meets the standard.

[0070] Next, for each sample wafer, the size scan data corresponding to the sample wafer can be determined based on the three-dimensional data of the sample wafer. Finally, the size scan data corresponding to each sample wafer can be used to determine whether it matches the acquired standard size data, and the matching sample wafer is used as the standard wafer, and the three-dimensional data corresponding to the standard wafer can be used as the standard photoresist three-dimensional data. The matching process can specifically be based on a set error threshold to determine whether the data error between the size scan data corresponding to each sample wafer and the standard size data meets the error threshold.

[0071] It should be noted that the above-mentioned target wafer and the corresponding multiple sample wafers can all be partial wafers of a whole wafer. The three-dimensional data of the sample wafer can specifically be the three-dimensional slice data of the same wafer portion among multiple wafers produced historically. In addition, if there are multiple sample wafers that match the standard size data at the same time, the three-dimensional features of the three-dimensional data corresponding to the multiple sample wafers can be extracted to determine the average three-dimensional data that can cover the multiple sample wafers as the standard photoresist three-dimensional data.

[0072] Through the above determination process, the technical solution provided by the embodiment of the present application can accurately determine the standard size data of the target wafer, and accurately screen out the sample wafers that match the standard size data, and use the corresponding three-dimensional data as the standard photoresist three-dimensional data. It provides a reference standard for subsequent testing of lithography simulation results, effectively ensures the accuracy of testing lithography simulation results, and improves the effectiveness and practicality of the subsequent optical proximity correction process.

[0073] S203: performing photolithography simulation on the three-dimensional thin film stack model according to preset photolithography parameter information, and determining simulation dimension data and simulated photoresist three-dimensional data corresponding to the three-dimensional thin film stack model.

[0074] In step S203, the technical solution provided in the embodiment of the present application can perform lithography simulation on the three-dimensional thin film stack model constructed in the above steps based on the preset lithography parameter information. According to the lithography simulation results, the simulation size data and simulated photoresist three-dimensional data corresponding to the three-dimensional thin film stack model are determined.

[0075] Among them, the photolithography parameter information may specifically include but is not limited to the light source corresponding to the photolithography process, the mask information corresponding to the target wafer, etc., which is used to simulate the actual photolithography simulation process. The simulated dimension data is similar to the standard dimension data in the above steps, and is specifically the dimension scanning data in the three-dimensional thin film stack model after the photolithography simulation. Similarly, the simulated photoresist three-dimensional data is similar to the standard photoresist three-dimensional data in the above steps, and can be specifically used to represent the three-dimensional morphology of the photoresist corresponding to the three-dimensional thin film stack model after the photolithography simulation.

[0076] Regarding the specific processing process of lithography simulation, in one embodiment provided in the present application, the technical solution provided in the embodiment of the present application can input the three-dimensional thin film stacking model and lithography parameter information into a preset lithography simulation model, so that the lithography simulation model can perform lithography simulation on the three-dimensional thin film stacking model based on the lithography parameter information, thereby accurately determining the simulated size data and simulated photoresist three-dimensional data corresponding to the three-dimensional thin film stacking model after the lithography simulation.

[0077] Among them, in one embodiment provided in the present application, the photolithography simulation model may specifically include but is not limited to an optical analysis model and a photoresist analysis model. The optical analysis model may be used to analyze the light irradiation path and light intensity distribution of a light source in multiple stacked layers of a three-dimensional thin film stack model during the photolithography simulation process. The photoresist analysis model may be used to analyze the three-dimensional morphology of the undecomposed portion of the photoresist in the photoresist layer on the three-dimensional thin film stack model after the photolithography simulation.

[0078] In this embodiment, the specific process of performing lithography simulation using the optical analysis model and the photoresist analysis model can be referred to Figure 4 as shown in .

[0079] Figure 4 A schematic diagram of a process of performing lithography simulation using an optical analysis model and a photoresist analysis model is provided for one embodiment of the present application, specifically including steps S401 to S403.

[0080] S401: Determine light intensity distribution data of a three-dimensional thin film stack model during a lithography simulation process through an optical analysis model and lithography parameter information.

[0081] Through step S401, the lithography analysis model can analyze and determine the distribution of light intensity in each stacked layer of the three-dimensional thin film stack model when it is irradiated by the light source based on the light source information and mask information in the lithography parameter information, for example, fully and accurately determine the reflection of each material or structure to the irradiated light. The determined light intensity distribution data can be used for subsequent lithography simulation processes.

[0082] In the embodiment of the present application, the specific model category of the optical analysis model is not limited. For example, it can be a rigorous optical model (Rigorous Coupled Wave Analysis, RCWA), which first calculates the incident light intensity at the top of the three-dimensional thin film stack model, and solves the Maxwell's equations corresponding to the three-dimensional thin film stack model based on the rigorous coupled wave analysis method, so as to accurately calculate the propagation path, scattering and reflection of the incident light in each stack layer, and finally integrate the data to determine the light intensity distribution data. Or it can be other models or algorithms with optical analysis capabilities, which can be flexibly limited according to actual application scenarios and actual needs.

[0083] S402: performing photolithography simulation on the three-dimensional thin film stacking model according to the light intensity distribution data, and determining simulation dimension data corresponding to the three-dimensional thin film stacking model.

[0084] In step S402, according to the light intensity distribution data determined by the optical analysis model, a lithography simulation that conforms to the actual light intensity distribution can be performed on the three-dimensional thin film stack model to obtain a three-dimensional thin film stack model after lithography simulation. Based on the three-dimensional thin film stack model after lithography simulation, the corresponding simulation size data can be determined.

[0085] It should be noted that in another embodiment provided in the present application, before performing lithography simulation based on the light intensity distribution data, it is also possible to pre-judge whether there may be potential abnormal problems in the subsequent lithography simulation process based on the light intensity distribution data, so as to timely adjust the model structure of the three-dimensional thin film stacking model before the lithography simulation to avoid the execution of invalid or abnormal lithography simulation processes.

[0086] The specific method of judging whether there is a potential abnormal problem in the lithography simulation process based on the light intensity distribution data is not strictly limited in the embodiments provided in this application. It can be that relevant personnel, based on historical experience, after determining the light intensity distribution data through an optical analysis model and before performing lithography simulation, actively predict the subsequent lithography simulation process based on the light intensity distribution data, so as to timely discover simulation abnormalities that may be caused by the current light intensity distribution data.

[0087] For example, it is determined that some parts that should have strong light intensity distribution have abnormally low light intensity distribution. In addition to manual observation, it is also possible to predict whether there may be abnormal problems in the lithography simulation process based on the light intensity distribution data according to pre-set detection rules. The specific implementation method and approach can be determined according to the actual application scenario and actual needs.

[0088] After determining that the light intensity distribution data has a problem that will cause anomalies in the subsequent photolithography simulation process, the model structure corresponding to the three-dimensional thin film stack model can be adjusted in advance according to the abnormal problem, and then the light intensity distribution data corresponding to the adjusted three-dimensional thin film stack model is determined through the optical analysis model in the above steps. Then, according to the adjusted corresponding light intensity distribution data, the adjusted three-dimensional thin film stack model is subjected to photolithography simulation again to determine the simulation size data.

[0089] Based on the above process, potential anomalies that may exist in the simulation process can be effectively detected before the lithography simulation is performed, and the three-dimensional thin film stack model can be adjusted in time. The authenticity and practicality of the lithography simulation process are effectively guaranteed, invalid lithography simulation processes are avoided, and simulation efficiency is improved. At the same time, an accurate lithography simulation process can also improve the accuracy and practicality of the subsequent optical proximity correction process.

[0090] S403: Analyze the three-dimensional morphology of the photoresist corresponding to the three-dimensional thin film stacking model simulated by photolithography through the photoresist analysis model to obtain simulated three-dimensional photoresist data.

[0091] In step S403, the photoresist analysis model can accurately determine the three-dimensional morphology of the photoresist corresponding to the three-dimensional thin film stack model after the photolithography simulation, thereby obtaining the corresponding simulated photoresist three-dimensional data. The model type and structure corresponding to the photoresist analysis model are not strictly limited in the embodiments of the present application. Specifically, it can be a computational model with three-dimensional model image analysis capabilities such as convolutional neural networks (CNNs), which can be selected according to actual application scenarios and actual needs.

[0092] Through the above steps S401 to S403, a photolithography simulation close to the actual situation can be performed on the three-dimensional film stack model, and the simulated size data and simulated photoresist three-dimensional data corresponding to the simulated three-dimensional film stack model can be accurately determined. This provides a strong basis for the subsequent optical proximity correction process, improves the practicality and accuracy of the correction process, and further improves the production efficiency and production yield of the final wafer.

[0093] S204: performing optical proximity correction on the target wafer according to the simulated size data and the standard size data, as well as the simulated photoresist three-dimensional data and the standard photoresist three-dimensional data.

[0094] In step S204, the technical solution provided by the embodiment of the present application can determine whether the optical simulation process of the target wafer meets the standard based on the simulated size data and simulated photoresist three-dimensional data determined after performing photolithography simulation on the three-dimensional thin film stack model through the above steps, and the standard size data and standard photoresist three-dimensional data obtained in the previous steps. For target wafers that do not meet the standards, optical proximity correction can be performed.

[0095] Specifically, in an embodiment provided in the present application, the simulation error corresponding to the three-dimensional thin film stack model in the lithography simulation process can be determined based on the simulation size data and the standard size data. The simulation error can specifically be the root mean square (RMS) of the simulation size data and the standard size data. Then, it is determined whether the simulation error is less than a preset standard error threshold.

[0096] At the same time, it is also possible to determine whether the simulated photoresist 3D data matches the standard photoresist 3D data. Specifically, it can be determined whether the simulated photoresist 3D data matches the standard photoresist 3D data, and whether they match according to a preset similarity threshold.

[0097] When it is determined through the above process that the simulation error is less than the preset standard error threshold, or the simulated photoresist 3D data does not match the standard photoresist 3D data, it can be determined that the photolithography simulation corresponding to the target wafer does not meet the standard, that is, the optical proximity correction process can be performed on the target wafer. Only when the simulation error is not less than the preset standard error threshold, and at the same time the simulated photoresist 3D data matches the standard photoresist 3D data, can it be determined that the photolithography simulation corresponding to the target wafer is fully compliant with the standard.

[0098] Based on the above verification process, it is possible to accurately determine whether the lithography simulation process of the target wafer meets the standards, and accurately determine whether optical proximity correction is required based on the simulation results that are close to the actual simulation situation. This effectively guarantees the production quality and production yield of subsequent wafers, and also improves the production efficiency of standard wafers to a certain extent.

[0099] The specific processing process of optical proximity correction for the target wafer whose lithography simulation does not meet the standards may be to adjust the pattern of the mask of the target wafer in the lithography parameter information, or to adjust the model structure of the three-dimensional thin film stacking model, or to adjust the parameters in other simulation processes, which may be determined according to the actual application scenario and actual needs.

[0100] In order to specifically understand the processing process of performing optical proximity correction on a target wafer, the optical proximity correction process of an embodiment of the present application is illustrated below by taking a target wafer with a shallow trench isolation structure and a target wafer with a polysilicon gate as examples.

[0101] FIG. 5( a ) and FIG. 5( b ) are schematic diagrams of an optical proximity correction process for a target wafer having a shallow trench isolation structure according to an embodiment of the present application.

[0102] FIG. 5( a ) is a schematic diagram of a lithography simulation process of a two-dimensional cross-section of a three-dimensional thin film stack model of a target wafer having a shallow trench isolation structure before optical proximity correction is performed.

[0103] As shown in Figure 5(a), when the incident light from the top light source is blocked by the mask and enters the stacked layer with the shallow trench isolation structure, the side of the shallow trench isolation structure will reflect the light to the photoresist area that was not illuminated by the mask, causing the photoresist that should not be decomposed to be decomposed by the reflected light. It can be clearly seen from the simulation results obtained at the bottom of Figure 5(a) that part of the photoresist adjacent to the stacked layer of the shallow trench isolation structure in the undecomposed photoresist part is abnormally decomposed, resulting in a significant error between the three-dimensional morphology of the photoresist in the simulation result and the standard three-dimensional data of the photoresist.

[0104] FIG. 5( b ) is a schematic diagram of the lithography simulation process after optical proximity correction is performed on the two-dimensional section corresponding to FIG. 5( a ).

[0105] As shown in Figure 5(b), a light shielding module is added to the photoresist layer in the two-dimensional section of the three-dimensional thin film stack model shown in Figure 5(a). From the development result at the bottom of Figure 5(b), it can be clearly seen that the problem of the decomposition of the part of the photoresist that should be retained due to the reflection problem of the shallow trench isolation structure in Figure 5(a) does not occur again. Finally, the three-dimensional morphology of the photoresist corresponding to the three-dimensional thin film stack model after the simulation is completely consistent with the standard three-dimensional photoresist data.

[0106] As shown in Figures 5(a) and 5(b), in an embodiment provided in the present application, when performing optical proximity correction on a target wafer that does not meet the standards in the lithography simulation process, the internal structure of the three-dimensional thin film stack model in the lithography simulation process can be adjusted, thereby effectively overcoming the abnormal decomposition of the photoresist caused by light reflected from the structure surface as shown in Figures 5(a) and 5(b).

[0107] Finally, the three-dimensional thin film stacking model with a light shielding module added to the photoresist layer as shown in FIG5(a) and the unadjusted lithography parameter information can be used as the optical proximity correction result corresponding to the target wafer. In the subsequent actual production process of the target wafer, the target wafer that meets the design specifications can be accurately produced according to the optical proximity correction result, significantly improving the production quality and yield of the target wafer.

[0108] FIG. 6( a ) and FIG. 6( b ) are schematic diagrams of an optical proximity correction process for a target wafer having a polysilicon gate structure according to an embodiment of the present application.

[0109] Similar to FIG. 5( a ), FIG. 6( a ) is a schematic diagram of a photolithography simulation process of a certain two-dimensional cross-section of a three-dimensional thin film stack model of a target wafer having a polysilicon gate structure before optical proximity correction is performed.

[0110] As shown in FIG6(a), when the incident light from the top light source is blocked by the mask and enters the photoresist layer having the polysilicon gate structure, the polysilicon gate structure itself will emit the light to the photoresist area that was originally not illuminated by the mask blocking part, causing part of the photoresist that should not be decomposed to be decomposed by the reflected light.

[0111] It can be clearly seen from the simulation results obtained at the bottom of Figure 6(a) that a portion of the photoresist that should be retained in the standard photoresist 3D morphology is abnormally decomposed by the light emitted by the polysilicon gate structure, resulting in an obvious error between the photoresist 3D morphology in the simulation results and the standard photoresist 3D data. This type of photolithography simulation process does not meet standard specifications in terms of both simulated dimensional data and simulated photoresist 3D data.

[0112] FIG. 6( b ) is a schematic diagram of the lithography simulation process after optical proximity correction is performed on the two-dimensional section corresponding to FIG. 5( a ).

[0113] As shown in Figure 6(b), a mask auxiliary pattern is added to the structure composed of the light source and mask shown in the top of Figure 6(a). Furthermore, from the simulation results at the bottom of Figure 6(b), it can be clearly seen that the problem of the original light problem of the polysilicon gate structure in Figure 6(a), which caused part of the photoresist that should be retained to be decomposed, did not occur again. Finally, the three-dimensional morphology of the photoresist corresponding to the three-dimensional film stack model after the simulation was completed was also completely consistent with the standard three-dimensional photoresist data.

[0114] As shown in FIG. 6( a ) and FIG. 6( b ), in an embodiment provided in the present application, when performing optical proximity correction on a target wafer that does not meet the standards in a lithography simulation process, adaptive adjustments can be made to the lithography parameter information in the lithography simulation process.

[0115] Specifically, the mask image corresponding to the target wafer can be adjusted, and mask auxiliary images can be added, etc. The internal structure of the three-dimensional film stack model can be adjusted, thereby effectively overcoming the abnormal decomposition of part of the photoresist caused by the light emitted by the structure itself, such as in Figures 6(a) and 6(b).

[0116] Finally, the adjusted lithography parameter information (including the mask image with the mask auxiliary image added) similar to that in FIG6(a) and the unadjusted three-dimensional film stack model can be used as the optical proximity correction result corresponding to the target wafer. In the subsequent actual production process of the target wafer, the target wafer that meets the design specifications can be accurately produced according to the optical proximity correction result, which significantly improves the production quality and yield of the target wafer.

[0117] In addition to the above examples, the technical solution provided in the embodiments of the present application can also achieve optical proximity correction by adjusting other parameters in the photolithography simulation process. For example, adjusting light source parameters, developer concentration, simulation temperature, etc. The adjusted parameters can also be used as optical proximity correction results in the actual production process of subsequent target wafers.

[0118] In addition, the technical solution provided in the embodiment of the present application can perform lithography simulation again on the target wafer that has undergone optical proximity correction to verify whether the target wafer after optical proximity correction strictly complies with the standard specifications. If the lithography simulation process still fails to meet the standard specifications after a single optical proximity correction, optical proximity correction can be performed again, and the correction method can be readjusted or replaced, and so on, and corrections are repeated until a lithography simulation process that meets the standard specifications is determined, and the corresponding relevant data is used as the optical proximity correction result.

[0119] In order to facilitate understanding of all the above contents, the optical proximity correction method provided in the embodiment of the present application is fully described below. Figure 7 as shown in .

[0120] Figure 7 An overall flow chart of an optical proximity correction method provided for one embodiment of the present application includes steps S701 to S706.

[0121] like Figure 7As shown in , the optical proximity correction method provided in the embodiment of the present application can construct a three-dimensional thin film stacking model corresponding to the target wafer according to the photolithography process data and the structural layout information through step S701. Then, the standard size data can be determined according to the design layout data through step S702, and the standard wafer can be determined from multiple sample wafers, thereby determining the standard photoresist three-dimensional data.

[0122] Next, in step S703, the three-dimensional thin film stack model is subjected to lithography simulation based on preset lithography parameter information through the optical analysis model and the photoresist analysis model to determine simulated dimension data and simulated photoresist three-dimensional data corresponding to the three-dimensional thin film stack model.

[0123] Further, in step S704, it is determined whether the simulated size data and the simulated photoresist three-dimensional data meet the standard according to the standard size data and the standard photoresist three-dimensional data. If they do not meet the standard, an optical proximity correction is performed on the target wafer in step S705. The specific correction method may be to adjust the three-dimensional film stack model constructed in S701, or to adjust the parameter data such as the lithography parameters used in the lithography simulation process in step S703 accordingly.

[0124] After the adjustment, the steps S701 to S704 can be performed again, and the corrections can be repeated until the lithography simulation process that meets the standard specifications is determined. The corresponding three-dimensional film stack model and lithography parameter information can be output as an optical proximity correction result through step S706, so that the production of the target wafer with high efficiency and high precision can be achieved based on the optical proximity correction result.

[0125] The above is a specific implementation method of the optical proximity correction method provided in the embodiment of the present application, which can construct a three-dimensional thin film stacking model corresponding to the structural layout information of the target wafer, so as to fully consider the multi-level structure of the target wafer from a three-dimensional level, thereby improving the authenticity and practicality of the subsequent lithography simulation process.

[0126] The photolithography simulation is performed on the three-dimensional thin film stack model to determine the simulated size data and the simulated photoresist three-dimensional data. The actual light intensity distribution in the three-dimensional wafer is accurately simulated during the simulation process. The simulation results provide a strong theoretical basis for the subsequent correction process and improve the practicality of the correction process. The simulation process considers and analyzes the light intensity distribution and the three-dimensional morphology of the photoresist separately, which is helpful for the subsequent accurate and effective implementation of the optical proximity correction process.

[0127] Finally, optical proximity correction is performed according to the standard size data and the standard photoresist three-dimensional data. The technical solution of the embodiment of the present application fully considers the wafer structure and light intensity distribution from a three-dimensional level, improves the practical effect of optical proximity correction and the production efficiency and yield of the wafer. In addition, the technical solution provided by the embodiment of the present application can perform optical proximity correction on the target wafer from multiple angles, increase the robustness of optical proximity correction, and improve wafer production quality and yield.

[0128] Based on the optical proximity correction method provided in the above embodiments, the present application also provides a specific implementation of the optical proximity correction device, please refer to the following embodiments.

[0129] Figure 8 This is a schematic structural diagram of an optical proximity correction device provided in another embodiment of the present application. The optical proximity correction device 800 includes: a model building unit 801, an acquisition unit 802, a lithography simulation unit 803 and an optical proximity correction unit 804.

[0130] The model building unit 801 is used to build a three-dimensional thin film stacking model corresponding to the target wafer according to the structural layout information corresponding to the target wafer;

[0131] An acquisition unit 802 is used to acquire standard size data and standard photoresist three-dimensional data corresponding to a target wafer;

[0132] The photolithography simulation unit 803 is used to perform photolithography simulation on the three-dimensional thin film stack model according to preset photolithography parameter information, and determine the simulation size data and simulated photoresist three-dimensional data corresponding to the three-dimensional thin film stack model;

[0133] The optical proximity correction unit 804 is used to perform optical proximity correction on the target wafer according to the simulated size data and the standard size data, as well as the simulated photoresist 3D data and the standard photoresist 3D data.

[0134] In the embodiments provided in the present application, the above-mentioned device can be used to construct a three-dimensional thin film stacking model according to the structural layout information of the target wafer, and the multi-level structure of the target wafer is fully considered from a three-dimensional level, effectively improving the authenticity and practicality of the subsequent lithography simulation process. Based on the lithography parameter information, the three-dimensional thin film stacking model is subjected to lithography simulation, and the corresponding simulation size data and simulated photoresist three-dimensional data are determined to accurately simulate the actual light intensity distribution of the three-dimensional wafer during the lithography process. The simulated results provide a strong reference basis for the subsequent correction process, thereby improving the practicality of the correction process. Finally, optical proximity correction is performed according to the standard size data and the standard photoresist three-dimensional data. The wafer structure and light intensity distribution are fully considered from a three-dimensional level to improve the optical proximity correction effect and the production efficiency of compliant wafers.

[0135] In one embodiment, the lithography simulation unit 803 is specifically used for:

[0136] The three-dimensional thin film stack model and lithography parameter information are input into a preset lithography simulation model, so that the lithography simulation model performs lithography simulation on the three-dimensional thin film stack model based on the lithography parameter information to determine simulated dimension data and simulated photoresist three-dimensional data.

[0137] In one embodiment, the lithography simulation model includes an optical analysis model and a photoresist analysis model;

[0138] The above-mentioned lithography simulation unit 803 is specifically used for:

[0139] Determine the light intensity distribution data of the three-dimensional thin film stack model during the lithography simulation process through the optical analysis model and lithography parameter information;

[0140] Performing photolithography simulation on the three-dimensional thin film stack model according to the light intensity distribution data to determine simulation size data corresponding to the three-dimensional thin film stack model;

[0141] The photoresist analysis model is used to analyze the three-dimensional morphology of the photoresist corresponding to the three-dimensional thin film stacking model simulated by photolithography, and the simulated three-dimensional photoresist data is obtained.

[0142] In one embodiment, the lithography simulation unit 803 is specifically used for:

[0143] According to the light intensity distribution data, determine whether there is simulation anomaly in the photolithography simulation process;

[0144] If so, adjust the three-dimensional film stack model according to the simulation anomaly;

[0145] The above-mentioned lithography simulation unit 803 is specifically used for:

[0146] Determine adjusted light intensity distribution data corresponding to the adjusted three-dimensional thin film stacking model through an optical analysis model and lithography parameter information;

[0147] According to the adjusted light intensity distribution data, a photolithography simulation is performed on the adjusted three-dimensional thin film stacking model to determine the simulation size data corresponding to the adjusted three-dimensional thin film stacking model.

[0148] In one embodiment, the optical proximity correction unit 804 is specifically used for:

[0149] Determine the simulation error corresponding to the three-dimensional thin film stacking model according to the simulation size data and the standard size data;

[0150] Determining whether the simulation error is less than a preset standard error threshold, and determining whether the simulated photoresist three-dimensional data matches the standard photoresist three-dimensional data;

[0151] If it is determined that the simulation error is less than a preset standard error threshold, or the simulated photoresist three-dimensional data does not match the standard photoresist three-dimensional data, an optical proximity correction is performed on the target wafer.

[0152] In one embodiment, the structure layout information includes a shallow trench isolation structure, and the optical proximity correction process includes adjusting a model structure of a three-dimensional thin film stack model;

[0153] The optical proximity correction unit 804 is specifically used for:

[0154] According to the simulated size data and the standard size data, as well as the simulated photoresist three-dimensional data and the standard photoresist three-dimensional data, a light shielding module is added to the photoresist layer in the three-dimensional thin film stacking model with a shallow trench isolation structure;

[0155] The three-dimensional thin film stacking model and lithography parameter information after adding the shading module are used as the optical proximity correction result corresponding to the target wafer.

[0156] In one embodiment, the structural layout information includes a polysilicon gate structure, and the optical proximity correction process further includes adjusting photolithography parameter information, and the photolithography parameter information includes a mask image corresponding to a target wafer and photolithography light source information;

[0157] The optical proximity correction unit 804 is specifically used for:

[0158] Adding a mask auxiliary pattern in a mask image corresponding to a target wafer having a polysilicon gate structure according to the simulated size data and the standard size data, as well as the simulated photoresist three-dimensional data and the standard photoresist three-dimensional data;

[0159] The three-dimensional film stacking model and the adjusted photolithography parameter information are used as the optical proximity correction result corresponding to the target wafer, and the adjusted photolithography parameter information includes a mask image with an added mask auxiliary pattern.

[0160] In one embodiment, the model building unit 801 is specifically used for:

[0161] A three-dimensional thin film stacking model corresponding to the target wafer is constructed according to the structural layout information and preset lithography process data, wherein the lithography process data includes at least one parameter among spraying parameters, deposition parameters, chemical mechanical polishing parameters and etching parameters.

[0162] In one embodiment, the acquisition unit 802 is specifically used for:

[0163] Determine standard size data according to the design layout data corresponding to the target wafer;

[0164] Acquire three-dimensional data of multiple sample wafers corresponding to the target wafer;

[0165] Determining size scanning data corresponding to the plurality of sample wafers according to the three-dimensional data of the plurality of sample wafers;

[0166] Determine at least one standard wafer from the plurality of sample wafers according to the size scanning data corresponding to the plurality of sample wafers, the size scanning data corresponding to the standard wafer matching the standard size data;

[0167] The standard photoresist three-dimensional data is determined according to the three-dimensional data of at least one standard wafer.

[0168] Fig. 9 A schematic diagram of the hardware structure of the optical proximity correction device provided in an embodiment of the present application is shown.

[0169] The optical proximity correction device may include a processor 901 and a memory 902 storing computer program instructions.

[0170] Specifically, the processor 901 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0171] The memory 902 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 902 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 902 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 902 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 902 is a non-volatile solid-state memory.

[0172] In certain embodiments, memory 902 includes a read-only memory (ROM). The ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically alterable ROM (EAROM), or flash memory, or a combination of two or more of the above, where appropriate.

[0173] The processor 901 implements any one of the optical proximity correction methods in the above embodiments by reading and executing computer program instructions stored in the memory 902 .

[0174] In one example, the optical proximity correction device may further include a communication interface 903 and a bus 910. Fig. 9 As shown, the processor 901, the memory 902, and the communication interface 903 are connected via a bus 910 and communicate with each other.

[0175] The communication interface 903 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0176] Bus 910 includes hardware, software or both, and the parts of online data flow billing equipment are coupled to each other. For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front-end bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 910 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the present application considers any suitable bus or interconnection.

[0177] In addition, in combination with the optical proximity correction method in the above embodiments, the present application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any one of the optical proximity correction methods in the above embodiments is implemented.

[0178] An embodiment of the present application further provides a computer program product, including a computer program, which implements any one of the optical proximity correction methods in the above embodiments when the computer program is processed and executed.

[0179] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0180] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0181] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0182] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0183] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. An optical proximity correction method, characterized in that: include: Constructing a three-dimensional thin film stacking model corresponding to the target wafer according to the structural layout information corresponding to the target wafer; Acquire standard size data and standard photoresist three-dimensional data corresponding to the target wafer; Performing photolithography simulation on the three-dimensional thin film stack model according to preset photolithography parameter information to determine simulated dimension data and simulated photoresist three-dimensional data corresponding to the three-dimensional thin film stack model; An optical proximity correction is performed on the target wafer according to the simulated size data and the standard size data, and the simulated photoresist three-dimensional data and the standard photoresist three-dimensional data.

2. The method according to claim 1, characterized in that According to preset lithography parameter information, lithography simulation is performed on the three-dimensional thin film stack model to determine simulated dimension data and simulated photoresist three-dimensional data corresponding to the three-dimensional thin film stack model, including: The three-dimensional thin film stacking model and the lithography parameter information are input into a preset lithography simulation model, so that the lithography simulation model performs lithography simulation on the three-dimensional thin film stacking model based on the lithography parameter information to determine the simulated size data and the simulated photoresist three-dimensional data.

3. The method according to claim 2, characterized in that The photolithography simulation model includes an optical analysis model and a photoresist analysis model; Based on the photolithography parameter information, performing photolithography simulation on the three-dimensional thin film stack model to determine the simulated size data and the simulated photoresist three-dimensional data includes: Determining light intensity distribution data of the three-dimensional thin film stack model during a photolithography simulation process by using the optical analysis model and the photolithography parameter information; Performing photolithography simulation on the three-dimensional thin film stack model according to the light intensity distribution data to determine the simulation size data corresponding to the three-dimensional thin film stack model; The photoresist analysis model is used to analyze the three-dimensional morphology of the photoresist corresponding to the three-dimensional thin film stacking model simulated by photolithography to obtain the simulated three-dimensional photoresist data.

4. The method according to claim 3, characterized in that Before performing photolithography simulation on the three-dimensional thin film stack model according to the light intensity distribution data to determine the simulation size data corresponding to the three-dimensional thin film stack model, the method further includes: According to the light intensity distribution data, determining whether there is a simulation anomaly in the photolithography simulation process; If so, adjusting the three-dimensional thin film stack model according to the simulated anomaly; According to the light intensity distribution data, performing a photolithography simulation on the three-dimensional thin film stack model to determine the simulation size data corresponding to the three-dimensional thin film stack model includes: Determining adjusted light intensity distribution data corresponding to the adjusted three-dimensional thin film stacking model through the optical analysis model and the photolithography parameter information; According to the adjusted light intensity distribution data, a photolithography simulation is performed on the adjusted three-dimensional thin film stack model to determine simulation size data corresponding to the adjusted three-dimensional thin film stack model.

5. The method according to claim 1, characterized in that According to the simulated size data and the standard size data, and the simulated photoresist three-dimensional data and the standard photoresist three-dimensional data, optical proximity correction is performed on the target wafer, including: Determining a simulation error corresponding to the three-dimensional thin film stacking model according to the simulation size data and the standard size data; Determining whether the simulation error is less than a preset standard error threshold, and determining whether the simulated photoresist three-dimensional data matches the standard photoresist three-dimensional data; If it is determined that the simulation error is less than a preset standard error threshold, or the simulated photoresist three-dimensional data does not match the standard photoresist three-dimensional data, an optical proximity correction is performed on the target wafer.

6. The method according to claim 1, characterized in that The structural layout information includes a shallow trench isolation structure, and the optical proximity correction process includes adjusting a model structure of the three-dimensional thin film stack model; According to the simulated size data and the standard size data, and the simulated photoresist three-dimensional data and the standard photoresist three-dimensional data, optical proximity correction is performed on the target wafer, including: According to the simulated size data and the standard size data, as well as the simulated photoresist three-dimensional data and the standard photoresist three-dimensional data, a light shielding module is added to the photoresist layer in the three-dimensional thin film stacking model with a shallow trench isolation structure; The three-dimensional thin film stacking model after the shading module is added and the photolithography parameter information are used as the optical proximity correction result corresponding to the target wafer.

7. The method according to claim 1, characterized in that The structural layout information includes a polysilicon gate structure, and the optical proximity correction process further includes adjusting the photolithography parameter information, wherein the photolithography parameter information includes a mask image and photolithography light source information corresponding to a target wafer; According to the simulated size data and the standard size data, and the simulated photoresist three-dimensional data and the standard photoresist three-dimensional data, optical proximity correction is performed on the target wafer, including: Adding a mask auxiliary pattern in a mask image corresponding to the target wafer having a polysilicon gate structure according to the simulated size data and the standard size data, and the simulated photoresist three-dimensional data and the standard photoresist three-dimensional data; The three-dimensional thin film stacking model and the adjusted lithography parameter information are used as the optical proximity correction result corresponding to the target wafer, and the adjusted lithography parameter information includes a mask image with the mask auxiliary pattern added.

8. The method according to claim 1, characterized in that According to the structural layout information corresponding to the target wafer, a three-dimensional thin film stacking model corresponding to the target wafer is constructed, including: A three-dimensional thin film stacking model corresponding to the target wafer is constructed according to the structural layout information and preset lithography process data, wherein the lithography process data includes at least one parameter among spraying parameters, deposition parameters, chemical mechanical polishing parameters and etching parameters.

9. The method according to claim 1, characterized in that: Obtaining standard size data and standard photoresist three-dimensional data corresponding to the target wafer, including: Determining the standard size data according to the design layout data corresponding to the target wafer; Acquiring three-dimensional data of a plurality of sample wafers corresponding to the target wafer; Determining, according to the three-dimensional data of the plurality of sample wafers, dimension scanning data corresponding to the plurality of sample wafers; Determine at least one standard wafer from the plurality of sample wafers according to the size scanning data corresponding to the plurality of sample wafers, wherein the size scanning data corresponding to the standard wafer matches the standard size data; The standard photoresist three-dimensional data is determined according to the three-dimensional data of the at least one standard wafer.

10. An electronic device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the optical proximity correction method as described in any one of claims 1-9 is implemented.

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