Hibernation and Wake-up Methods, Devices and Media for Multi-Core Homogeneous Chip Systems

Abstract

The present application discloses a method, device and medium for dormancy and wake-up of a multi-core homogeneous chip system. The system includes a main core and at least one sub-core, and corresponding synchronization registers are provided for both the main core and the sub-core. The method includes: the main core sends a dormancy instruction, and both the main core and the sub-core make dormancy preparations. During the dormancy preparation, if an execution task instruction is received, the main core configures its register with a parameter value representing the stop of dormancy, sends a wake-up instruction to the sub-core and makes wake-up preparations. After receiving the wake-up instruction, the sub-core interrupts the dormancy to make wake-up preparations and configures its register with a second parameter value representing non-dormancy. After the main core confirms that the sub-core register is the second parameter value, it also configures its own register with this value, and the system enters the wake-up state. The embodiments of the present application can ensure the synchronization of the dormancy and wake-up states among multiple cores and avoid anomalies caused by the asynchronous states of multiple cores.

Description

Technical Field

[0001] The embodiments of the present application relate to, but are not limited to, the field of signal processing technology, and in particular to a sleep and wake-up method, device, and medium for a multi-core homogeneous chip system. Background Art

[0002] In order to improve the read and write performance of devices, storage device manufacturers gradually use multi-core solutions instead of single-core solutions. However, while the multi-core solution brings performance improvement, it also introduces a series of problems that need to be solved urgently. Among them, the inter-core synchronization problem has become a key factor restricting the performance and stability of multi-core systems. In multi-core embedded storage application scenarios, there is usually one CPU core responsible for processing the storage device protocol, and another core processes the flash memory management algorithm and the flash memory underlying driver. Because different cores undertake different tasks, the working status and processing rhythm of each core are different during the operation of the system. If inter-core synchronization cannot be effectively achieved, it is very easy for multiple CPU states to be out of sync. This asynchrony will cause a series of abnormal events, such as data read and write errors, system response delays, and even system crashes, which seriously affect the reliability and stability of the storage system. At the same time, how to achieve fast wake-up after the multi-core system enters the dormant state is also an important challenge currently faced. The fast wake-up function is crucial to improving the user experience and response speed of the device, but the existing technical means are difficult to balance power consumption control and inter-core synchronization while ensuring fast wake-up, and cannot meet the needs of actual applications.

[0003] Therefore, how to effectively achieve inter-core synchronization and ensure fast wake-up in a multi-core system has become an urgent problem to be solved. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiments of the present application provide a sleep and wake-up method, device and medium for a multi-core homogeneous chip system, which can ensure the synchronization of sleep and wake-up states between multiple cores, and effectively prevent abnormal situations caused by asynchrony of multi-core states.

[0006] In a first aspect, an embodiment of the present application provides a method for dormancy and wake-up of a multi-core homogeneous chip system. The multi-core homogeneous chip system includes a main core and at least one sub-core. The main core is provided with a main synchronization register, and the sub-core is provided with a sub-synchronization register. The method includes: the main core sends a dormancy instruction to the sub-core, and the sub-core and the main core perform dormancy preparation work; during the process of the sub-core and the main core performing dormancy preparation work, when an execution task instruction is received, the main core configures the main synchronization register to a first parameter value, sends a wake-up instruction to the sub-core, and performs wake-up preparation work; the sub-core receives the wake-up instruction, interrupts dormancy and performs wake-up preparation work, and configures the sub-synchronization register to a second parameter value; when the main core confirms that the sub-synchronization register is configured to the second parameter value, the main core configures the main synchronization register to the second parameter value, and the system enters a wake-up state; wherein, the main synchronization register configured to the first parameter value indicates that the main core is in a stopped dormancy state, the sub-synchronization register configured to the second parameter value indicates that the sub-core is in a non-dormancy state; the main synchronization register configured to the second parameter value indicates that the main core is in a non-dormancy state.

[0007] In an embodiment of the present application, during the process of the sub-core performing dormancy preparation work, the method includes: if the sub-core confirms that the main synchronization register is configured to the second parameter value or the third parameter value, the sub-core continues to perform the dormancy preparation work, and when the dormancy preparation work is completed, the sub-core configures the sub-synchronization register to the third parameter value; wherein, the sub-synchronization register configured to the third parameter value indicates that the sub-core is in a dormancy state.

[0008] In an embodiment of the present application, during the process of the sub-core performing dormancy preparation work, the method further includes: when the sub-core confirms that the main synchronization register is configured to the first parameter value, the sub-core performs wake-up preparation work, configures the sub-synchronization register to the second parameter value, and the sub-core exits the dormancy state.

[0009] In an embodiment of the present application, during the process of the sub-core performing dormancy preparation work, the method further includes: when the dormancy preparation work is not completed, the sub-core queries the parameter value of the main synchronization register; when the parameter value of the main synchronization register is configured to the second parameter value or the third parameter value, the sub-core continues to perform the dormancy preparation work.

[0010] In an embodiment of the present application, during the process of the main core preparing for dormancy, the method includes: querying the parameter value of the sub-synchronization register when the preparation for dormancy is completed; when it is confirmed that the parameter value of the sub-synchronization register is the third parameter value, the main core configures the main synchronization register to the third parameter value; the main synchronization register being configured to the third parameter value indicates that the main core is in a dormant state.

[0011] In an embodiment of the present application, when the main core is in a dormant state and receives an instruction, the main core interrupts the dormant state and executes the instruction.

[0012] In an embodiment of the present application, the main core executing the instruction includes: if the instruction is a dormancy entry instruction, the main core enters the dormant state again; if the instruction is an execution task instruction, the main core configures the main synchronization register to the first parameter value, sends a wake-up instruction to the sub-core, and simultaneously performs wake-up preparation work.

[0013] In an embodiment of the present application, the main core queries the parameter value of the sub-synchronization register in a periodic manner, or when the sub-core updates the parameter value of the sub-synchronization register, the main core receives the update message sent by the sub-core and configures the parameter value of the main synchronization register accordingly.

[0014] On the other hand, an embodiment of the present application provides a computer device, which includes a processor, a memory, and a computer program stored on the memory and executable by the processor. When the computer program is executed by the processor, it implements the dormancy and wake-up methods of the multi-core homogeneous chip system as described above.

[0015] On the other hand, an embodiment of the present application provides a computer-readable storage medium, which stores a program executable by a processor. The program executable by the processor is used to execute the dormancy and wake-up methods of the multi-core homogeneous chip system as described above when executed by the processor.

[0016] A method for the sleep and wake-up of a multi-core homogeneous chip system provided by an embodiment of the present application. The main core sends a sleep instruction to the sub-cores, and then the sub-cores and the main core synchronously carry out sleep preparation work. During the sleep preparation, if a task execution instruction is received, the main core will configure the main synchronization register with a first parameter value indicating that it is in a stopped sleep state. Then, the main core sends a wake-up instruction to the sub-cores and starts relevant wake-up preparation work. After receiving the wake-up instruction, the sub-cores immediately interrupt the sleep operation and start wake-up preparation work, and at the same time configure the sub-synchronization register with a second parameter value indicating that they are in a non-sleep state. When the main core confirms that the sub-synchronization register has been configured with the second parameter value, the main core will also configure the main synchronization register with the second parameter value indicating that it is in a non-sleep state. At this point, the system officially enters the wake-up state and can normally execute the received tasks. By means of the synchronization register and the configured parameter values, the embodiment of the present application can ensure the synchronization of the sleep and wake-up states among multiple cores. For example, it can ensure that after the sub-cores exit the sleep state, the main core then exits the sleep state to prevent abnormal situations caused by the asynchronous states of multiple cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flowchart of the sleep and wake-up method of the multi-core homogeneous chip system provided by the embodiment of the present application;

[0018] Figure 2 is a flowchart of the main core performing sleep preparation work provided by the embodiment of the present application;

[0019] Figure 3 is the overall flowchart of the sleep and wake-up of the system provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0021] It should be noted that, although the logical order is shown in the flowchart, in some cases, the steps shown or described can be performed in a different order from that in the flowchart. The terms "first", "second", etc. in the specification, claims and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions that can be implemented in this application, so they have no technical substantive significance. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effects that can be produced by this application and the purposes that can be achieved, should still fall within the scope of the technical content disclosed in this application. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of narration, and are not used to limit the scope of implementation of this application. The change or adjustment of the relative relationship should also be regarded as the scope of implementation of this application without substantial change of the technical content.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0023] In order to improve the read and write performance of devices, storage device manufacturers gradually use multi-core solutions instead of single-core solutions. However, while the multi-core solution brings performance improvement, it also introduces a series of problems that need to be solved urgently. Among them, the inter-core synchronization problem has become a key factor restricting the performance and stability of multi-core systems. In multi-core embedded storage application scenarios, there is usually one CPU core responsible for processing the storage device protocol, and another core processes the flash memory management algorithm and the flash memory underlying driver. Because different cores undertake different tasks, the working status and processing rhythm of each core are different during the operation of the system. If inter-core synchronization cannot be effectively achieved, it is very easy for multiple CPU states to be out of sync. This asynchrony will cause a series of abnormal events, such as data read and write errors, system response delays, and even system crashes, which seriously affect the reliability and stability of the storage system. At the same time, how to achieve fast wake-up after the multi-core system enters the dormant state is also an important challenge currently faced. The fast wake-up function is crucial to improving the user experience and response speed of the device, but the existing technical means are difficult to balance power consumption control and inter-core synchronization while ensuring fast wake-up, and cannot meet the needs of actual applications.

[0024] Therefore, how to effectively achieve inter-core synchronization and ensure fast wake-up in a multi-core system has become a key issue that needs to be solved urgently.

[0025] In view of this, the embodiment of the present application provides a sleep and wake-up method of a multi-core homogeneous chip system, a computer device and a computer-readable storage medium. The multi-core homogeneous chip system includes a main core and at least one sub-core, the main core is provided with a corresponding main synchronization register, and the sub-core is provided with a corresponding sub-synchronization register. The embodiment of the present application mainly achieves inter-core synchronization by configuring the register parameter value. The specific method is as follows: the main core sends a sleep instruction to the sub-core, and then the sub-core and the main core synchronously carry out sleep preparation work. During the sleep preparation, if an execution task instruction (such as a task instruction sent by the host) is received, the main core will configure the main synchronization register to a first parameter value representing that it is in a stop sleep state. Then, the main core sends a wake-up instruction to the sub-core and starts related wake-up preparation work. After receiving the wake-up instruction, the sub-core immediately interrupts the sleep operation, starts the wake-up preparation work, and configures the sub-synchronization register to a second parameter value representing that it is in a non-sleep state. When the main core confirms that the sub-synchronization register has been configured as the second parameter value, the main core will also configure the main synchronization register to the second parameter value representing that it is in a non-sleep state. At this point, the system officially enters the wake-up state and can execute the received task normally. The embodiment of the present application can ensure the synchronization of sleep and wake-up states among multiple cores with the help of synchronization registers and configured parameter values. For example, it can ensure that the main core exits sleep after the sub-core exits sleep, so as to prevent abnormal situations caused by asynchrony of multi-core states.

[0026] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0027] Reference Figure 1 , Figure 1 It is a flowchart of the sleep and wake-up method of the multi-core homogeneous chip system provided in the embodiment of the present application. The flowchart mainly describes the complete process of the multi-core homogeneous chip system from entering sleep preparation to being awakened by receiving a task instruction during the sleep preparation process. The whole process revolves around the interaction between the main core and the sub-core, and the configuration of the main synchronization register and the sub-synchronization register. Through these operations, inter-core synchronization is achieved to ensure that the system can respond to tasks stably and efficiently. The process may specifically include but is not limited to steps 110 to 140.

[0028] Step 110: the main core sends a sleep instruction to the sub-core, and the sub-core and the main core prepare for sleep;

[0029] Step 120: When the sub-core and the main core are performing sleep preparation work, upon receiving the task execution instruction, the main core configures the main synchronization register to the first parameter value, sends a wake-up instruction to the sub-core, and performs wake-up preparation work;

[0030] Step 130: the sub-core receives the wake-up instruction, interrupts the sleep state, performs wake-up preparation, and configures the sub-synchronization register to the second parameter value;

[0031] Step 140: When the main core confirms that the sub-synchronization register is configured with the second parameter value, the main core configures the main synchronization register with the second parameter value, and the system enters the wake-up state.

[0032] The following elaborates on Steps 110 to 140 in detail.

[0033] It can be understood that under the architecture of a multi-core homogeneous chip system, the main core responsible for core scheduling and task processing specializes in running the front-end protocol code, and its core function is to receive and efficiently process various tasks initiated from the host side. At the same time, the main core is also responsible for the management of some peripheral modules. When the system enters the sleep state, the main core can turn off these peripheral modules to achieve the effect of reducing power consumption. The sub-core runs the back-end flash management code. When entering the sleep state, the sub-core is mainly responsible for turning off the hardware modules related to the flash to reduce power consumption. Since the main core is mainly responsible for the processing of front-end protocol transactions, it can sense the host's operation on the device in the first place. Therefore, the operations of the system entering sleep and wake-up are both initiated by the main core.

[0034] In a feasible embodiment, in a multi-core system, the sub-synchronization register and the main synchronization register are respectively used to indicate the current sleep states of the sub-core and the main core. They can both be configured according to the sleep states of the corresponding cores. Specifically, the main synchronization register can be configured with three different parameter values, and each parameter value corresponds to a specific sleep state of the main core: The first parameter value indicates that the main core is in the stopped sleep state, that is, the main core is ready to resume work from sleep; the second parameter value indicates that the main core is in the non-sleep state, and at this time the main core may be in the following two situations: one is that it is normally executing various tasks, such as performing data operations, processing requests from external devices, etc.; the other is that it is in a waiting or idle state, that is, it has completed the current task and is waiting for a new task to be assigned, or waiting for a specific external condition to be met (such as waiting for a cooperation signal from other cores, a data transmission completion signal from a peripheral device, etc.), and there is no actual task execution operation during this period. The third parameter value represents that the main core is in the sleep state (that is, completely enters the sleep state) to reduce power consumption. Similarly, the sub-synchronization register can also be configured with three parameter values, and the states of the sub-core represented by the parameter values correspond one-to-one with those of the main core: The first parameter value indicates that the sub-core is in the stopped sleep state; the second parameter value indicates that the sub-core is in the non-sleep state; the third parameter value indicates that the sub-core is in the sleep state. Through such a configuration method, the system can clearly and accurately master the sleep states of the main core and the sub-core, so as to achieve efficient inter-core synchronization and management.

[0035] In a feasible embodiment, in an actual usage scenario, when configuring parameters for the main synchronization register and the sub - synchronization register, corresponding status characteristic values can be written to these registers, and these status characteristic values are the parameter values mentioned above. Specifically, there are three parameter value configuration cases for both the main synchronization register and the sub - synchronization register. The status characteristic value corresponding to the first parameter value can be set to PM_STOP; the status characteristic value corresponding to the second parameter value can be set to PM_NONE; the status characteristic value corresponding to the third parameter value can be set to PM_FINISH. Through such a configuration of status characteristic values, the different states of the main core and the sub - core can be accurately indicated.

[0036] In a feasible embodiment, in step 110, when the system determines that it needs to enter the sleep state (i.e., the low - power state), the main core can act as the initiator to start the entire sleep process. Specifically, if the main core does not receive a command from the host within a preset duration (e.g., 20 milliseconds), the main core will send a sleep instruction to the sub - core through the inter - core communication module, thereby informing the sub - core that the system is about to enter the sleep state. After receiving the sleep instruction, the sub - core can carry out sleep preparation work. At the same time, the main core itself will also perform corresponding sleep preparation work. These preparation works may include saving the current working state, turning off some unnecessary modules or functions, etc., with the aim of minimizing power consumption after entering the sleep state.

[0037] In a feasible embodiment, in step 120, during the sleep preparation process of the main core and the sub - core, if the system receives an execution task instruction (e.g., a task instruction sent by the host), the wake - up process will be triggered. Specifically, when the main core senses a signal that the system needs to be woken up, the main core configures the main synchronization register to the first parameter value, indicating that it is in a stopped - sleep state, and sends a wake - up instruction to the sub - core, notifying the sub - core that the system needs to be woken up immediately to execute a new task. While sending the wake - up instruction, the main core starts its own wake - up preparation work, such as restarting peripheral modules, etc.

[0038] In a feasible embodiment, in step 130, after receiving the wake - up instruction sent by the main core, the sub - core immediately triggers interrupt sleep and exits the Wait For Interrupt (WFI) mode. Among them, the WFI mode can put the system core into the low - power state and can be woken up by an interrupt signal and restore the modules that have been turned off. This may include turning on the flash - related hardware modules, etc., to ensure that it can quickly respond to new tasks. After restoring the relevant hardware modules, the sub - core exits the sleep process and configures the sub - synchronization register to the second parameter value. This second parameter value is used to indicate that the sub - core is in a non - sleep state. By configuring the sub - synchronization register, the sub - core feeds back its own status information to the main core for subsequent synchronization operations.

[0039] In a feasible embodiment, in step 140, the main core can continuously monitor the value of the sub-synchronization register. When it is confirmed that the sub-synchronization register has been configured with the second parameter value, it indicates that the sub-core has completed the wake-up preparation work and is in a non-sleep state. At this time, the main core can also configure the main synchronization register with the second parameter value. This step realizes the synchronization of the states of the main core and the sub-core, ensuring that both cores are in a non-sleep state and have the same state. When the main core completes the configuration of the main synchronization register, the entire system officially enters the wake-up state and can start to normally execute the received tasks.

[0040] In a feasible embodiment, in order to keep the state of the main core synchronized with that of the sub-core, the main core can query the parameter value of the sub-synchronization register in the following two ways: On the one hand, the main core can periodically query the parameter value of the sub-synchronization register at a preset fixed period. This preset period can be flexibly adjusted according to the actual requirements and performance requirements of the system to ensure that the sub-core state information can be obtained at an appropriate time interval. On the other hand, when the sub-core updates the parameter value of the sub-synchronization register, it can actively send a message containing the updated parameter value to the main core. After receiving this message, the main core can immediately configure the main synchronization register according to the parameter value in the message. Through these two ways, the main core can obtain the state information of the sub-core in a timely and accurate manner, thus ensuring that the states of the main core and the sub-core are always consistent.

[0041] In a feasible embodiment, during the period when the sub-core performs the sleep preparation work, the sub-core can also continuously monitor the configuration state of the main synchronization register. If the sub-core confirms that the main synchronization register is configured with the second parameter value (indicating that the main core is in a non-sleep state but has not initiated a wake-up operation) or the third parameter value (meaning that the main core has entered the sleep state), the sub-core will continue to advance the sleep preparation work. When the sub-core completes all the sleep preparation work, it will configure its own sub-synchronization register with the third parameter value. The sub-synchronization register being configured with the third parameter value means that the sub-core has entered the sleep state. It can be further understood that when the sub-synchronization register presents the third parameter value, the sub-core immediately enters the Wait for Interrupt (WFI) mode and successfully switches to the low-power state to reduce energy consumption.

[0042] It should be noted that in this embodiment, before the system core enters the wait-for-interrupt mode, the module clock of the system can be turned off first to reduce unnecessary clock signal consumption. The WFI mode enables the system core to enter a low-power state and can be woken up by an interrupt signal. Among them, the module clock is the part that provides clock signals for a single or a group of specific modules. Turning it off only stops the modules related to this clock from working, while other parts of the system that do not depend on this module clock can still operate normally. It should be noted that considering the differences in hardware design, there may be multiple different types of sleep modes in the system. Different sleep modes correspond to different wake-up mechanisms. For example, some sleep modes may require specific hardware signals to wake up, while some may be triggered by software instructions. However, regardless of the sleep and wake-up methods adopted, the management method for realizing fast sleep and wake-up and fast mode transition demonstrated in this embodiment is universal and consistent, and can be effectively applied under various hardware designs.

[0043] In a feasible embodiment, during the sleep preparation work of the sub-core, once the sub-core confirms that the main synchronization register is configured with a first parameter value, it immediately stops the sleep preparation work and instead proceeds with the wake-up preparation work, including restoring the modules that have been turned off, etc. At the same time, the sub-core configures the sub-synchronization register with a second parameter value to indicate that it has exited the sleep state. On the contrary, if the sub-core monitors that the parameter value of the main synchronization register is configured with a second parameter value or a third parameter value, the sub-core continues with the sleep preparation work until the sleep preparation work is completed.

[0044] In a feasible embodiment, as Figure 2 shown, when the main core is performing sleep preparation work, the work process may include but is not limited to steps 210 to 220.

[0045] Step 210: Query the parameter value of the sub-synchronization register when the sleep preparation work is completed;

[0046] Step 220: When it is confirmed that the parameter value of the sub-synchronization register is the third parameter value, the main core configures the main synchronization register with the third parameter value, where configuring the main synchronization register with the third parameter value indicates that the main core is in the sleep state.

[0047] In a feasible embodiment, in step 210, during the process of the main core performing sleep preparation work, it can continuously monitor whether new task instructions arrive. Here, the task instructions can come from outside the system (such as instructions sent by the host side), or may be specific task requirements generated within the system. If no new task instructions arrive, the main core will continue with the sleep preparation work. When the sleep preparation work is completed, such as turning off unnecessary modules or functions, the main core can query the parameter value of the sub-synchronization register to understand the current state of the sub-core.

[0048] In a feasible embodiment, in step 220, after the main core queries the parameter value of the sub-synchronization register, it will make a judgment. If it is confirmed that the parameter value of the sub-synchronization register is the third parameter value, according to the previous setting, the third parameter value indicates that the sub-core is in the sleep state. This means that the sub-core has completed the sleep preparation work and entered the sleep state. At this time, the main core can enter the sleep state. It should be noted that when the main core confirms that the sub-core is already in the sleep state (i.e., the parameter value of the sub-synchronization register is the third parameter value), the main core can immediately configure its own main synchronization register to the third parameter value. In this way, the main core indicates to other parts of the system that it has also entered the sleep state. This ensures the state synchronization of each core in the entire multi-core system and avoids system anomalies caused by inconsistent states.

[0049] In a feasible embodiment, when the main core is in the sleep state, if it receives an instruction, the main core will immediately interrupt the sleep state and execute the corresponding instruction. The process of the main core executing the instruction is as follows: If the received instruction is a sleep instruction, after the current instruction is executed, the main core enters the sleep state again. If the received instruction is a task execution instruction, the main core first configures the main synchronization register to the first parameter value. Then, the main core sends a wake-up instruction to the sub-core through the inter-core communication module to notify the sub-core to prepare to resume work. At the same time, the main core itself performs wake-up preparation work, such as re-initializing relevant hardware modules, restoring the previously saved working state, loading necessary data required for task execution, etc., to ensure that it can quickly respond to tasks.

[0050] See Figure 3 , Figure 3 is the overall flowchart of the sleep and wake-up of the system provided by an embodiment of the present application. In the figure, CPU0 refers to the main core, and CPU1 refers to the sub-core.

[0051] The entire process is as follows: If CPU0 does not receive a command sent by the HOST side within the preset duration, it can send a sleep instruction to CPU1 through the inter-core communication module to notify it to perform sleep preparation work.

[0052] CPU0 side operation

[0053] After CPU0 notifies CPU1 to start sleeping, it also synchronously carries out the preparation work before sleeping. During this period, CPU0 will continuously query whether there is a task sent by the HOST (i.e., the host side):

[0054] No task situation: If there is no task, CPU0 will turn off other peripheral modules one by one (such as non-protocol control modules, non-flash control modules, etc.). After completing the preparations before entering the sleep state, CPU0 will wait for CPU1 to complete the sleep process, specifically by waiting for the status characteristic value in the synchronization register of CPU1 to be set to PM_FINISH. When it detects that CPU1 enters the WFI mode, CPU0 also enters the WFI mode.

[0055] Task situation: If there is a task sent by the HOST currently, CPU0 will set the status characteristic value in its own synchronization register to PM_STOP, which indicates that CPU0 stops sleeping. Then, CPU0 sends a wake-up instruction to CPU1 through the inter-core communication module, causing CPU1 to trigger an interrupt and then exit the WFI mode, thus exiting the sleep state. Subsequently, CPU0 resumes the modules that have been turned off and waits for CPU1 to exit the sleep process, that is, waits for the status characteristic value in the synchronization register of CPU1 to be set to PM_NONE. When CPU1 completes the operation of exiting the sleep state, CPU0 also sets its own status characteristic value to PM_NONE. At this time, the system completely exits the sleep state and can start executing the task sent by the HOST.

[0056] Operations on the CPU1 side

[0057] After receiving the sleep instruction sent by CPU0, CPU1 starts to perform the preparations for sleep and continuously queries the status characteristic value in the current CPU0 synchronization register:

[0058] CPU0 has not exited the sleep process: If CPU0 has not exited the sleep process currently (that is, the status characteristic value of CPU0 is not PM_STOP), CPU1 will turn off the modules related to flash control one by one. After completing the preparations before entering the sleep state, it sets the status characteristic value in its own synchronization register to PM_FINISH, and then enters the sleep state.

[0059] CPU0 exits the sleep process: When CPU1 queries that the status characteristic value of CPU0 becomes PM_STOP, if CPU1 has not completed the sleep and entered the sleep state at this time, it will immediately stop the sleep preparations; if CPU1 is already in the sleep mode, when it receives the wake-up instruction sent by CPU0, CPU1 will trigger an interrupt and then exit the WFI mode. Subsequently, CPU1 will sequentially resume each module that was turned off for entering the sleep state. After completing the module resumption work, CPU1 will set the status characteristic value in its own synchronization register to PM_NONE. Through this series of operations, CPU1 successfully exits the sleep process and re-enters the normal working state, ready to respond to subsequent tasks.

[0060] It should be noted that there is no limit on the number of sub-cores in this embodiment. The system can include two, three or even more sub-cores, and each sub-core is equipped with a corresponding sub-synchronization register. Regardless of the number of sub-cores, inter-core synchronization can be achieved through parameter configuration between its own sub-synchronization register and the main synchronization register of the main core. This synchronization mechanism is universal and will not fail due to changes in the number of sub-cores. For example, when the system includes one main core and two sub-cores, the same inter-core synchronization rules are followed between the main core and these two sub-cores. After the main core sends a sleep or wake-up instruction, the two sub-cores perform corresponding sleep or wake-up operations respectively according to the parameter configuration of their own sub-synchronization registers. At the same time, the main core will monitor the parameter values of the sub-synchronization registers of the two sub-cores to ensure that the states of all cores are consistent, so as to achieve the stable operation of the entire system.

[0061] An embodiment of the present application also discloses a computer device, where the computer device includes a processor, a memory, and a computer program stored on the memory and executable by the processor. When the computer program is executed by the processor, it implements the sleep and wake-up methods of the multi-core homogeneous chip system as described above.

[0062] An embodiment of the present application also discloses a computer-readable storage medium, in which a program executable by a processor is stored. The program executable by the processor is used to execute the sleep and wake-up methods of the multi-core homogeneous chip system as described above when executed by the processor.

[0063] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A sleep and wake-up method for a multi-core homogeneous chip system, characterized in that: The multi-core homogeneous chip system includes a main core and at least one sub-core, the main core is provided with a main synchronization register, and the sub-core is provided with a sub-synchronization register, and the method includes: The main core sends a sleep instruction to the sub-core, and the sub-core and the main core perform sleep preparation work; During the process of the sub-core and the main core performing sleep preparation work, when receiving an execution task instruction, the main core configures the main synchronization register to a first parameter value, sends a wake-up instruction to the sub-core, and performs wake-up preparation work; The sub-core receives the wake-up instruction, interrupts the sleep state and performs wake-up preparation, and configures the sub-synchronization register to a second parameter value; When the main core confirms that the sub-synchronization register is configured as the second parameter value, the main core configures the main synchronization register as the second parameter value, and the system enters a wake-up state; Among them, the main synchronization register is configured with the first parameter value to indicate that the main core is in a stopped sleep state, and the sub-synchronization register is configured with the second parameter value to indicate that the sub-core is in a non-sleep state; the main synchronization register is configured with the second parameter value to indicate that the main core is in a non-sleep state.

2. The sleep and wake-up method of a multi-core homogeneous chip system according to claim 1, characterized in that: During the process of the sub-core performing the sleep preparation work, the method includes: If the sub-core confirms that the main synchronization register is configured as the second parameter value or the third parameter value, the sub-core continues the sleep preparation work, and when the sleep preparation work is completed, the sub-core configures the sub-synchronization register as the third parameter value; The sub-synchronization register is configured as the third parameter value to represent that the sub-core is in a dormant state.

3. The sleep and wake-up method of a multi-core homogeneous chip system according to claim 2, characterized in that: During the process of the sub-core performing the sleep preparation work, the method further includes: When the sub-core confirms that the main synchronization register is configured as the first parameter value, the sub-core performs wake-up preparation, configures the sub-synchronization register as the second parameter value, and the sub-core exits the sleep state.

4. The sleep and wake-up method of a multi-core homogeneous chip system according to claim 2, characterized in that: During the process of the sub-core performing the sleep preparation work, the method further includes: In the case where the sleep preparation work is not completed, the sub-core queries the parameter value of the main synchronization register; When the parameter value of the master synchronization register is configured as the second parameter value or the third parameter value, the sub-core continues the sleep preparation work.

5. The sleep and wake-up method of a multi-core homogeneous chip system according to claim 2, characterized in that: During the process of the main core performing sleep preparation work, the method includes: When the sleep preparation work is completed, querying the parameter value of the sub-synchronization register; When confirming that the parameter value of the sub-synchronization register is the third parameter value, the main core configures the main synchronization register to the third parameter value; The master synchronization register is configured such that the third parameter value indicates that the master core is in a sleep state.

6. The sleep and wake-up method of a multi-core homogeneous chip system according to claim 4, characterized in that: In the case that the main core is in a sleep state, when the main core receives an instruction, the main core interrupts the sleep state and executes the instruction.

7. The sleep and wake-up method of a multi-core homogeneous chip system according to claim 6, characterized in that: The main core executes the instruction, including: If the instruction is a sleep state instruction, the main core enters the sleep state again; If the instruction is the execution task instruction, the main core configures the main synchronization register to the first parameter value, sends a wake-up instruction to the sub-core, and performs wake-up preparation work at the same time.

8. The method according to any one of claims 1 to 7, characterized in that: The main core queries the parameter value of the sub-synchronous register by periodic query, or when the sub-core updates the parameter value of the sub-synchronous register, the main core receives the update message sent by the sub-core and configures the parameter value of the main synchronous register accordingly according to the update message.

9. A computer device comprising a processor, a memory, and a computer program stored in the memory and executable by the processor, characterized in that: When the computer program is executed by the processor, the sleep and wake-up method of the multi-core homogeneous chip system as described in any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to execute the sleep and wake-up method of the multi-core homogeneous chip system as described in any one of claims 1 to 8 when executed by the processor.

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