Chip design retention time violation automatic correction method and system, medium and product

Abstract

The invention discloses a chip design hold time violation automatic correction method and system, a medium and a product, and the method comprises the steps: calculating a ratio between a setting time margin and an absolute value of a hold time violation value according to an end point pin of a time sequence path of the hold time violation of the chip design; selecting different insertion points to insert the delay unit or the buffer unit according to whether the ratio is greater than a preset value K; and then finishing one-time retention time violation correction, detecting and reporting whether a time sequence path of retention time violation exists or not, and if yes, repeating the process until all retention time violation paths in the design are repaired. The invention aims to realize the automatic correction of the retention time violation of chip design, make up for the defect that the existing engineering renovation tool can only automatically repair the retention time violation with sufficient time margin at the end point of the time sequence path, and can automatically and efficiently repair various retention time violations with sufficient and insufficient time margin. And the chip design achieves the purpose of time sequence convergence as soon as possible.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit physical design, and in particular to a chip design hold time violation automatic correction method, system, medium and product. Background Art

[0002] Static timing analysis (STA) is an important part of integrated circuit physical design. It is used to verify whether the chip design meets the timing requirements. Static timing analysis is a timing verification method that does not rely on test vectors. It analyzes all timing paths in the circuit, calculates the propagation delay of the signal on these paths, and checks whether the setup time and hold time of the signal meet the constraint requirements.

[0003] Setup time refers to the minimum time that the input data must remain stable before the clock edge (rising edge or falling edge) arrives. Setup slack refers to the difference between the actual setup time and the required setup time. When the actual setup time is greater than the required setup time, the setup slack is positive, indicating that the timing requirements are met; conversely, the setup slack is negative, indicating that the timing requirements are not met and there is a setup time violation. Hold time refers to the shortest time that the input data needs to remain unchanged after the clock edge (rising edge or falling edge) is triggered. When the data arrival time is less than the time the data needs to be held, a hold time violation occurs.

[0004] In chip design, if there are setup time violations that are not fixed, the final manufactured chip will not reach the expected operating frequency; if there are hold time violations that are not fixed, the produced chip will not work properly. Therefore, before the chip is finally taped out, all setup time and hold time violations must be fixed. In particular, the priority of holding time violation repair is higher than that of setup time violation repair. At present, hold time violation repair is usually a combination of engineering renovation tools (ECO tools) in electronic design automation tools and manual repair. The engineering renovation tools repair most of the hold time violations, and the remaining few rely on the experience of physical design engineers to repair them one by one. There may be a problem of low repair efficiency, which affects the design convergence time. Summary of the invention

[0005] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a method, system, medium and product for automatically correcting hold time violations in chip design are provided. The present invention aims to automatically and efficiently repair hold time violations existing in the design by obtaining hold time violation points in static timing analysis, automatically analyzing and determining the number of delay units or buffer units to be inserted to repair hold time violations and the locations of insertion points.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A method for automatically correcting a chip design hold time violation comprises the following steps: S1, obtain the endpoint pins of the timing path with hold time violation from the static timing analysis report of the chip design and put them into the list; S2, traverse and select an endpoint pin from the list, obtain the hold time violation value hold_slack of the endpoint pin and the setup time margin setup_slack of the point; calculate the ratio between the setup time margin setup_slack and the absolute value hold_slack_abs of the hold time violation value hold_slack; S3, judging whether the ratio is greater than a preset value K, if the ratio is greater than the preset value K, taking the end point pin as the insertion point and jumping to step S5, otherwise jumping to step S4; S4, obtain all fan-in pins with hold time violations in the destination pin, traverse to obtain the setup time margin passing through each fan-in pin, and select a pin with a positive and maximum setup time margin as an insertion point, and jump to step S5; S5, determining the type and quantity of the delay unit or buffer unit to be inserted at the insertion point according to the hold time violation value hold_slack, obtaining the physical position coordinates of the insertion point, inserting a corresponding number of delay units or buffer units at the physical position coordinates, and jumping to step S6; S6, determine whether the list of timing path endpoints has been traversed, if not, jump to step S2; otherwise, jump to step S7; S7, first complete the hold time violation correction for the chip design, then check whether there are still timing paths with hold time violations in the chip design, if yes, jump to step S1, otherwise determine that all timing paths with hold time violations in the chip design are repaired, end and exit.

[0007] Optionally, obtaining the hold time violation value hold_slack of the endpoint pin and the setup time margin setup_slack of the point in step S2 refers to obtaining them in a static timing analysis tool.

[0008] Optionally, step S4 includes: S4.1, put all fan-in pins to the destination pin into a list all_fanin_pins; S4.2, traverse and obtain the hold time margin from each fan-in pin to the destination pin in the list all_fanin_pins, and put the fan-in pins with negative hold time margin into a list hold_fanin_pins; S4.3, traverse to obtain the setup time margin of each fan-in pin in the list hold_fanin_pins, and select a fan-in pin with a positive and maximum setup time margin as the insertion point.

[0009] Optionally, step S5 includes: S5.1, determine whether the absolute value hold_slack_abs of the hold time violation value hold_slack of the endpoint pin is greater than the preset maximum delay unit delay value D, if so, jump to step S5.2; otherwise, jump to step S5.3; S5.2, calculate the ratio between the absolute value hold_slack_abs of the hold time violation value hold_slack of the endpoint pin and the preset maximum delay unit delay value D and round it down to get the number N of inserted maximum delay units, then calculate the remaining value hold_slack_left of the hold time violation after inserting N maximum delay units, and jump to step S5.4; S5.3, determining a delay unit or buffer unit type to be inserted according to the absolute value hold_slack_abs value of the hold time violation value hold_slack of the endpoint pin, obtaining the physical position coordinates of the current pin, and inserting a delay unit or buffer unit of a determined type at the physical position coordinates; S5.4, determine the type of a delay unit or buffer unit to be inserted according to the hold_slack_left value of the remaining hold time violation after inserting N maximum delay units, obtain the physical position coordinates of the current pin, insert N maximum delay units and 1 other type of delay unit or buffer unit at the physical position coordinates, the maximum delay unit refers to a delay unit with the largest delay value among multiple delay units and a preset maximum delay unit delay value D, and the other type of delay unit refers to a delay unit other than the maximum delay unit among multiple delay units.

[0010] Optionally, the calculation function expression of the remaining value hold_slack_left of the hold time violation after inserting N maximum delay units in step S5.2 is: hold_slack_left=hold_slack_abs- N×D; Wherein, hold_slack_abs is the absolute value of the hold time violation value hold_slack of the endpoint pin, N is the number of inserted maximum delay units, and D is the preset maximum delay unit delay value.

[0011] Optionally, completing one hold time violation correction for the chip design in step S7 refers to performing a cell position legalization operation and a local routing operation in a placement and routing tool to complete one hold time violation correction for the chip design.

[0012] Optionally, detecting whether the chip design still has a timing path with a hold time violation in step S7 refers to detecting the chip design in a static timing tool to determine whether the chip design still has a timing path with a hold time violation.

[0013] In addition, the present invention also provides a chip design hold time violation automatic correction system, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the chip design hold time violation automatic correction method.

[0014] In addition, the present invention also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the chip design hold time violation automatic correction method through a processor.

[0015] In addition, the present invention also provides a computer program product, including a computer program or instructions, wherein the computer program or instructions are programmed or configured to execute the chip design hold time violation automatic correction method through a processor.

[0016] Compared with the prior art, the present invention mainly has the following advantages: the method of the present invention includes calculating the ratio between the setup time margin and the absolute value of the hold time violation value for the endpoint pin of the timing path of the hold time violation in the chip design, and selecting different insertion points to insert a delay unit or a buffer unit according to whether the ratio is greater than a preset value K; then completing a hold time violation correction, and then detecting and reporting whether there are still timing paths with hold time violations, and if there are, repeating the above process until all hold time violation paths in the design are repaired. The present invention automatically analyzes and determines the number of delay units or buffer units to be inserted and the position of the insertion point to repair the hold time violation, automatically and efficiently repairs the hold time violation in the design, making up for the deficiency of the existing engineering renovation tools that can only automatically repair the hold time violation with sufficient setup time margin at the endpoint of the timing path, and effectively solves the problem of low efficiency in manually repairing the hold time violation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the basic flow of the method of the embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of a flow chart of obtaining fan-in pins with sufficient establishment time margin in step S4 of the method according to an embodiment of the present invention.

[0019] Figure 3 A schematic diagram of fan-in pins with sufficient time margin is established in an embodiment of the present invention.

[0020] Figure 4 Schematic diagram of the process of step S5 in the embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of an example of inserting a delay unit and a buffer unit in a method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] like Figure 1 As shown, the chip design hold time violation automatic correction method of this embodiment includes the following steps: S1, obtain the endpoint pins of the timing path with hold time violation from the static timing analysis report of the chip design and put them into the list; S2, traverse and select an endpoint pin from the list, obtain the hold time violation value hold_slack of the endpoint pin and the setup time margin setup_slack of the point; calculate the ratio between the setup time margin setup_slack and the absolute value hold_slack_abs of the hold time violation value hold_slack; S3, judging whether the ratio is greater than a preset value K, if the ratio is greater than the preset value K, taking the end point pin as the insertion point and jumping to step S5, otherwise jumping to step S4; S4, obtain all fan-in pins with hold time violations in the destination pin, traverse to obtain the setup time margin passing through each fan-in pin, and select a pin with a positive and maximum setup time margin as an insertion point, and jump to step S5; S5, determining the type and quantity of the delay unit or buffer unit to be inserted at the insertion point according to the hold time violation value hold_slack, obtaining the physical position coordinates of the insertion point, inserting a corresponding number of delay units or buffer units at the physical position coordinates, and jumping to step S6; S6, determine whether the list of timing path endpoints has been traversed, if not, jump to step S2; otherwise, jump to step S7; S7, first complete the hold time violation correction for the chip design, then check whether there are still timing paths with hold time violations in the chip design, if yes, jump to step S1, otherwise determine that all timing paths with hold time violations in the chip design are repaired, end and exit.

[0023] As an optional implementation manner, obtaining the hold time violation value hold_slack of the endpoint pin and the setup time margin setup_slack of the point in step S2 refers to obtaining them in a static timing analysis tool.

[0024] like Figure 2 As shown, step S4 includes: S4.1, put all fan-in pins to the destination pin into a list all_fanin_pins; S4.2, traverse and obtain the hold time margin from each fan-in pin to the destination pin in the list all_fanin_pins, and put the fan-in pins with negative hold time margin into a list hold_fanin_pins; S4.3, traverse to obtain the setup time margin of each fan-in pin in the list hold_fanin_pins, and select a fan-in pin with a positive and maximum setup time margin as the insertion point.

[0025] Figure 3 A schematic diagram of fan-in pins with sufficient time margin is established in this embodiment. Figure 3 As shown, there are three fan-in pins to the D input end of the timing path endpoint flip-flop FF2: the B end of the two-input AND gate AND2, the A end of the three-input OR gate and the I end of the inverter INV. In the static timing analysis tool, the hold time margins from these three fan-in pins to the D end of the endpoint FF2 are all negative values, and the setup time margin from the B end of the two-input AND gate AND2 is the largest. Therefore, the B end pin of the two-input AND gate AND2 is selected as the fan-in pin of the buffer unit or delay unit to be inserted.

[0026] like Figure 4 As shown, step S5 includes: S5.1, determine whether the absolute value hold_slack_abs of the hold time violation value hold_slack of the endpoint pin is greater than the preset maximum delay unit delay value D, if so, jump to step S5.2; otherwise, jump to step S5.3; S5.2, calculate the ratio between the absolute value hold_slack_abs of the hold time violation value hold_slack of the endpoint pin and the preset maximum delay unit delay value D and round it down to get the number N of inserted maximum delay units, then calculate the remaining value hold_slack_left of the hold time violation after inserting N maximum delay units, and jump to step S5.4; S5.3, determining a delay unit or buffer unit type to be inserted according to the absolute value hold_slack_abs value of the hold time violation value hold_slack of the endpoint pin, obtaining the physical position coordinates of the current pin, and inserting a delay unit or buffer unit of a determined type at the physical position coordinates; S5.4, determine the type of a delay unit or buffer unit to be inserted according to the hold_slack_left value of the remaining hold time violation after inserting N maximum delay units, obtain the physical position coordinates of the current pin, insert N maximum delay units and 1 other type of delay unit or buffer unit at the physical position coordinates, the maximum delay unit refers to a delay unit with the largest delay value among multiple delay units and a preset maximum delay unit delay value D, and the other type of delay unit refers to a delay unit other than the maximum delay unit among multiple delay units.

[0027] As an optional implementation, in step S5.2 of this embodiment, the calculation function expression of the remaining value hold_slack_left of the hold time violation after inserting N maximum delay units is: hold_slack_left=hold_slack_abs-N×D; Wherein, hold_slack_abs is the absolute value of the hold time violation value hold_slack of the endpoint pin, N is the number of inserted maximum delay units, and D is the preset maximum delay unit delay value.

[0028] Figure 5 FIG. 1 is a schematic diagram showing an example of inserting a delay unit and a buffer unit in the method of this embodiment. Figure 5 As shown, suppose the absolute value of the hold time violation from the A end of the three-input OR gate OR3 to the D end of the end point FF2 is 210ps, and the delays of the three delay units DLY1, DLY2, and DLY4 are 25ps, 50ps, and 100ps respectively, that is, the delay D of the maximum delay unit DLY4 is 100ps, and the delay of the buffer unit BUF1 is 10ps. Because the absolute value of the hold time violation value of the current pin is greater than the delay value of the maximum delay unit, according to calculation, it is necessary to insert two maximum delay units DLY4 at the A end of the three-input OR gate OR3, and the remaining value of the hold time violation hold_slack_left is 10ps. Therefore, it is necessary to insert another buffer unit BUF1 at the A end to fix the hold time violation.

[0029] As an optional implementation, in step S7 of this embodiment, completing one hold time violation correction for the chip design refers to executing a cell position legalization operation and a local routing operation in a placement and routing tool to complete one hold time violation correction for the chip design.

[0030] As an optional implementation, in step S7 of this embodiment, detecting whether the chip design still has a timing path with a hold time violation refers to detecting the chip design in a static timing tool to determine whether the chip design still has a timing path with a hold time violation.

[0031] In summary, the automatic correction method for hold time violation in chip design of this embodiment includes obtaining the end point pin of the timing path with hold time violation from the static timing analysis report and putting it into a list; traversing and selecting a timing path end point pin from the list, obtaining the hold time violation value of the point and the setup time margin of the point; calculating the ratio between the setup time margin and the absolute value of the hold time violation value, if the ratio is greater than a preset value K (the value is determined empirically according to different processes), determining the type and number of delay units or buffer units to be inserted according to the hold time violation value, obtaining the physical position coordinates of the point, and inserting the corresponding number of delay units or buffer units at the physical position; if the ratio is less than K, obtaining the hold time violation value in the end point pin. All fan-in pins with hold time violation are traversed to obtain the setup time margin passing through each fan-in pin, and the one with the positive and largest setup time margin among all fan-in pins is selected. The type and number of delay units or buffer units to be inserted are determined according to the hold time violation value, and the physical position coordinates of the fan-in pin are obtained, and the corresponding number of delay units or buffer units are inserted at the physical position; traverse until the list of terminal pins of all timing paths is empty; perform unit position legalization operations and local routing operations in the layout and routing tool, that is, complete one hold time violation correction, and then detect and report whether there are still timing paths with hold time violation in the static timing analysis tool. If there are, repeat the above process until all hold time violation paths in the design are repaired. The automatic correction method for hold time violations in chip design of the present embodiment obtains hold time violation points in static timing analysis, automatically analyzes and determines the number of delay units or buffer units to be inserted to repair the hold time violation and the positions of the insertion points, and automatically and efficiently repairs the hold time violations existing in the design. The automatic correction method for hold time violations in chip design of the present embodiment makes up for the deficiency that existing engineering renovation tools can only automatically repair hold time violations with sufficient establishment time margin at the endpoint of the timing path, and effectively solves the problem of low efficiency in manual repair of hold time violations.

[0032] In addition, this embodiment also provides a chip design hold time violation automatic correction system, including a microprocessor and a memory connected to each other, and the microprocessor is programmed or configured to execute the chip design hold time violation automatic correction method.

[0033] In addition, this embodiment also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the chip design hold time violation automatic correction method through a processor.

[0034] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the chip design hold time violation automatic correction method through a processor.

[0035] Those skilled in the art should understand that the technical solution that the present invention can provide can be in the form of a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment that combines software and hardware. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0036] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A method for automatically correcting chip design hold time violations, characterized in that: The steps include: S1, obtain the endpoint pins of the timing path with hold time violation from the static timing analysis report of the chip design and put them into the list; S2, traverse and select an endpoint pin from the list, obtain the hold time violation value hold_slack of the endpoint pin and the setup time margin setup_slack of the point; calculate the ratio between the setup time margin setup_slack and the absolute value hold_slack_abs of the hold time violation value hold_slack; S3, judging whether the ratio is greater than a preset value K, if the ratio is greater than the preset value K, taking the end point pin as the insertion point and jumping to step S5, otherwise jumping to step S4; S4, obtain all fan-in pins with hold time violations in the destination pin, traverse to obtain the setup time margin passing through each fan-in pin, and select a pin with a positive and maximum setup time margin as an insertion point, and jump to step S5; S5, determining the type and quantity of the delay unit or buffer unit to be inserted at the insertion point according to the hold time violation value hold_slack, obtaining the physical position coordinates of the insertion point, inserting a corresponding number of delay units or buffer units at the physical position coordinates, and jumping to step S6; S6, determine whether the list of end points of the timing path has been traversed, if not, jump to step S2; Otherwise, jump to step S7; S7, first complete the hold time violation correction for the chip design, then check whether there are still timing paths with hold time violations in the chip design, if yes, jump to step S1, otherwise determine that all timing paths with hold time violations in the chip design are repaired, end and exit.

2. The chip design hold time violation automatic correction method according to claim 1, characterized in that: In step S2, obtaining the hold time violation value hold_slack of the endpoint pin and the setup time margin setup_slack of the point refers to obtaining them in a static timing analysis tool.

3. The chip design hold time violation automatic correction method according to claim 1, characterized in that: Step S4 includes: S4.1, put all fan-in pins to the destination pin into a list all_fanin_pins; S4.2, traverse and obtain the hold time margin from each fan-in pin to the destination pin in the list all_fanin_pins, and put the fan-in pins with negative hold time margin into a list hold_fanin_pins; S4.3, traverse to obtain the setup time margin of each fan-in pin in the list hold_fanin_pins, and select a fan-in pin with a positive and maximum setup time margin as the insertion point.

4. The chip design hold time violation automatic correction method according to claim 1, characterized in that: Step S5 includes: S5.1, determine whether the absolute value hold_slack_abs of the hold time violation value hold_slack of the endpoint pin is greater than the preset maximum delay unit delay value D, if so, jump to step S5.2; otherwise, jump to step S5.3; S5.2, calculate the ratio between the absolute value hold_slack_abs of the hold time violation value hold_slack of the endpoint pin and the preset maximum delay unit delay value D and round it down to get the number N of inserted maximum delay units, then calculate the remaining value hold_slack_left of the hold time violation after inserting N maximum delay units, and jump to step S5.4; S5.3, determining a delay unit or buffer unit type to be inserted according to the absolute value hold_slack_abs value of the hold time violation value hold_slack of the endpoint pin, obtaining the physical position coordinates of the current pin, and inserting a delay unit or buffer unit of a determined type at the physical position coordinates; S5.4, determine the type of a delay unit or buffer unit to be inserted according to the hold_slack_left value of the remaining hold time violation after inserting N maximum delay units, obtain the physical position coordinates of the current pin, insert N maximum delay units and 1 other type of delay unit or buffer unit at the physical position coordinates, the maximum delay unit refers to a delay unit with the largest delay value among multiple delay units and a preset maximum delay unit delay value D, and the other type of delay unit refers to a delay unit other than the maximum delay unit among multiple delay units.

5. The chip design hold time violation automatic correction method according to claim 4, characterized in that: The calculation function expression of the remaining value hold_slack_left of the hold time violation after inserting N maximum delay units in step S5.2 is: hold_slack_left=hold_slack_abs- N×D; Wherein, hold_slack_abs is the absolute value of the hold time violation value hold_slack of the endpoint pin, N is the number of inserted maximum delay units, and D is the preset maximum delay unit delay value.

6. The chip design hold time violation automatic correction method according to claim 1, characterized in that: The step S7 of completing one hold time violation correction for the chip design refers to executing a cell position legalization operation and a local routing operation in a placement and routing tool to complete one hold time violation correction for the chip design.

7. The chip design hold time violation automatic correction method according to claim 1, characterized in that: Detecting whether the chip design still has a timing path with a hold time violation in step S7 refers to detecting the chip design in a static timing tool to determine whether the chip design still has a timing path with a hold time violation.

8. A chip design hold time violation automatic correction system, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the chip design hold time violation automatic correction method as claimed in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the chip design hold time violation automatic correction method according to any one of claims 1 to 7 through a processor.

10. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the chip design hold time violation automatic correction method according to any one of claims 1 to 7 through a processor.

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