Method, device and equipment for calculating maximum time delay capable of being supported by DRAM (Dynamic Random Access Memory) system

Abstract

The invention discloses a calculation method, device and equipment for maximum time delay supported by a DRAM (Dynamic Random Access Memory) system, and relates to the technical field of storage, the method comprises the following steps: building a simulation environment, a simulation circuit of the simulation environment comprising an RDL (Registered Description Language) model, an IBIS IO (International IBIS Input / Output) model and a DFE (Differential Feedback Establishment) model; setting ODT parameters so as to independently simulate the two Ranks based on the established simulation environment, and obtaining DQ and DMI time domain waveforms; according to the method, DQ and DMI time domain waveforms are processed based on a WCK Trigger mode, an eye diagram is generated, and Timing Margin and the maximum tWCK2CKRank2Rank are obtained through calculation according to the eye diagram. According to the invention, accurate calculation of the maximum time delay can be realized.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a method, device and apparatus for calculating a maximum delay that a DRAM system can support. Background Art

[0002] LPDDR5 SDRAM (Low Power Double Data Rate 5 SDRAM, a high-performance, low-power memory technology designed for mobile devices) uses two clocks with different frequencies, WCK (write clock) and CK (address and command clock). The frequency of WCK is four times or twice that of CK. WCK is the DQ (data signal) data clock, and CK is the command and address clock. Before sending a WRITE (write) or READ (degree) command, it is necessary to initiate a WCK2CK Sync operation (synchronous operation between WCK and CK) through a CAS command (a mechanism used to ensure cache data consistency and security) to align the phases of WCK and CK inside the SDRAM (Synchronous Dynamic Random Access Memory) to prepare for DQ data transmission.

[0003] LPDDR5 (a memory technology) provides a Write Leveling function, which continuously adjusts the WCK phase on the SoC (System on Chip) side during the DDR Trainin (DDR memory training process) phase to align the WCK and CK clocks, determine the best WCK Delay (delay time between the WCK signal and the DQ signal), recorded as WCKTxDly, and directly use WCKTxDly for WCK2CK Sync before subsequent read and write operations. After WCK2CK Sync is completed, the WCK sampled DQ signal has the best Margin (time redundancy).

[0004] For dual-rank SDRAM (Rank is a group of DRAM chips connected to the same chip select), WCK and CK clocks are connected to both ranks at the same time. SoC needs to access both ranks and perform WCK2CK Sync on both ranks. There is a difference between the best WCKTxDly obtained after DDR Training between one rank and the other rank, which is determined by the characteristic parameter tWCK2CK_Rank2Rank of DRAM (Dynamic Random Access Memory). tWCK2CK_Rank2Rank is a characteristic parameter related to timing parameters, which is usually used to describe the timing relationship between WCK and CK in DDR5 DRAM, that is, the timing delay from WCK to CK in Rank-to-Rank operation.

[0005] When accessing dual-rank SDRAM, there are two ways to handle WCK2CK Sync. One is to perform WCK2CK Sync on another Rank after one Rank completes the DQburst operation, and each Rank uses its own WCKTxDly value. A WCK2CK Sync is performed before each read and write, so there is a certain performance loss in the LPDDR5 system.

[0006] Performance is an important indicator of DDR (double rate synchronous dynamic random access memory). In order to improve system performance, the LPDDR5 system needs to be in WCK always on mode (WCK continuous activation mode). At this time, the two ranks share the same WCKTxDly, and only one WCK2CK Sync operation is required. However, this setting cannot meet the optimal WCK Delay value of the two ranks at the same time, resulting in Margin loss of the DQ signals of the two ranks.

[0007] Therefore, for a SoC-LPDDR5 DRAM system, SI simulation (signal integrity simulation) must be used to determine whether the eye diagram of the DQ signal meets the design requirements. However, the existing SI simulation cannot simulate the DRAM's tWCK2CK_Rank2Rank parameter. The SI simulation of each Rank is independent, and there is no unified standard to quantify whether the SoC-DRAM system can work stably in the WCK always on mode. At the same time, the simulation tool often uses the UI (time length of a code element) Trigger method to generate the DQ eye diagram, which is different from the process of using WCK on the chip to sample the data signal to determine the actual eye diagram. Summary of the invention

[0008] The present application provides a method, device and equipment for calculating the maximum delay that a DRAM system can support, which can achieve accurate calculation of the maximum delay.

[0009] In a first aspect, an embodiment of the present application provides a method for calculating a maximum latency that a DRAM system can support, and the method for calculating a maximum latency that a DRAM system can support includes: Building a simulation environment, wherein the simulation circuit of the simulation environment includes an RDL model, an IBIS IO model, and a DFE model; Set ODT parameters to simulate two ranks independently based on the built simulation environment to obtain DQ and DMI time domain waveforms; The DQ and DMI time domain waveforms are processed based on the WCK Trigger method to generate an eye diagram. According to the eye diagram, the Timing Margin and the maximum tWCK2CK_Rank2Rank are calculated.

[0010] In combination with the first aspect, in one implementation, The link structure of the simulation circuit includes a SoC IBIS model, a SoC PKG model, a PCB model, and a Dram PKG model connected in sequence, and the Dram PKG model is also connected to two DRAM IBIS models, wherein one of the two DRAM IBIS models corresponds to one of the two Ranks, and the other DRAM IBIS model corresponds to the other of the two Ranks.

[0011] In combination with the first aspect, in one implementation, The SoC IBIS model is used to describe the electrical behavior of the DDR interface input / output buffer of the SoC; The SoC PKG model is an S-parameter model of the SoC package, which characterizes the high-frequency transmission characteristics of the SoC package structure; The PCB model is an S parameter model of the PCB; The Dram PKG model is an S parameter model of DRAM packaging, which is used to quantify the impact of DRAM chip packaging on signals; The DRAM IBIS model is used to simulate the driver and receiver behaviors of the DRAM chip interface.

[0012] In combination with the first aspect, in one implementation, the ODT parameters are specifically set as follows: When simulating one of the two ranks, the ODT value of the DRAM IBIS model corresponding to the Rank is selected according to the transmission line impedance, and the ODT of the DRAM IBIS model corresponding to the other Rank is turned off.

[0013] In combination with the first aspect, in one implementation, the WCK Trigger-based method for processing DQ and DMI time domain waveforms and generating eye diagrams specifically includes: According to the WCK time domain waveform, the DQ time domain waveform is sliced ​​according to the time length of a complete cycle of the WCK time domain waveform, and the DQ time domain waveform is divided into a plurality of DQ time domain waveform segments, wherein a complete cycle of the WCK time domain waveform includes a first transition edge, a level, a second transition edge, a level, and a third transition edge; Each DQ time domain waveform segment is aligned at the second transition edge time and overlapped to generate an eye diagram.

[0014] In combination with the first aspect, in one implementation, after generating the eye diagram, the method further includes: Determine the unified Vref based on all DQ eye diagrams and DMI eye diagrams of the entire Byte, thereby determining the Eye Mask position; Based on the eye diagram and the determined Eye Mask position, the DQ Margin and DMI Margin are calculated.

[0015] In combination with the first aspect, in one implementation, the calculation of the Timing Margin specifically includes: For the 3 setup margins and 3 hold margins contained in each Bit, record the minimum value of the 3 setup margins and 3 hold margins contained in the current Bit as tBit_Margin_Min; The minimum value of tBit_Margin_Min of all single-Byte signals in the current Rank is used as tByte_Margin_Min of the current Rank.

[0016] In combination with the first aspect, in one implementation, for the maximum tWCK2CK_Rank2Rank, the calculation method is: Max tWCK2CK_rank2rank=2Min(tByte_Margin_Min[0], tByte_Margin_Min[1]) Among them, Max tWCK2CK_rank2rank represents the maximum tWCK2CK_Rank2Rank, tByte_Margin_Min[0] represents the tByte_Margin_Min of one of the two Ranks, and tByte_Margin_Min[1] represents the tByte_Margin_Min of the other Rank of the two Ranks.

[0017] In a second aspect, an embodiment of the present application provides a computing device in which a DRAM system can support a maximum latency, wherein the computing device in which the DRAM system can support a maximum latency includes: A building module, which is used to build a simulation environment, wherein the simulation circuit of the simulation environment includes an RDL model, an IBIS IO model and a DFE model; A simulation module is used to set ODT parameters to simulate two ranks independently based on the built simulation environment to obtain WCK, DQ, and DMI time domain waveforms; The calculation module is used to process the DQ and DMI time domain waveforms based on the WCK Trigger method and generate an eye diagram. According to the eye diagram, the Timing Margin and the maximum tWCK2CK_Rank2Rank are calculated.

[0018] In a third aspect, an embodiment of the present application provides a computing device for a DRAM system that can support a maximum delay, wherein the computing device for the DRAM system that can support a maximum delay comprises a processor, a memory, and a computing program for the maximum delay that the DRAM system can support, which is stored in the memory and can be executed by the processor. When the computing program for the maximum delay that the DRAM system can support is executed by the processor, the steps of the computing method for the maximum delay that the DRAM system can support described above are implemented.

[0019] The beneficial effects brought by the technical solution provided in the embodiments of the present application include: By building a simulation environment and then setting ODT parameters to independently simulate the two Ranks based on the built simulation environment, the DQ and DMI time domain waveforms are obtained, and then the DQ and DMI time domain waveforms are processed based on the WCK Trigger method to generate an eye diagram. According to the eye diagram, the Timing Margin and the maximum tWCK2CK_Rank2Rank are calculated to achieve the quantification of the maximum tWCK2CK_rank2rank supported by the SoC-LPDDR5DRAM system, and the generation of the DQ / DMI data signal eye diagram by WCK Trigger according to the simulation time domain diagram. After the system design is completed, the maximum tWCK2CK_Rank2Rank supported by the system can be directly calculated, thereby putting forward requirements for DRAM indicators and reducing testing costs. It can also point out which signals have greater risks before the system is produced, indicating the direction of improvement for the SoC-LPDDR5 DRAM system simulation link. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flowchart of a method for calculating the maximum latency that a DRAM system can support is provided in this application; Figure 2 It is the link structure diagram of the simulation circuit; Figure 3 A functional module diagram of a computing device that can support the maximum latency of the DRAM system of this application; Figure 4 This is a schematic diagram of the hardware structure of a computing device with the maximum latency that the DRAM system of this application can support. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0023] In the first aspect, the embodiment of the present application provides a method for calculating the maximum latency that a DRAM system can support, that is, realizing the calculation of the maximum tWCK2CK_rank2rank that a SoC-LPDDR5 DRAM system can support, realizing the quantification of the maximum tWCK2CK_rank2rank that a SoC-LPDDR5 DRAM system can support, and realizing the generation of a DQ / DMI data signal eye diagram using a WCK Trigger according to a simulation time domain diagram. DQ and DMI are key data signals in memory technology.

[0024] In one embodiment, referring to Figure 1 , Figure 1 This is a flow chart of a method for calculating the maximum delay that a DRAM system can support in this application. Figure 1 As shown, the calculation method of the maximum delay that the DRAM system can support includes: S1: Building a simulation environment, wherein the simulation circuit of the simulation environment includes an RDL model, an IBIS IO model, and a DFE model; Among them, RDL stands for Re-distributed Layer; IBIS stands for Input / Output Buffer Information Specification, which is a behavioral model; IO stands for input and output; DFE stands for Decision Feedback Equalier, which is a decision feedback equalizer; S2: Set ODT parameters to simulate two ranks independently based on the built simulation environment to obtain WCK, DQ, and DMI time domain waveforms; S3: Process the DQ and DMI time domain waveforms based on the WCK Trigger method and generate an eye diagram. According to the eye diagram, calculate the Timing Margin and the maximum tWCK2CK_Rank2Rank.

[0025] For further information, see Figure 2 As shown, the link structure of the simulation circuit includes a SoC IBIS model, a SoCPKG model, a PCB model, and a Dram PKG model connected in sequence, and the Dram PKG model is also connected to two DRAM IBIS models, wherein one of the two DRAM IBIS models corresponds to one of the two Ranks, and the other DRAM IBIS model corresponds to the other of the two Ranks.

[0026] Specifically, the SoC IBIS model is used to describe the electrical behavior of the SoC's DDR interface input / output buffer, including the driver's output voltage, current waveform, rise / fall time, output impedance, and the receiver's input impedance, threshold voltage, etc.; the SoC PKG model is an S-parameter model (scattering parameter model, a general benchmark behavioral model for describing the behavior of linear, passive interconnect structures) of the SoC package, which characterizes the high-frequency transmission characteristics of the SoC package structure (such as pins, solder balls, and internal interconnects), and quantifies the reflection, insertion loss, crosstalk, and phase delay of the signal in the package through scattering parameters.

[0027] The PCB model is an S-parameter model of a PCB (Printed Circuit Board), which is used to describe the frequency domain response of passive structures such as PCB traces, vias, power / ground planes, etc., including insertion loss, return loss, crosstalk, and impedance discontinuity.

[0028] The Dram PKG model is an S-parameter model of DRAM packaging, which is used to quantify the impact of DRAM chip packaging (such as BGA packaging) on ​​signals, including impedance changes of package interconnections and signal distortion caused by parasitic parameters.

[0029] The DRAM IBIS model is used to simulate the driver and receiver behaviors of the DRAM chip interface, defining its output drive strength, input logic threshold, and termination characteristics.

[0030] Furthermore, in one embodiment, the ODT parameter setting is specifically as follows: when simulating one of the two ranks, the ODT value of the DRAM IBIS model corresponding to the Rank is selected according to the transmission line impedance, and the ODT of the DRAM IBIS model corresponding to the other Rank is turned off. ODT, the full name of On-Die Termination, is a technology used for signal integrity and reflection reduction in DDR SDRAM.

[0031] Furthermore, the WCK, DQ, and DMI time domain waveforms obtained by Rank simulation are specifically described as follows.

[0032] Take one of the two ranks (denoted as Rank0) for simulation as an example. First, set the ODT parameters. As the receiving end, DRAM must enable ODT to achieve impedance matching and suppress signal reflection. Therefore, the ODT value of the DRAM IBIS model corresponding to Rank0 is selected according to the transmission line impedance (such as 40Ω or 48Ω), and the ODT of the DRAM IBIS model corresponding to the other Rank needs to be turned off. Then, set the code element sequence of the IBIS input of DQ / DMI at the SoC end to PRBS7, and the code element of the WCK IBIS input to a 0 / 1 sequence. Run Transient analysis in the simulation tool, and finally view the time domain waveform through the voltage probe Vprobe at the DRAM IBIS model end corresponding to Rank0.

[0033] Further, in one embodiment, the DQ and DMI time domain waveforms are processed based on the WCK Trigger method and the eye diagram is generated, specifically including: S301: According to the WCK time domain waveform, slicing the DQ time domain waveform according to the time length of a complete cycle of the WCK time domain waveform, dividing the DQ time domain waveform into a plurality of DQ time domain waveform segments, wherein a complete cycle of the WCK time domain waveform includes a first transition edge, a level, a second transition edge, a level, and a third transition edge; S302: Align each DQ time domain waveform segment at the second transition edge time, and overlap them to generate an eye diagram.

[0034] Specifically, a complete cycle of the WCK time domain waveform is obtained, and the complete cycle of the WCK time domain waveform is recorded as the target time domain waveform. The DQ time domain waveform is sliced ​​using the time length of the target time domain waveform to obtain multiple DQ time domain waveform segments, and each DQ time domain waveform segment is aligned at the moment of the second transition edge of the target time domain waveform, and overlapped to generate an eye diagram.

[0035] Furthermore, after the eye diagram is generated, the following steps are also included: a: Determine a unified Vref (reference voltage) based on all DQ eye diagrams and DMI eye diagrams of the entire Byte, thereby determining the Eye Mask position; the Eye Mask position is the boundary used to specify the minimum eye opening amplitude in the eye diagram test; b: Based on the eye diagram and the determined Eye Mask position, calculate the DQ Margin and DMI Margin.

[0036] Furthermore, in one embodiment, the calculation of Timing Margin specifically includes: S311: For the 3 setup margins and 3 hold margins included in each Bit, record the minimum value among the 3 setup margins (setup time redundancy) and 3 hold margins (hold time redundancy) included in the current Bit as tBit_Margin_Min; S312: Take the minimum value of tBit_Margin_Min of all signals of a single Byte in the current Rank as tByte_Margin_Min of the current Rank. Among them, Timing Margin is denoted as time redundancy.

[0037] Specifically, each Bit (bit) includes 3 setup margins and 3 hold margins. Define the minimum value among the 6 margins as tBit_Margin_Min. At the same time, for a single Rank, define the minimum value of tBit_Margin_Min of all signals of a single Byte in the Rank as tByte_Margin_Min.

[0038] Further, in an embodiment, for the maximum tWCK2CK_Rank2Rank, the calculation method is: Max tWCK2CK_rank2rank = 2Min(tByte_Margin_Min[0], tByte_Margin_Min[1]) Among them, Max tWCK2CK_rank2rank represents the maximum tWCK2CK_Rank2Rank, tByte_Margin_Min[0] represents tByte_Margin_Min of one of the two Ranks, and tByte_Margin_Min[1] represents tByte_Margin_Min of the other Rank among the two Ranks.

[0039] Specifically, in the WCK always on mode, the offset of WCK relative to the center of the DQ eye diagram is: tWCK2CK_rank2rank / 2, and it affects all signals of a single Byte. Therefore, for the system to work properly, it is required that: tWCK2CK_rank2rank / 2 < tByte_Margin_Min[rank], that is, the calculation method of Max tWCK2CK_rank2rank is 2Min(tByte_Margin_Min[0], tByte_Margin_Min[1]).

[0040] The DRAM system of the embodiment of the present application can support the calculation method of the maximum delay, by building a simulation environment, and then setting the ODT parameters to independently simulate the two ranks based on the built simulation environment, to obtain DQ and DMI time domain waveforms, and then process the DQ and DMI time domain waveforms based on the WCK Trigger method and generate an eye diagram, and according to the eye diagram, calculate the TimingMargin and the maximum tWCK2CK_Rank2Rank to achieve the quantification of the maximum tWCK2CK_rank2rank supported by the SoC-LPDDR5 DRAM system, and the generation of the DQ / DMI data signal eye diagram by the WCK Trigger according to the simulation time domain diagram. After the system design is completed, the maximum tWCK2CK_Rank2Rank supported by the system can be directly calculated, thereby putting forward requirements for DRAM indicators and reducing testing costs. It can also point out which signals have greater risks before the system is produced, and point out the direction of improvement for the SoC-LPDDR5 DRAM system simulation link.

[0041] In a second aspect, an embodiment of the present application also provides a computing device in which a DRAM system can support a maximum latency.

[0042] In one embodiment, referring to Figure 3 , Figure 3 This is a functional module diagram of a computing device that can support the maximum latency supported by the DRAM system of this application. Figure 3 As shown, the computing devices with the maximum latency that the DRAM system can support include: a building module, a simulation module, and a computing module.

[0043] The building module is used to build a simulation environment, and the simulation circuit of the simulation environment includes an RDL model, an IBIS IO model and a DFE model; the simulation module is used to set ODT parameters to independently simulate two Ranks based on the built simulation environment to obtain WCK, DQ, and DMI time domain waveforms; the calculation module is used to process the DQ and DMI time domain waveforms based on the WCK Trigger method and generate an eye diagram, and according to the eye diagram, the Timing Margin and the maximum tWCK2CK_Rank2Rank are calculated.

[0044] On the third aspect, an embodiment of the present application provides a computing device with a maximum latency supported by a DRAM system. The computing device with a maximum latency supported by the DRAM system may be a personal computer (PC), a laptop computer, a server, or other device with data processing capabilities.

[0045] Reference Figure 4 , Figure 4The hardware structure diagram of the computing device with the maximum latency supported by the DRAM system involved in the embodiment of the present application is shown in FIG. In the embodiment of the present application, the computing device with the maximum latency supported by the DRAM system may include a processor, a memory, a communication interface, and a communication bus.

[0046] The communication bus may be of any type and is used to interconnect the processor, the memory, and the communication interface.

[0047] The communication interface includes input / output (I / O) interfaces, physical interfaces, and logical interfaces, which are used to interconnect devices within the computing device that the DRAM system can support the maximum latency, and interfaces used to interconnect the computing device that the DRAM system can support the maximum latency with other devices (such as other computing devices or user devices). The physical interface can be an Ethernet interface, a fiber optic interface, an ATM interface, etc.; the user device can be a display, a keyboard, etc.

[0048] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0049] The processor may be a general-purpose processor, and the general-purpose processor may call the calculation program of the maximum delay that the DRAM system can support stored in the memory, and execute the calculation method of the maximum delay that the DRAM system can support provided by the embodiment of the present application. For example, the general-purpose processor may be a central processing unit (CPU). The method executed when the calculation program of the maximum delay that the DRAM system can support is called may refer to the various embodiments of the calculation method of the maximum delay that the DRAM system can support of the present application, and will not be repeated here.

[0050] Those skilled in the art will understand that Figure 4 The hardware structure shown in the figure does not constitute a limitation on the present application, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0051] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit "first", "second" and "third" to different types.

[0052] In the description of the embodiments of the present application, "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.

[0053] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; the “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0054] In some processes described in the embodiments of the present application, multiple operations or steps that appear in a specific order are included, but it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or in parallel, and the sequence number of the operation is only used to distinguish the different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.

[0055] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD) as described above, and includes a number of instructions for a terminal device to execute the methods described in each embodiment of the present application.

[0056] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for calculating the maximum delay that a DRAM system can support, characterized in that: The calculation method of the maximum delay that the DRAM system can support includes: Building a simulation environment, wherein the simulation circuit of the simulation environment includes an RDL model, an IBIS IO model, and a DFE model; Set ODT parameters to simulate two ranks independently based on the built simulation environment to obtain DQ and DMI time domain waveforms; The DQ and DMI time domain waveforms are processed based on the WCK Trigger method to generate an eye diagram. According to the eye diagram, the Timing Margin and the maximum tWCK2CK_Rank2Rank are calculated.

2. The method for calculating the maximum delay that a DRAM system can support according to claim 1, wherein: The link structure of the simulation circuit includes a SoC IBIS model, a SoC PKG model, a PCB model, and a DramPKG model connected in sequence, and the Dram PKG model is also connected to two DRAM IBIS models, wherein one of the two DRAM IBIS models corresponds to one of the two Ranks, and the other DRAM IBIS model corresponds to the other of the two Ranks.

3. The method for calculating the maximum delay that a DRAM system can support as claimed in claim 2, characterized in that: The SoC IBIS model is used to describe the electrical behavior of the DDR interface input / output buffer of the SoC; The SoC PKG model is an S-parameter model of the SoC package, which characterizes the high-frequency transmission characteristics of the SoC package structure; The PCB model is an S parameter model of the PCB; The Dram PKG model is an S parameter model of DRAM packaging, which is used to quantify the impact of DRAM chip packaging on signals; The DRAM IBIS model is used to simulate the driver and receiver behaviors of the DRAM chip interface.

4. A method for calculating the maximum delay that a DRAM system can support as claimed in claim 3, characterized in that: The ODT parameter settings are as follows: When simulating one of the two ranks, the ODT value of the DRAM IBIS model corresponding to the Rank is selected according to the transmission line impedance, and the ODT of the DRAM IBIS model corresponding to the other Rank is turned off.

5. The method for calculating the maximum delay that a DRAM system can support as claimed in claim 1, characterized in that: The WCK Trigger-based method processes DQ and DMI time domain waveforms and generates eye diagrams, specifically including: According to the WCK time domain waveform, the DQ time domain waveform is sliced ​​according to the time length of a complete cycle of the WCK time domain waveform, and the DQ time domain waveform is divided into a plurality of DQ time domain waveform segments, wherein a complete cycle of the WCK time domain waveform includes a first transition edge, a level, a second transition edge, a level, and a third transition edge; Each DQ time domain waveform segment is aligned at the second transition edge time and overlapped to generate an eye diagram.

6. A method for calculating the maximum delay that a DRAM system can support as claimed in claim 5, characterized in that: After generating the eye diagram, it also includes: Determine the unified Vref based on all DQ eye diagrams and DMI eye diagrams of the entire Byte, thereby determining the Eye Mask position; Based on the eye diagram and the determined Eye Mask position, the DQ Margin and DMI Margin are calculated.

7. A method for calculating the maximum delay that a DRAM system can support as claimed in claim 6, characterized in that: The calculation of Timing Margin includes: For the 3 setup margins and 3 hold margins contained in each Bit, record the minimum value of the 3 setup margins and 3 hold margins contained in the current Bit as tBit_Margin_Min; The minimum value of tBit_Margin_Min of all single-Byte signals in the current Rank is used as tByte_Margin_Min of the current Rank.

8. A method for calculating the maximum delay that a DRAM system can support as claimed in claim 7, characterized in that: For the maximum tWCK2CK_Rank2Rank, it is calculated as: Max tWCK2CK_rank2rank=2Min(tByte_Margin_Min[0], tByte_Margin_Min[1]) Among them, Max tWCK2CK_rank2rank represents the maximum tWCK2CK_Rank2Rank, tByte_Margin_Min[0] represents the tByte_Margin_Min of one of the two Ranks, and tByte_Margin_Min[1] represents the tByte_Margin_Min of the other Rank of the two Ranks.

9. A computing device with a maximum latency supported by a DRAM system, characterized in that: The computing devices with the maximum latency supported by the DRAM system include: A building module, which is used to build a simulation environment, wherein the simulation circuit of the simulation environment includes an RDL model, an IBIS IO model and a DFE model; A simulation module is used to set ODT parameters to simulate two ranks independently based on the built simulation environment to obtain WCK, DQ, and DMI time domain waveforms; The calculation module is used to process the DQ and DMI time domain waveforms based on the WCK Trigger method and generate an eye diagram. According to the eye diagram, the Timing Margin and the maximum tWCK2CK_Rank2Rank are calculated.

10. A computing device with a maximum latency supported by a DRAM system, characterized in that: The computing device for the maximum delay that the DRAM system can support includes a processor, a memory, and a computing program for the maximum delay that the DRAM system can support, which is stored in the memory and can be executed by the processor. When the computing program for the maximum delay that the DRAM system can support is executed by the processor, the steps of the method for calculating the maximum delay that the DRAM system can support as described in any one of claims 1 to 8 are implemented.

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