Three-dimensional integrated circuit silicon through hole fault repairing method and system

Abstract

The invention discloses a three-dimensional integrated circuit through-silicon via fault repairing method and system, and the method comprises the steps: firstly building a switch matrix composed of n * n switch units, then connecting the switch matrix with n * n through-silicon vias and n redundant through-silicon vias to form a through-silicon via repairing circuit, and after the position of a fault through-silicon via is positioned, taking the fault through-silicon via as a starting point, and taking the redundant through-silicon via as an end point, performing path planning between the starting point and the end point, and finally repairing the fault through-silicon via according to the planned path. According to the method, the TSV repair efficiency and flexibility are improved under the condition that hardware and delay overhead are not obviously increased.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging and assembly, in particular to a fault repair method and system for through silicon vias of a three-dimensional integrated circuit. Background Art

[0002] With the continuous miniaturization of semiconductor processes and the improvement of system integration, two-dimensional planar integrated circuits are gradually approaching physical limits in terms of performance, power consumption and area. 3D ICs use vertical stacking and through-silicon via (TSV) technology to tightly integrate multiple chips with different functions within a limited silicon area, achieving high-density vertical interconnection, improving communication bandwidth, and reducing signal delay and power consumption. However, voids, stress and impurities are easily introduced during deep etching, TSV filling and planarization, resulting in structural defects and functional failures of TSV. In addition, high power density and thermal imbalance will increase the risk of electromigration and stress failure of TSV. In the face of these failures, if there is no effective detection and repair mechanism, the entire 3D chip may be scrapped due to the failure of a small number of TSVs, resulting in cost waste and reduced yield.

[0003] Existing TSV repair methods include router structures, ring structures, honeycomb structures, etc., but relying solely on traditional methods is difficult to meet the needs of fast and efficient repair of TSV faults. The main reason is that existing TSV redundancy strategies rely on a large number of redundant TSVs and multiplexers (MUX), which often introduce high latency, area, and design complexity while achieving a high repair rate. In addition, when encountering serious cluster failures, traditional routing architectures or grouping strategies may also be difficult to meet the requirements of efficient repair. Summary of the invention

[0004] Purpose of the invention: The purpose of the present invention is to provide a method and system for repairing through silicon vias in three-dimensional integrated circuits, which can improve the efficiency and flexibility of TSV repair without significantly increasing hardware and delay overhead, and meet the needs of future 3D IC design development towards larger scale and higher reliability.

[0005] Technical solution: The method for repairing a fault of a three-dimensional integrated circuit through silicon via according to the present invention comprises the following steps: (1) Establishing a switch matrix consisting of n×n switch units, wherein the switch unit includes four transmission transistors G1, G2, G3 and G4 connected end to end in sequence, and the connection point between the four transmission transistors serves as an external connection point, which is connected to other switch units to form a switch matrix; The switch unit further includes a fifth transmission transistor G5, one end of which is connected between G1 and G4, and the connection point thereof is referred to as a first node; The other ends of G5 are all connected to TSVs, and the first nodes on edge rows or edge columns in the switch matrix are all connected to redundant TSVs, thereby obtaining a TSV repair circuit; (2) reading the test results of the through silicon vias in the through silicon via repair circuit to obtain the positions of m faulty through silicon vias, where m≤n; Convert the circuit diagram of the through silicon via repair circuit into a network node diagram, in which a node represents a connection between the ends of a transmission transistor, and two nodes are connected to form an edge; (3) Taking the faulty TSV as the starting point and the redundant TSV as the end point, and using a breadth-first search algorithm to plan a path between the starting point and the end point according to a preset priority order of the TSVs, m paths are obtained, and the faulty TSV is repaired using the paths; The edges in the network node graph included in each path represent that the transmission transistor is in the on state and the other transmission transistors are in the off state.

[0006] Furthermore, in step (3), the path planning between the starting point and the end point using the breadth-first search algorithm includes path connectivity constraints and path overlap constraints; The path connectivity constraint is that each node in each path is an adjacent node and there is no duplicate node; The path overlap constraint is that there are no reused nodes in each path.

[0007] Furthermore, in step (3), before using the breadth-first search algorithm to plan the path between the starting point and the end point, the method further includes pairing the starting point and the end point: selecting a starting point in turn according to a preset priority order, calculating the Manhattan distance between the starting point and each optional end point, selecting the end point with the shortest Manhattan distance to pair with the starting point, and saving the matching pair of the starting point and the end point to a form; Each endpoint matches only one starting point, and unmatched endpoints are optional endpoints.

[0008] Furthermore, in step (3), a matching pair is selected in turn according to a preset priority order, and a path is planned using a breadth-first search algorithm. When a path is not successfully planned, a forward exchange of endpoints is performed; The end point of the forward exchange is: deleting all the obtained paths, exchanging the current matching pair with the matching pair of the previous priority order, updating the table, selecting a matching pair in turn according to the priority order in the updated table, and using the breadth-first search algorithm for path planning; the maximum number of forward exchanges is set to n times.

[0009] Furthermore, in step (3), after executing n forward exchange of endpoints, if the path planning is not successfully planned using the breadth-first search algorithm, the endpoints are exchanged backwards; The end point of the backward exchange is: delete all the obtained paths, exchange the current matching pair with the matching pair of the next priority order for the table before the forward exchange end point, update the table, select a matching pair in turn according to the priority order in the updated table, and use the breadth-first search algorithm to plan the path; the maximum number of backward exchanges is set to n times.

[0010] The three-dimensional integrated circuit through silicon via fault repair system of the present invention comprises: A switch matrix establishing unit, used to establish a switch matrix consisting of n×n switch units, wherein the switch unit includes four transmission transistors G1, G2, G3 and G4 connected in sequence end to end, and the connection point between the four transmission transistors is used as an external connection point to connect with other switch units to form a switch matrix; The switch unit further includes a fifth transmission transistor G5, one end of which is connected between G1 and G4, and the connection point thereof is referred to as a first node; The other ends of G5 are all connected to TSVs, and the first nodes on edge rows or edge columns in the switch matrix are all connected to redundant TSVs, thereby obtaining a TSV repair circuit; A through silicon via test result reading unit, used to read the test result of the through silicon via in the through silicon via repair circuit, and obtain the positions of m faulty through silicon vias, m≤n; A network node graph conversion unit, used for converting a circuit diagram of a through silicon via repair circuit into a network node graph, in which a node represents a connection between two ends of a transmission transistor, and two nodes are connected to form an edge; A faulty TSV repair unit is used to use the faulty TSV as a starting point and the redundant TSV as an end point, and to plan a path between the starting point and the end point using a breadth-first search algorithm according to a preset priority order of the TSVs to obtain m paths, and to repair the faulty TSV using the paths; The edges in the network node graph included in each path represent that the transmission transistor is in the on state and the other transmission transistors are in the off state.

[0011] Further, in the faulty through silicon via repair unit, the path planning between the starting point and the end point using the breadth-first search algorithm includes a path connectivity constraint and a path overlap constraint; The path connectivity constraint is that each node in each path is an adjacent node and there is no duplicate node; The path overlap constraint is that there are no reused nodes in each path.

[0012] Furthermore, in the faulty through silicon via repair unit, before using the breadth-first search algorithm to perform path planning between the starting point and the end point, the method further includes pairing the starting point and the end point: selecting a starting point in turn according to a preset priority order, calculating the Manhattan distance between the starting point and each optional end point, selecting the end point with the shortest Manhattan distance to pair with the starting point, and saving the matching pair of the starting point and the end point to a form; Each endpoint is matched with only one starting point, and the unmatched endpoints are optional endpoints; In the faulty through silicon via repair unit, a matching pair is selected in turn according to the preset priority order, and the path planning is performed using the breadth-first search algorithm. When the path planning is unsuccessful, the end point is forward exchanged; The end point of the forward exchange is: deleting all the obtained paths, exchanging the current matching pair with the matching pair of the previous priority order, updating the table, selecting a matching pair in turn according to the priority order in the updated table, and performing path planning using the breadth-first search algorithm; the maximum number of forward exchanges is set to n times; After executing n forward exchange endpoints, if the path planning is unsuccessful using the breadth-first search algorithm, the backward exchange endpoint is performed; The end point of the backward exchange is: delete all the obtained paths, exchange the current matching pair with the matching pair of the next priority order for the table before the forward exchange end point, update the table, select a matching pair in turn according to the priority order in the updated table, and use the breadth-first search algorithm to plan the path; the maximum number of backward exchanges is set to n times.

[0013] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the fault repair method of the three-dimensional integrated circuit silicon through-hole via is implemented.

[0014] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the fault repair method of the three-dimensional integrated circuit silicon through-hole via is implemented.

[0015] Beneficial effects: Compared with the prior art, the advantages of the present invention are: the present invention uses transmission transistors to construct basic switch units, and uses basic switch units to form a switch matrix to replace the routing structure (MUX) in the traditional repair algorithm, effectively controlling the hardware overhead. The construction of the switch matrix allows all faulty TSVs that are not greater than the number of redundant TSVs (theoretically the maximum number of faulty TSVs that can be repaired) to be repaired, with a repair rate of 100%, solving the problem that the traditional repair algorithm cannot repair in some highly clustered situations. The test algorithm is simple and has low time complexity, which shortens the running time of the automatic test equipment and saves the repair cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a flow chart of the fault repair method of the present invention.

[0017] Figure 2 Schematic diagram of the basic switch unit structure of an embodiment of the present invention.

[0018] Figure 3 Schematic diagram of the switch matrix network structure of an embodiment of the present invention.

[0019] Figure 4 This is a network node diagram of an embodiment of the present invention.

[0020] Figure 5 Schematic diagram of a test result file according to an embodiment of the present invention.

[0021] Figure 6 This is a schematic diagram of a path planning result after executing a breadth-first search algorithm according to an embodiment of the present invention.

[0022] Figure 7 This is a schematic diagram of the path planning result after executing the first terminal exchange algorithm five times according to an embodiment of the present invention.

[0023] Figure 8 This is a schematic diagram of the path planning result after executing the second terminal exchange algorithm once according to an embodiment of the present invention.

[0024] Fig. 9 Schematic diagram of a signal matrix according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0026] like Figure 1 As shown, the method for repairing faults of through silicon vias in a three-dimensional integrated circuit includes the following steps.

[0027] Step 1, design of the basic switch unit circuit structure consisting of five transmission transistors.

[0028] like Figure 2 The basic circuit structure shown in (a) in FIG. 1 includes: four transmission transistors are connected end to end to form a diamond structure, one end of the fifth transistor is connected to the right end of the diamond, and the other end is connected to the TSV; a basic switch unit is designed according to the basic circuit structure, such as Figure 2As shown in (b), the basic switch unit is composed of five transmission transistors, among which four transmission transistors (G1, G2, G3, G4) are connected end to end to form a diamond structure, and one end of the fifth transmission transistor (G5) is connected to any vertex of the diamond inside the diamond, and the other end is used to connect to the TSV; in this embodiment, the right end point of the fifth transmission transistor is connected to the right vertex of the diamond, and the left end point is used to connect to the TSV. The advantage of this is that each time when searching for a repair path for a faulty TSV, the BFS algorithm will give priority to trying the right node, so as to approach the right redundant TSV faster, reduce the redundant path caused by unnecessary trials, and try to get a shorter path.

[0029] The four vertices of the diamond structure of the basic switch unit serve as external connection points for connecting the connection points of other basic switch units to form a switch array structure. Figure 2 (b) is represented using an extended line segment.

[0030] Step 2: Design of switch matrix structure constructed by n×n scale switch units.

[0031] The basic switch units are arranged into an array structure, and each basic switch unit has the same direction, so that when TSV failures occur at different positions, the algorithm will give priority to path exploration on the same side, which can effectively avoid the occurrence of path conflicts. The general structure is an n×n switch array, called a switch matrix (SM). Specifically, the left vertex of the first switch unit is connected to the right vertex of the next switch unit, and the left vertex of the second switch unit is connected to the right vertex of the next switch unit, and then connected to the nth switch unit to form a switch row; and the lower vertex of the switch unit corresponding to the previous switch row is connected to the upper vertex of the switch unit corresponding to the next switch row, and then connected to the nth row to form a switch matrix.

[0032] Step 3: The switch matrix is ​​functionally connected to the TSV array.

[0033] Construct an n×n scale TSV array to simulate a single group of signal TSV arrays to be repaired, connect the TSV array to the constructed switch matrix, and connect each TSV to the unconnected end of the fifth transmission transistor in the basic switch unit. At the same time, the unconnected ends of the most edge column of the switch matrix are connected to a redundant TSV, and finally form a through silicon via repair circuit. Figure 3 As shown, in this embodiment, taking n=5 as an example, each TSV is connected to the left end point of the fifth transmission transistor in each basic switch unit, and the rightmost column of the switch matrix is ​​connected to the redundant TSV, specifically, the right end point of the fifth transmission transistor is connected to the redundant TSV (R1, R2, R3, R4, R5).

[0034] Step 4: read the TSV interconnect test result file and identify the faulty TSV.

[0035] Read the TSV test result file. The result file contains the fault conditions of the corresponding scale (n×n) TSV array. The encoding rule is that binary "1" represents that the TSV at the corresponding position is fault-free, and binary "0" represents that the TSV at the corresponding position is a faulty TSV. The result file contains n lines, each line has n-bit encoding, which constitutes the test results of the fault conditions of the corresponding n×n signal TSV array. The coordinates of the m faulty TSV positions are extracted and identified for the start and end point matching and path planning basis of the next step of the repair path, m≤n.

[0036] Step 5, converting the circuit diagram of the through silicon via repair circuit into a corresponding network node diagram, and converting the faulty through silicon via repair signal switching problem into a start-end point pair path planning problem.

[0037] The circuit diagram of the through silicon via repair circuit is converted into the corresponding network node diagram, such as Figure 2 As shown in (c) in the figure, the network node graph includes nodes and edges. The nodes represent the connection between the ends of the transmission transistors that constitute the basic switch unit. Two nodes are connected to form an edge, which represents the line connecting the transmission transistors or the basic switch units.

[0038] The faulty TSV is used as the starting point, and the redundant TSV is used as the end point.

[0039] Step 6: Match the start and end points in order of priority and with the shorter Manhattan distance as the heuristic, and record the start and end point matching table.

[0040] According to the preset TSV priority, a starting point is selected for processing in turn, the Manhattan distance between the starting point and all optional end points is calculated, and a set of starting points and end points with the shortest Manhattan distance is selected as the current matching pair, until all starting points have a corresponding end point, and finally m matching pairs are obtained, and the matching pairs are recorded in the starting point and end point matching form (hereinafter referred to as the form).

[0041] Each endpoint matches only one starting point, and unmatched endpoints are optional endpoints.

[0042] Step 7: Run the breadth-first search algorithm (BFS) for path planning in order of priority, check and return the planned path information; run the end point exchange algorithm for situations where all start-end point path matching cannot be completed, update the form, and re-plan the path. If all path planning is successful, output the path information file, convert it into a signal matrix, and perform fault repair according to the path corresponding to the signal matrix; if there is a situation where the path cannot be planned, the result returned is repair failure.

[0043] According to the pre-set TSV priority, a matching pair is selected from the table in turn, and path planning is performed using BFS. Path planning needs to satisfy path connectivity constraints and path overlap constraints. The path connectivity constraint requires that each node in each path is an adjacent node and there are no duplicate nodes; the path overlap constraint requires that there are no reused nodes in all paths.

[0044] If the path planning fails, run the first endpoint exchange algorithm. First, clear all previously completed and stored path planning results, exchange the endpoints of the current matching pair and the previous sequential matching pair, and update the table at the same time. Then, according to the latest table, the BFS path planning process is carried out again in order. This process is called forward exchange of endpoints. If the path planning still fails, continue to exchange endpoints forward until all paths are planned. The maximum number of forward exchanges is set to n times.

[0045] If the path planning fails after executing the first endpoint exchange algorithm n times, run the second endpoint exchange algorithm. Clear the current form and read the form saved in step 6 (that is, return to the form before running the first endpoint exchange algorithm), clear all previously completed and stored path planning results, exchange the endpoints of the current matching pair and the next sequential matching pair, and update the form at the same time. Then perform the BFS path planning process in sequence again according to the latest form. This process is called backward exchange of endpoints. If the path planning still cannot be completed, continue to exchange endpoints backwards until all paths are fully planned. The maximum number of backward exchanges is set to n times.

[0046] The first matching pair and the mth matching pair in the table form a front-to-back relationship, the first pair is the next matching pair of the mth pair, and the mth pair is the previous matching pair of the first pair.

[0047] If the path is still not successfully planned after executing the second end point exchange algorithm n times, all path planning information is cleared and the result returned is repair failure. If all path planning has been completed and path information has been stored, the path search is successful and the algorithm is exited, and the result returned is repair success.

[0048] When the result is a successful repair, run the path conversion signal matrix algorithm. Extract the edges in each path in the path information, and filter out the coordinates of the edges that exist on the basic switch unit. Mark the corresponding position of the signal matrix with a binary "1", and mark the remaining positions of the signal matrix with a binary "0". Each binary "1" in the signal matrix represents that the transmission transistor at the corresponding position should be in the "on" state after the repair is completed, which is equivalent to a short circuit in electrical connection and can form a signal path. Each binary "0" in the signal matrix represents that the transmission transistor at the corresponding position should be in the "off" state after the repair is completed, which is equivalent to an open circuit in electrical connection and cannot form a signal path. In actual use, other representations are also used, such as using binary "0" to represent the "on" state and binary "1" to represent the "off" state.

[0049] The method of the present invention is verified by specific experiments below.

[0050] Taking a 5×5 switch array as an example, in the network node diagram, the location coordinates of TSV contain three elements: row, col, and id. Row represents the row in the array, col represents the column in the array, and id is the node coordinate of the basic switch unit connected to TSV in the corresponding node diagram. The location id value corresponding to the TSV connection is 0.

[0051] Each matching pair stored in the form contains three elements, namely the starting point, the end point and the Manhattan distance between the two. The pairing is recorded as Point-pair (start, goal, instance).

[0052] The following two aspects are explained separately.

[0053] (1) The process of converting a 5×5 switch matrix connected TSV array into a network node graph.

[0054] For a TSV array of a specific scale, take a 5×5 scale with 25 signal TSVs as an example, connected to a 5×5 switch matrix, after converting the circuit diagram into a node diagram, the signal TSV (or fault TSV) is located at the center of the switch, denoted as node 0, represented by id=0; node 0 is connected to the right node of the switch (denoted as node 1); node 1 is connected to the upper node (denoted as node 2) and the lower node (denoted as node 4) of the switch, as well as the left node of the right switch (denoted as node 3; except the rightmost column switch); node 2 is also connected to node 3 and node 4 of the upper switch (except the top row switch); node 3 is also connected to node 1 of the left switch (except the leftmost column switch); node 4 is also connected to node 2 of the lower switch (except the bottom row switch).

[0055] Reference Figure 4, select the switch in the second row and second column as the most typical connection relationship to explain, node 0 (1, 1, 0) is connected to node 1 (1, 1, 1); node 1 is connected to node 2 (1, 1, 2) and node 4 (1, 1, 4); node 2 (1, 1, 2) is also connected to node 3 (1, 1, 3) and node 4 in the previous row (0, 1, 4); node 3 is also connected to node 1 on the right (1, 0, 1); node 4 is also connected to node 2 below (2, 1, 2).

[0056] Reference Figure 4 , the coordinates of node 0 in the switch in the first row and first column are (0, 0, 0). Similarly, the coordinates of nodes 1-4 are (0, 0, 1), (0, 0, 2), (0, 0, 3), and (0, 0, 4). Nodes 2 and 3 have no additional connection relationship.

[0057] Reference Figure 4 ,In the first row and last column, the right side of the switch No. 1 is connected to the nodes No. 2 and No. 4 in the same switch, and is also connected to the right node R0, representing the connection relationship with the redundant TSV.

[0058] (2) The process of reading the test result file, identifying the faulty TSV, and matching the starting point and end point according to the priority.

[0059] Reference Figure 5, is a test result file, which shows the fault condition of each TSV in the 5×5 TSV array. The TSV corresponding to the binary "1" is the faulty TSV. In this embodiment, the coordinates of all faulty TSVs are (0, 1, 0), (1, 1, 0), (3, 1, 0), (2, 1, 0) and (0, 0, 0). The known faulty TSVs are sorted according to their priorities. In this embodiment, the priority order is: {0,4,0}, {1,4,0}, {2,4,0}, {3,4,0}, {4,4,0}, {0,3,0}, {4,3,0}, {1,3,0}, {3,3,0}, {0,2,0}, {4,2,0}, {2,3,0}, {1,2,0}, {3,2,0}, {0,1,0}, {4,1,0},{2,2,0}, {1,1,0}, {3,1,0}, {0,0,0}, {4,0,0}, {2,1,0}, {1,0,0}, {3,0,0}, {2,0,0}. The order of the starting points after sorting them in order of priority is: (0, 1, 0), (1, 1, 0), (3, 1, 0), (0,0, 0), (2, 1, 0). The Manhattan distance from each starting point to each end point is calculated in turn, and the one with the shortest distance is selected as the current end point for pairing each time. The end points that have been used cannot be used again. The matching table result of this embodiment is: 1. Starting point: (0, 1, 0), end point: R0; 2. Starting point: (1, 1, 0), end point: R1; 3. Starting point: (3, 1, 0), end point: R3; 4. Starting point: (0, 0, 0), end point: R2; 5. Starting point: (2, 1, 0), end point: R4.

[0060] The matching table result after this embodiment triggers the first end point exchange algorithm 5 times and the second end point exchange algorithm once is: 1. Starting point: (0, 1, 0), end point: R0; 2. Starting point: (1, 1, 0), end point: R1; 3. Starting point: (3, 1, 0), end point: R3; 4. Starting point: (2, 1, 0), end point: R2; 5. Starting point: (0, 0, 0), end point: R4.

[0061] Reference Figure 6, which is a schematic diagram of the path planning result after executing a breadth-first search algorithm in this embodiment. It can be seen from the figure that the entire path planning is not successfully performed, the triggering condition of the first terminal exchange algorithm is met, and the first terminal exchange algorithm is started to be executed.

[0062] Reference Figure 7 , which is a schematic diagram of the path planning result after executing the first terminal exchange algorithm five times in this embodiment. It can be seen from the figure that the entire path planning has not been successfully completed. At this time, the triggering condition of the second terminal exchange algorithm is met, and the second terminal exchange algorithm is started.

[0063] Reference Figure 8 , which is a schematic diagram of the path planning result after executing the second terminal exchange algorithm once in this embodiment. It can be seen from the figure that the program finally outputs all five valid paths and successfully performs path planning.

[0064] Reference Fig. 9 , extract the edges in each path, and filter out the coordinates of the edges existing on the basic switch unit, and mark the corresponding positions of the signal matrix with binary "1". The rest of the positions of the signal matrix are marked with binary "0". The signal matrix is ​​used as the input of the switch matrix to control the construction of the repair path. Fig. 9 The red edge in the figure is the edge that the path passes through, and the corresponding switch must be closed. The fault repair system of the three-dimensional integrated circuit silicon through via of the present invention includes:

[0065] A switch matrix establishing unit, used to establish a switch matrix consisting of n×n switch units, wherein the switch unit includes four transmission transistors G1, G2, G3 and G4 which are connected in sequence in the first position, and the connection point between the four transmission transistors is used as an external connection point to connect with other switch units to form a switch matrix; The switch unit further includes a fifth transmission transistor G5, one end of which is connected between G1 and G4, and the connection point thereof is referred to as a first node; The other ends of G5 are all connected to TSVs, and the first nodes on edge rows or edge columns in the switch matrix are all connected to redundant TSVs, thereby obtaining a TSV repair circuit; A through silicon via test result reading unit, used for reading the through silicon via test result of the through silicon via array, and obtaining the positions of m faulty through silicon vias, m≤n; A network node graph conversion unit, used for converting a circuit diagram of a through silicon via repair circuit into a network node graph, in which a node represents a connection between two ends of a transmission transistor, and two nodes are connected to form an edge; A faulty TSV repair unit is used to use the faulty TSV as a starting point and the redundant TSV as an end point, and to plan a path between the starting point and the end point using a breadth-first search algorithm according to a preset priority order of the TSVs to obtain m paths, and to repair the faulty TSV using the paths; The edges in the network node graph included in each path represent that the transmission transistor is in the on state and the other transmission transistors are in the off state.

[0066] The computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store program code in the form of instructions or data structures and that can be accessed by a computer.

[0067] The processor is used to execute the computer program stored in the memory to implement each step of the method involved in the above embodiment.

Claims

1. A method for repairing a fault of a three-dimensional integrated circuit through silicon via, characterized in that: The steps include: (1) Establishing a switch matrix consisting of n×n switch units, wherein the switch unit includes four transmission transistors G1, G2, G3 and G4 connected end to end in sequence, and the connection point between the four transmission transistors serves as an external connection point, which is connected to other switch units to form a switch matrix; The switch unit further includes a fifth transmission transistor G5, one end of which is connected between G1 and G4, and the connection point thereof is referred to as a first node; The other ends of G5 are all connected to TSVs, and the first nodes on edge rows or edge columns in the switch matrix are all connected to redundant TSVs, thereby obtaining a TSV repair circuit; (2) reading the test results of the through silicon vias in the through silicon via repair circuit to obtain the positions of m faulty through silicon vias, where m≤n; converting the circuit diagram of the through silicon via repair circuit into a network node diagram, in which a node represents a connection between two ends of a transmission transistor, and two nodes are connected to form an edge; (3) Taking the faulty TSV as the starting point and the redundant TSV as the end point, and using a breadth-first search algorithm to plan a path between the starting point and the end point according to a preset priority order of the TSVs, m paths are obtained, and the faulty TSV is repaired using the paths; The edges in the network node graph included in each path represent that the transmission transistor is in the on state and the other transmission transistors are in the off state.

2. The method for repairing a fault of a three-dimensional integrated circuit through silicon via according to claim 1, characterized in that: In step (3), the path planning between the starting point and the end point using the breadth-first search algorithm includes path connectivity constraints and path overlap constraints; The path connectivity constraint is that each node in each path is an adjacent node and there is no duplicate node; The path overlap constraint is that there are no reused nodes in each path.

3. The method for repairing a fault of a three-dimensional integrated circuit through silicon via according to claim 1, characterized in that: In step (3), before using the breadth-first search algorithm to plan the path between the starting point and the end point, the method further includes pairing the starting point and the end point: selecting a starting point in turn according to a preset priority order, calculating the Manhattan distance between the starting point and each optional end point, selecting the end point with the shortest Manhattan distance to pair with the starting point, and saving the matching pair of the starting point and the end point to a form; Each endpoint matches only one starting point, and unmatched endpoints are optional endpoints.

4. The method for repairing a fault of a three-dimensional integrated circuit through silicon via according to claim 3, characterized in that: In step (3), a matching pair is selected in turn according to a preset priority order, and a path is planned using a breadth-first search algorithm. When a path is not successfully planned, a forward exchange of endpoints is performed; The end point of the forward exchange is: deleting all the obtained paths, exchanging the current matching pair with the matching pair of the previous priority order, updating the table, selecting a matching pair in turn according to the priority order in the updated table, and using the breadth-first search algorithm for path planning; the maximum number of forward exchanges is set to n times.

5. The method for repairing a fault of a three-dimensional integrated circuit through silicon via according to claim 4, characterized in that: In step (3), after executing n forward exchange endpoints, if the path planning is unsuccessful using the breadth-first search algorithm, the backward exchange endpoint is performed; The backward exchange end point is: deleting all the obtained paths, exchanging the current matching pair with the matching pair of the next priority order for the table before the forward exchange end point, updating the table, selecting a matching pair in turn according to the priority order in the updated table, and performing path planning using a breadth-first search algorithm; The maximum number of backward exchanges is set to n.

6. A three-dimensional integrated circuit through silicon via fault repair system, characterized in that: include: A switch matrix establishing unit, used to establish a switch matrix consisting of n×n switch units, wherein the switch unit includes four transmission transistors G1, G2, G3 and G4 connected in sequence end to end, and the connection point between the four transmission transistors is used as an external connection point to connect with other switch units to form a switch matrix; The switch unit further includes a fifth transmission transistor G5, one end of which is connected between G1 and G4, and the connection point thereof is referred to as a first node; The other ends of G5 are all connected to TSVs, and the first nodes on edge rows or edge columns in the switch matrix are all connected to redundant TSVs, thereby obtaining a TSV repair circuit; A through silicon via test result reading unit, used to read the test result of the through silicon via in the through silicon via repair circuit, and obtain the positions of m faulty through silicon vias, m≤n; A network node graph conversion unit, used for converting a circuit diagram of a through silicon via repair circuit into a network node graph, in which a node represents a connection between two ends of a transmission transistor, and two nodes are connected to form an edge; A faulty TSV repair unit is used to use the faulty TSV as a starting point and the redundant TSV as an end point, and to plan a path between the starting point and the end point using a breadth-first search algorithm according to a preset priority order of the TSVs to obtain m paths, and to repair the faulty TSV using the paths; The edges in the network node graph included in each path represent that the transmission transistor is in the on state and the other transmission transistors are in the off state.

7. The three-dimensional integrated circuit through silicon via fault repair system according to claim 6, characterized in that: In the faulty through silicon via repair unit, the path planning between the starting point and the end point using the breadth-first search algorithm includes path connectivity constraints and path overlap constraints; The path connectivity constraint is that each node in each path is an adjacent node and there is no duplicate node; The path overlap constraint is that there are no reused nodes in each path.

8. The three-dimensional integrated circuit through silicon via fault repair system according to claim 6, characterized in that: In the faulty through silicon via repair unit, before using the breadth-first search algorithm to plan the path between the starting point and the end point, the starting point and the end point are paired: a starting point is selected in turn according to a preset priority order, the Manhattan distance between the starting point and each optional end point is calculated, the end point with the shortest Manhattan distance is selected to pair with the starting point, and the matching pair of the starting point and the end point is saved in a form; Each endpoint is matched with only one starting point, and the unmatched endpoints are optional endpoints; In the faulty through silicon via repair unit, a matching pair is selected in turn according to the preset priority order, and the path is planned using the breadth-first search algorithm. When the path planning is unsuccessful, the end point is forward exchanged; The end point of the forward exchange is: deleting all the obtained paths, exchanging the current matching pair with the matching pair of the previous priority order, updating the table, selecting a matching pair in turn according to the priority order in the updated table, and performing path planning using the breadth-first search algorithm; the maximum number of forward exchanges is set to n times; After executing n forward exchange endpoints, if the path planning is unsuccessful using the breadth-first search algorithm, the backward exchange endpoint is performed; The end point of the backward exchange is: delete all the obtained paths, exchange the current matching pair with the matching pair of the next priority order for the table before the forward exchange end point, update the table, select a matching pair in turn according to the priority order in the updated table, and use the breadth-first search algorithm to plan the path; the maximum number of backward exchanges is set to n times.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into a processor, the fault repair method of a three-dimensional integrated circuit through silicon via according to any one of claims 1 to 5 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the fault repair method of a three-dimensional integrated circuit through silicon via according to any one of claims 1 to 5 is implemented.

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