Interconnection process defect test structure, critical defect value acquisition method and interconnection process defect clamping control method

Abstract

The invention discloses an interconnection process defect test structure, a critical defect value acquisition method and an interconnection process defect control method. According to the invention, a test structure and method capable of obtaining the dish-shaped defect caused by the interconnection process are designed, the corresponding critical defect value is obtained, and the layer-by-layer accumulation effect of the dish-shaped defect can be monitored on line according to the critical defect value; and when the dish-shaped defect is accumulated to a corresponding critical defect value, the dish-shaped defect can be found online in time to carry out clamping control and remedy, so that low-quality defects are avoided. And on-line clamping control of wafers with different metal line widths can be realized by establishing a comparison table of critical defect values and metal line widths. Due to the layer-by-layer accumulation effect of short circuit between wires caused by dish-shaped defects, online and timely clamping control can be achieved according to critical defect values, remedial measures can be taken, low-quality products are avoided, and stable product quality is guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to an interconnection process defect test structure and a critical defect value acquisition method, and an interconnection process defect card control method. Background Art

[0002] In the dual damascene process, chemical mechanical polishing (CMP) is used to remove excess metal copper (Cu) to form an embedded copper interconnect structure. Since materials with different polishing rates are polished simultaneously, it is easy to cause local over-polishing of the copper wire, resulting in dishing defects (Dishing). The degree of dishing defects is related to the width of the copper wire being polished. The wider the copper wire, the greater the copper wire density (Density), and the more serious the dishing defects. The dishing defects will reduce the effective thickness of the copper wire and cause increased resistance. More seriously, due to the accumulation effect of dishing defects, copper residual defects (Cu Residue) are generated in the area at the grinding capacity limit of the copper CMP process, causing short circuits between wires, resulting in a decrease in chip yield or even scrapping.

[0003] The existing test key that reflects whether there is a short circuit between wires cannot fully represent the distribution status of the copper wires in the chip; and the wafer acceptance test (WAT) is conducted after the process is completed, which takes a long time. Short circuits between wires caused by process fluctuations and serious dishing defects are often not discovered in time.

[0004] Therefore, how to perform inline monitoring of dishing defects in the interconnection process and timely discover the dishing defects is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide an interconnection process defect test structure and a critical defect value acquisition method, and an interconnection process defect control method, which can monitor the layer-by-layer accumulation effect of dish-shaped defects in the interconnection process, and then realize online control of interconnection process defects to avoid low-quality products.

[0006] To solve the above problems, an embodiment of the present invention provides an interconnection process defect test structure, comprising: multiple test units; each of the test units comprises an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer perform the same dielectric layer process, and only the experimental test wafer performs an interconnection process between two adjacent dielectric layer processes, wherein the dielectric layer process comprises a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process comprises a metal filling sub-process and a metal grinding sub-process; the number of interconnection processes performed by the experimental test wafers of the multiple test units gradually changes, so that the dish-shaped defect values ​​corresponding to the multiple test units gradually change, and the dish-shaped defect value is the difference in film thickness between the film thickness of the top dielectric layer of the experimental test wafer in the test unit and the film thickness of the top dielectric layer of the control test wafer; through the interconnection process defect test structure, the minimum value among the dish-shaped defect values ​​of the test units with abnormalities in all experimental test wafers can be obtained as the critical defect value.

[0007] In some embodiments, the interconnection process defect test structure includes multiple test unit groups with different metal line widths, each of the test unit groups includes multiple test units with the same metal line width, and the critical defect value corresponding to each metal line width can be obtained through the interconnection process defect test structure.

[0008] In some embodiments, the experimental test wafer has an ID, the dielectric layer materials deposited in two consecutive dielectric layer processes are different, or all the dielectric layer processes are the same and each dielectric layer process forms at least two dielectric layers with different materials.

[0009] To solve the above problem, an embodiment of the present invention further provides a method for obtaining a critical defect value of an interconnection process defect test structure, comprising the following steps: preparing a plurality of test units, each of the test units comprising an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer performing the same dielectric layer process, only the experimental test wafer performing an interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of the plurality of test units gradually changes, wherein the dielectric layer process comprises a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process comprises a dielectric layer etching sub-process, a metal filling sub-process and a metal grinding sub-process; obtaining a film thickness difference between a film thickness of a top dielectric layer of the experimental test wafer in each of the test units and a film thickness of a top dielectric layer of the control test wafer as a dish-shaped defect value of the test unit; obtaining the minimum value among the dish-shaped defect values ​​of the test units where abnormalities occur in all experimental test wafers as a critical defect value.

[0010] In some embodiments, the method further includes: preparing multiple test unit groups with different metal line widths, each of the test unit groups including multiple test units with the same metal line width; obtaining the critical defect value of each of the test unit groups, and establishing a comparison table between critical defect value and metal line width.

[0011] To solve the above problem, an embodiment of the present invention further provides an interconnection process defect control method, comprising the following steps: obtaining a target critical defect value for abnormal wafers corresponding to a current batch of wafers; performing the same dielectric layer process on the current batch of wafers and the current control wafers, with only the current batch of wafers performing an interconnection process between two adjacent dielectric layer processes, wherein the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a dielectric layer etching sub-process, a metal filling sub-process and a metal grinding sub-process; obtaining a film thickness difference between the film thickness of the top dielectric layer of the current batch of wafers and the film thickness of the top dielectric layer of the current control wafer as a current dish-shaped defect value; judging whether the current dish-shaped defect value is greater than or equal to the target critical defect value, and if the current dish-shaped defect value is greater than or equal to the target critical defect value, judging that the current batch of wafers is abnormal.

[0012] In some embodiments, after determining that the current batch of wafers is abnormal, the method further includes: re-performing a dielectric layer grinding process on the wafers with the abnormality, and re-obtaining a current dish-shaped defect value for judgment.

[0013] The above technical solution designs a test structure and method that can obtain the dish-shaped defects caused by the interconnection process and obtain the corresponding critical defect value. According to the critical defect value, the layer-by-layer accumulation effect of the dish-shaped defects can be monitored online; when the dish-shaped defects accumulate to the corresponding critical defect value, they can be discovered online in time for card control and remediation to avoid the occurrence of low-quality products. It is also possible to achieve online card control of wafers with different metal line widths by establishing a comparison table of critical defect values ​​and metal line widths. Since the short circuit between wires caused by dish-shaped defects is a layer-by-layer accumulation effect, compared with the prior art, the abnormality cannot be discovered in time, and it cannot be remedied by the WAT test / CP test, and the batches of wafers (Lot) that are overstocked during the period may face the same problem. The present invention can be controlled online in time according to the critical defect value and can take remedial measures to avoid the occurrence of low-quality products and ensure stable product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A schematic diagram of an interconnection process defect test structure provided by an embodiment of the present invention;

[0016] Figure 2 A schematic diagram of the steps of a method for obtaining a critical defect value of an interconnect process defect test structure provided by an embodiment of the present invention.

[0017] Figure 3 A schematic diagram of the steps of an interconnection process defect control method provided by an embodiment of the present invention.

[0018] Description of reference numerals:

[0019] 11 First test unit 12 Second test unit 13 Third test unit

[0020] 111 first experimental test wafer 112 first control test wafer

[0021] 121 second experimental test wafer 122 second control test wafer

[0022] 131 third experimental test wafer 132 third control test wafer

[0023] 100 substrate 101 first dielectric layer 102 second dielectric layer

[0024] 103 third dielectric layer 104 fourth dielectric layer

[0025] 191 first metal layer 192 second metal layer 193 third metal layer DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0027] An embodiment of the present invention provides an interconnection process defect test structure, which includes multiple test units, each of which includes an experimental test wafer and a control test wafer. The experimental test wafer and the control test wafer perform the same dielectric layer process (the number of dielectric layer processes is the same, and the process parameters of each dielectric layer process are the same), and only the experimental test wafer performs an interconnection process between two adjacent dielectric layer processes. Wherein, the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a metal filling sub-process and a metal grinding sub-process. The number of interconnection processes performed by the experimental test wafers of multiple test units gradually changes, so that the dish-shaped defect values ​​corresponding to the multiple test units gradually change, and the dish-shaped defect value is the film thickness difference between the film thickness of the top dielectric layer of the experimental test wafer in the test unit and the film thickness of the top dielectric layer of the control test wafer; through the interconnection process defect test structure, the minimum value of the dish-shaped defect values ​​of the test units with abnormalities in all experimental test wafers can be obtained as the critical defect value.

[0028] See also Figure 1 , which is a schematic diagram of an interconnection process defect test structure provided by an embodiment of the present invention. Figure 1 As shown, the interconnection process defect test structure described in this embodiment includes: a first test unit 11 , a second test unit 12 , and a third test unit 13 .

[0029] The first test unit 11 includes a first experimental test wafer 111 and a first control test wafer 112. The first experimental test wafer 111 and the first control test wafer 112 both perform the same dielectric layer process twice to form a first dielectric layer 101 and a second dielectric layer 102 on the substrate 100. Only the first experimental test wafer 111 performs an interconnection process between two adjacent dielectric layer processes to form a first metal layer 191 on the first dielectric layer 101. The film thickness difference D11 between the film thickness T11 of the top dielectric layer (second dielectric layer 102) of the first experimental test wafer 111 and the film thickness T12 of the top dielectric layer (second dielectric layer 102) of the first control test wafer 112 is used as the dish-shaped defect value of the test unit; that is, the dish-shaped defect value corresponding to the first test unit 11 is D11=T12-T11.

[0030] The second test unit 12 includes a second experimental test wafer 121 and a second control test wafer 122. The second experimental test wafer 121 and the second control test wafer 122 both perform the same dielectric layer process three times to form a first dielectric layer 101, a second dielectric layer 102, and a third dielectric layer 103 on the substrate 100. Only the second experimental test wafer 121 performs an interconnection process between two adjacent dielectric layer processes, that is, only the second experimental test wafer 121 performs two interconnection processes to form a first metal layer 191 on the first dielectric layer 101 and a second metal layer 192 on the second dielectric layer 102. The film thickness difference D21 between the film thickness T21 of the top dielectric layer (third dielectric layer 103) of the second experimental test wafer 121 and the film thickness T22 of the top dielectric layer (third dielectric layer 103) of the second control test wafer 122 is used as the dish-shaped defect value of the test unit; that is, the dish-shaped defect value corresponding to the second test unit 12 is D21=T22-T21, and D21>D11.

[0031] The third test unit 13 includes a third experimental test wafer 131 and a third control test wafer 132. The third experimental test wafer 131 and the third control test wafer 132 both perform the same dielectric layer process four times, forming a first dielectric layer 101, a second dielectric layer 102, a third dielectric layer 103, and a fourth dielectric layer 104 on the substrate 100. Only the third experimental test wafer 131 performs an interconnection process between two adjacent dielectric layer processes, that is, only the third experimental test wafer 131 performs three interconnection processes, forming a first metal layer 191 on the first dielectric layer 101, a second metal layer 192 on the second dielectric layer 102, and a third metal layer 193 on the third dielectric layer 103. The film thickness difference D31 between the film thickness T31 of the top dielectric layer (fourth dielectric layer 104) of the third experimental test wafer 131 and the film thickness T32 of the top dielectric layer (fourth dielectric layer 104) of the third control test wafer 132 is used as the dish-shaped defect value of the test unit; that is, the dish-shaped defect value corresponding to the third test unit 13 is D31=T32-T31, and D31>D21.

[0032] By analogy, the number of interconnection processes performed on the experimental test wafers of multiple test units gradually changes, so that the dish-shaped defect values ​​corresponding to the multiple test units gradually change, that is, the multiple test units reflect the layer-by-layer accumulation effect of the dish-shaped defect values.

[0033] In some embodiments, an electron beam measurement method can be used to measure the film thickness of the top dielectric layer of the experimental test wafer after the current dielectric layer process and the film thickness of the top dielectric layer of the control test wafer online, and the difference in film thickness between the two is obtained as the dish-shaped defect value of the test unit. For the control test wafer, the electron beam measurement can be used with the dielectric layer material deposited by the previous dielectric layer process as the aiming point. For the experimental test wafer, the electron beam measurement can be used with the metal layer formed by the interconnection process before the current dielectric layer process as the aiming point.

[0034] In some embodiments, the dielectric layer materials deposited by two consecutive dielectric layer processes are different, and the metal thickness after the corresponding metal grinding sub-process can be indirectly reflected by measuring the thickness (Thickness) of the top dielectric layer; the top dielectric layer is a single dielectric layer using the corresponding material formed after the current dielectric layer process. The dielectric layer (IMD) materials deposited by two consecutive dielectric layer processes can be selected from one of silicon oxide, silicon oxynitride, and silicon nitride; for example, the dielectric layer material deposited by the previous dielectric layer process can be silicon oxide, and the dielectric layer material deposited by the next dielectric layer process can be silicon oxynitride. For the control test wafer, since the dielectric layers formed by each dielectric layer process can be distinguished by material, the dielectric layer material deposited by the previous dielectric layer process can be used as the aiming point for electron beam measurement. For the experimental test wafer, the metal layer formed by the interconnection process before the current dielectric layer process can be used as the aiming point for electron beam measurement.

[0035] In some embodiments, all the dielectric layer processes are the same, and each dielectric layer process forms at least two dielectric layers of different materials. The metal thickness after the corresponding metal grinding sub-process can be indirectly reflected by measuring the thickness of the top dielectric layer; the top dielectric layer is a multi-layer composite dielectric layer using different materials formed after the current dielectric layer process. For example, the dielectric layer (IMD) material deposited by each dielectric layer process can be a three-layer composite dielectric layer of silicon oxide, silicon oxynitride, and silicon nitride. For the control test wafer, the dielectric layer material corresponding to the topmost dielectric layer deposited by the previous dielectric layer process can be used as the aiming point for electron beam measurement. For the experimental test wafer, the metal layer formed by the interconnection process before the current dielectric layer process can be used as the aiming point for electron beam measurement.

[0036] By setting the number of interconnection processes performed by the experimental test wafer of multiple test units to gradually change, the dish-shaped defect values ​​corresponding to the multiple test units gradually change; that is, the multiple test units reflect the layer-by-layer accumulation effect of the dish-shaped defect values. When the dish-shaped defect values ​​accumulate to the point where the experimental test wafer is abnormal, the minimum value of the dish-shaped defect values ​​of the test units with abnormal experimental test wafers can be obtained as the critical defect value. Specifically, by performing a WAT ​​test or a CP test on the experimental test wafers of all the test units, the test units with abnormal experimental test wafers can be screened out, and then the critical defect value can be obtained.

[0037] In some embodiments, the interconnection process may be a metal copper interconnection process for forming an embedded copper interconnection structure. The anomaly is a copper residual defect causing a short circuit between conductors.

[0038] In some embodiments, multiple test unit groups with different metal line widths can be set, each of which includes multiple test units with the same metal line width, so that the critical defect value corresponding to each metal line width can be obtained. The critical defect value can be used to perform online card control of interconnection process defects.

[0039] Based on the same inventive concept, the present invention also provides a method for obtaining a critical defect value of an interconnection process defect test structure, wherein the method prepares the interconnection process defect test structure described in the above embodiment of the present invention and performs measurement to obtain the corresponding critical defect value, and further establishes a corresponding relationship between the dish-shaped defect value and the number of interconnection processes, which is then used to perform online card control on the interconnection process defects to avoid low-quality products.

[0040] See also Figure 2 , which is a schematic diagram of the steps of a method for obtaining a critical defect value of an interconnection process defect test structure provided by an embodiment of the present invention. Figure 2 As shown, in this embodiment, the method includes the following steps: S21, preparing multiple test units, each of the test units includes an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer perform the same dielectric layer process, only the experimental test wafer performs one interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of multiple test units gradually changes; S22, obtaining the film thickness difference between the film thickness of the top dielectric layer of the experimental test wafer in each of the test units and the film thickness of the top dielectric layer of the control test wafer as the dish-shaped defect value of the test unit; S23, obtaining the minimum value among the dish-shaped defect values ​​of all test units with abnormal experimental test wafers as the critical defect value.

[0041] Regarding step S21, prepare multiple test units, each of which includes an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer perform the same dielectric layer process, only the experimental test wafer performs an interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of multiple test units gradually changes. Among them, the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a dielectric layer etching sub-process, a metal filling sub-process and a metal grinding sub-process. The specific process flow can refer to the existing process, which will not be repeated here. The multiple test units prepared can refer to Figure 1 shown.

[0042] The test unit preparation steps are as follows: (1) The same dielectric layer process is performed on the experimental test wafer and the control test wafer in the same test unit to form a dielectric layer with the same film thickness. (2) A groove for filling metal can be formed only on the experimental test wafer by using a bright field mask (Clear Mask) and a dark field mask (Dark Mask) in combination with a positive photoresist and a negative photoresist, and the experimental test wafer is subjected to an interconnection process. Since materials with different polishing rates are polished simultaneously, the experimental test wafer is prone to local over-polishing of metal lines. (3) The same dielectric layer process is performed on the experimental test wafer and the control test wafer again to generate a dishing defect (Dishing). Since the experimental test wafer has local over-polishing of metal lines, the dielectric layer grinding sub-process in the current dielectric layer process will accumulate this dishing defect, so that the film thickness of the top dielectric layer of the experimental test wafer after the current dielectric layer process and the film thickness of the top dielectric layer of the control test wafer are measured respectively in the subsequent process. The dishing defect value of the test unit after the current dielectric layer process can be obtained based on the difference in film thickness between the two. As needed, repeat the above steps (2) to (3) to form a test unit in which the experimental test wafer has performed the corresponding number of interconnection processes. Among them, in the dark field mask, most areas are opaque, and only the pattern area that needs to be transferred to the wafer is translucent; during the exposure process, only these small translucent areas can allow ultraviolet light to irradiate the photoresist; in this way, the photoresist irradiated by light undergoes chemical changes, while most of the remaining areas remain unexposed. The bright field mask is just the opposite, and its design feature is that most areas are translucent. In the positive photoresist process, after the coating is exposed and developed, the exposed part is dissolved and the unexposed part remains. In the negative photoresist process, after the coating is exposed and developed, the exposed part is retained and the unexposed part is dissolved.

[0043] In some embodiments, the experimental test wafer has an ID, and the step of preparing multiple test units specifically includes: providing a process machine and a process menu, wherein the process menu includes configuring the process machine to perform the interconnection process after completing the current dielectric layer process and when the ID of the experimental test wafer is identified. Thus, the experimental test wafer only performs one interconnection process between two adjacent dielectric layer processes.

[0044] In some embodiments, the dielectric layer materials deposited in two consecutive dielectric layer processes are different, or all the dielectric layer processes are the same and each dielectric layer process forms at least two dielectric layers of different materials.

[0045] Regarding step S22, a film thickness difference between the film thickness of the top dielectric layer of the experimental test wafer and the film thickness of the top dielectric layer of the control test wafer in each test unit is obtained as the dishing defect value of the test unit.

[0046] Specifically, the film thickness of the top dielectric layer of the experimental test wafer after the current dielectric layer process and the film thickness of the top dielectric layer of the control test wafer can be measured online by electron beam measurement, and the difference in film thickness between the two can be obtained as the dish-shaped defect value of the test unit. For the control test wafer, the electron beam measurement can be used with the dielectric layer material deposited by the previous dielectric layer process as the aiming point. For the experimental test wafer, the electron beam measurement can be used with the metal layer formed by the interconnection process before the current dielectric layer process as the aiming point.

[0047] In some embodiments, the dielectric layer materials deposited by two consecutive dielectric layer processes are different, and the metal thickness after the corresponding metal grinding sub-process can be indirectly reflected by measuring the thickness (Thickness) of the top dielectric layer; the top dielectric layer is a single dielectric layer using the corresponding material formed after the current dielectric layer process. The dielectric layer (IMD) materials deposited by two consecutive dielectric layer processes can be selected from one of silicon oxide, silicon oxynitride, and silicon nitride; for example, the dielectric layer material deposited by the previous dielectric layer process can be silicon oxide, and the dielectric layer material deposited by the next dielectric layer process can be silicon oxynitride. For the control test wafer, since the dielectric layers formed by each dielectric layer process can be distinguished by material, the dielectric layer material deposited by the previous dielectric layer process can be used as the aiming point for electron beam measurement. For the experimental test wafer, the metal layer formed by the interconnection process before the current dielectric layer process can be used as the aiming point for electron beam measurement.

[0048] In some embodiments, all the dielectric layer processes are the same, and each dielectric layer process forms at least two dielectric layers of different materials. The metal thickness after the corresponding metal grinding sub-process can be indirectly reflected by measuring the thickness of the top dielectric layer; the top dielectric layer is a multi-layer composite dielectric layer using different materials formed after the current dielectric layer process. For example, the dielectric layer (IMD) material deposited by each dielectric layer process can be a three-layer composite dielectric layer of silicon oxide, silicon oxynitride, and silicon nitride. For the control test wafer, the dielectric layer material corresponding to the topmost dielectric layer deposited by the previous dielectric layer process can be used as the aiming point for electron beam measurement. For the experimental test wafer, the metal layer formed by the interconnection process before the current dielectric layer process can be used as the aiming point for electron beam measurement.

[0049] Regarding step S23, the minimum value among the dish-shaped defect values ​​of the test units with abnormalities in all experimental test wafers is obtained as the critical defect value.

[0050] In some embodiments, the step S23 specifically includes: (1) performing a WAT ​​test or a CP test on the experimental test wafers of all the test units to screen out the test units with abnormal experimental test wafers; (2) obtaining the minimum value of the dish-shaped defect values ​​of the test units with abnormal experimental test wafers as the critical defect value. By setting the number of interconnection processes performed by the experimental test wafers of multiple test units to gradually change, the dish-shaped defect values ​​corresponding to the multiple test units gradually change; that is, the multiple test units reflect the layer-by-layer accumulation effect of the dish-shaped defect values. When the dish-shaped defect values ​​accumulate to the point where the experimental test wafer is abnormal, the minimum value of the dish-shaped defect values ​​of the test units with abnormal experimental test wafers can be obtained as the critical defect value. Specifically, the WAT test or the CP test can be performed on the experimental test wafers of all the test units to screen out the test units with abnormal experimental test wafers, and then the critical defect value can be obtained. WAT (Wafer Acceptance Test) is also called process control monitoring (Process Control Monitor, PCM). WAT measures the electrical parameters of specific test structures after the wafer product is taped out and before quality inspection. The purpose of WAT is to detect the process conditions of each wafer product by testing the electrical parameters of specific test structures on the wafer, evaluate the quality and stability of the semiconductor manufacturing process, and determine whether the wafer product meets the electrical specification requirements of the process technology platform. CP (Chip Probing), CP testing is between wafer manufacturing and packaging in the entire chip manufacturing process, and usually includes voltage, current, timing and function verification.

[0051] In some embodiments, the interconnection process may be a metal copper interconnection process for forming an embedded copper interconnection structure. The anomaly is a copper residual defect causing a short circuit between conductors.

[0052] In this embodiment, the method further includes: S24, preparing a plurality of test unit groups with different metal line widths, each of the test unit groups including a plurality of test units with the same metal line width; and S25, obtaining the critical defect value of each of the test unit groups, and establishing a comparison table between the critical defect value and the metal line width. Step S24 can be performed simultaneously with step S21.

[0053] For the metal copper interconnection process, the main reason for the dishing defect is that during the CMP process, due to the different physical and chemical properties of copper and dielectric layer materials, the polishing rates of different materials are also inconsistent. The copper removal rate is too fast and the dielectric layer material is removed slowly, which easily causes local over-polishing of the copper wire and produces serious dishing defects. As the copper line width increases, the copper density (Density) also increases, and the dishing defect also tends to increase. By setting up multiple test unit groups with different metal line widths, each of the test unit groups includes multiple test units with the same metal line width, so that the critical defect value corresponding to each metal line width can be obtained. The critical defect value can be used to perform online card control of interconnection process defects.

[0054] Based on the same inventive concept, the present invention also provides an interconnection process defect control method.

[0055] See also Figure 3 , which is a schematic diagram of the steps of the interconnection process defect control method provided by an embodiment of the present invention. Figure 3 As shown, in this embodiment, the method includes the following steps: S31, obtaining a target critical defect value of an abnormal wafer corresponding to the current batch of wafers; S32, performing the same dielectric layer process on the current batch of wafers and the current control wafer, and only the current batch of wafers performs an interconnection process between two adjacent dielectric layer processes; S33, obtaining a film thickness difference between the film thickness of the top dielectric layer of the current batch of wafers and the film thickness of the top dielectric layer of the current control wafer as a current dish-shaped defect value; S34, judging whether the current dish-shaped defect value is greater than or equal to the target critical defect value, if the current dish-shaped defect value is greater than or equal to the target critical defect value, it is determined that the current batch of wafers is abnormal.

[0056] Regarding step S31, the target critical defect value of the wafers corresponding to the current batch of wafers is obtained. Figure 1-2 The interconnection process defect test structure and critical defect value acquisition method shown are used to obtain the target critical defect value of the wafer corresponding to the current batch of wafers that has an abnormality.

[0057] In some embodiments, step S31 specifically includes: (11) preparing multiple test units, each of which includes an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer have the same metal line width as the current batch of wafers, the experimental test wafer and the control test wafer perform the same dielectric layer process, only the experimental test wafer performs one interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of multiple test units gradually changes. Among them, the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a dielectric layer etching sub-process, a metal filling sub-process and a metal grinding sub-process. For details, please refer to Figure 1-2 (12) Obtain the difference in film thickness between the top dielectric layer of the experimental test wafer and the top dielectric layer of the control test wafer in each of the test units as the dish defect value of the test unit. Figure 1-2 The electron beam measurement method is used for online measurement. (13) The minimum value of the dish-shaped defect values ​​of all test units with abnormal test wafers is obtained as the target critical defect value. Figure 1-2 The WAT test or CP test method screens out test units with abnormalities in the experimental test wafer.

[0058] In some embodiments, step S31 specifically includes: (21) preparing multiple test unit groups with different metal line widths, each of the test unit groups includes multiple test units with the same metal line width, each of the test units includes an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer perform the same dielectric layer process, only the experimental test wafer performs one interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of the multiple test units gradually changes. Among them, the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a dielectric layer etching sub-process, a metal filling sub-process and a metal grinding sub-process. For details, please refer to Figure 1-2 (22) Obtain the difference in film thickness between the top dielectric layer of the experimental test wafer and the top dielectric layer of the control test wafer in each of the test units as the dish defect value of the test unit. Figure 1-2 The electron beam measurement method is used for online measurement. (23) The minimum value of the dish-shaped defect values ​​of all test units with abnormal test wafers is obtained as the critical defect value, and a comparison table of critical defect values ​​and metal line width is established. Specifically, Figure 1-2The WAT test or CP test method selects the test units with abnormalities in the experimental test wafer. (24) The comparison table is searched according to the metal line width of the current batch of wafers to obtain the corresponding critical defect value as the target critical defect value.

[0059] Regarding step S32, the same dielectric layer process is performed on the current batch of wafers and the current reference wafer, and only the current batch of wafers performs an interconnection process between two adjacent dielectric layer processes. The reference wafer can be set in the same manner as the test unit of the present invention to monitor the dishing defect value.

[0060] Regarding step S33, the thickness difference between the top dielectric layer of the current batch of wafers and the top dielectric layer of the current reference wafer is obtained as the current dishing defect value. Figure 1-2 The electron beam measurement method performs online measurement. The number of executions of the dielectric layer process can be set to start from 2 times, and each time the dielectric layer process is executed, the current dish defect value is obtained once.

[0061] Regarding step S34, it is determined whether the current dish-shaped defect value is greater than or equal to the target critical defect value. If the current dish-shaped defect value is greater than or equal to the target critical defect value, it is determined that the current batch of wafers is abnormal. By comparing the current dish-shaped defect value with the target critical defect value, it is possible to directly determine whether the current batch of wafers is abnormal without using a complex test pattern (Test Key) or waiting until the process is completed before performing a WAT ​​test or a CP test. Wafers with severe dish-shaped defects can be discovered in a timely manner to avoid short circuits between wires that cause poor quality.

[0062] In some embodiments, after determining that the current batch of wafers is abnormal, the method further includes: re-performing the dielectric layer grinding process on the wafers with the abnormality, and re-obtaining the current dishing defect value for judgment. That is, for wafers that exceed the target critical defect value of the current batch of wafers, re-grinding (CMP Rework) is performed to avoid short circuits between wires and resulting in low-quality products. It is also possible to stop the machine online for inspection to troubleshoot the causes of dishing defects (Dishing) and process instability, and make timely adjustments to avoid more wafers being affected.

[0063] From the above content, it can be seen that the present invention designs a test structure and method that can obtain the dish-shaped defects caused by the interconnection process and obtain the corresponding critical defect value. According to the critical defect value, the layer-by-layer accumulation effect of the dish-shaped defects can be monitored online; when the dish-shaped defects accumulate to the corresponding critical defect value, they can be discovered online in time for card control and remediation to avoid the occurrence of low-quality products. It is also possible to achieve online card control of wafers with different metal line widths by establishing a comparison table of critical defect values ​​and metal line widths. Since the short circuit between wires caused by dish-shaped defects is a layer-by-layer accumulation effect, compared with the prior art, the abnormality cannot be discovered in time, and it cannot be remedied by the WAT test / CP test, and the wafers in the batches (Lot) during the period may face the same problem. The present invention can be controlled online in time according to the critical defect value and can take remedial measures to avoid the occurrence of low-quality products and ensure stable product quality.

[0064] It should be noted that the terms "including" and "having" and their variations involved in the document of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates, and it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context, and can be used to describe features, structures or characteristics in a singular sense, or can be used to describe features, structures or combinations of features in a plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow the presence of other factors that are not necessarily explicitly described. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0065] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An interconnection process defect test structure, characterized in that: include: Multiple test units; Each of the test units includes an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer are subjected to the same dielectric layer process, and only the experimental test wafer is subjected to an interconnection process between two adjacent dielectric layer processes, wherein the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a metal filling sub-process and a metal grinding sub-process; The number of interconnection processes performed on the experimental test wafers of the multiple test units gradually changes, so that the dish-shaped defect values ​​corresponding to the multiple test units gradually change, and the dish-shaped defect value is the film thickness difference between the film thickness of the top dielectric layer of the experimental test wafer in the test unit and the film thickness of the top dielectric layer of the control test wafer; The interconnection process defect test structure can be used to obtain the minimum value among the dish-shaped defect values ​​of the test units with abnormalities in all experimental test wafers as a critical defect value.

2. The interconnection process defect test structure according to claim 1, characterized in that: It comprises a plurality of test unit groups with different metal line widths, each of the test unit groups comprises a plurality of test units with the same metal line width, and the critical defect value corresponding to each metal line width can be obtained through the interconnection process defect test structure.

3. The interconnection process defect test structure according to claim 1, characterized in that: The experimental test wafer has an ID; The dielectric layer materials deposited by two consecutive dielectric layer processes are different, or all the dielectric layer processes are the same and each dielectric layer process forms at least two dielectric layers with different materials.

4. A method for obtaining a critical defect value of an interconnect process defect test structure, characterized in that: The steps include: Prepare a plurality of test units, each of the test units includes an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer perform the same dielectric layer process, only the experimental test wafer performs an interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of the plurality of test units gradually changes, wherein the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a dielectric layer etching sub-process, a metal filling sub-process and a metal grinding sub-process; Obtaining a film thickness difference between a film thickness of a top dielectric layer of an experimental test wafer and a film thickness of a top dielectric layer of a control test wafer in each of the test units as a dishing defect value of the test unit; The minimum value among the dish-shaped defect values ​​of the test units with abnormalities in all experimental test wafers is obtained as the critical defect value.

5. The method according to claim 4, characterized in that The method further comprises: Prepare a plurality of test unit groups with different metal line widths, each of the test unit groups comprising a plurality of the test units with the same metal line width; The critical defect value of each test unit group is obtained, and a comparison table of critical defect value and metal line width is established.

6. The method according to claim 4, characterized in that The dielectric layer materials deposited by two consecutive dielectric layer processes are different, or all the dielectric layer processes are the same, and each dielectric layer process forms at least two dielectric layers with different materials; the step of obtaining the film thickness difference between the film thickness of the top dielectric layer of the experimental test wafer and the film thickness of the top dielectric layer of the control test wafer in each of the test units as the dish defect value of the test unit specifically includes: The electron beam measurement method is used to measure the film thickness of the top dielectric layer of the experimental test wafer after the current dielectric layer process and the film thickness of the top dielectric layer of the control test wafer online, and the film thickness difference between the two is obtained as the dish defect value of the test unit.

7. The method according to claim 4, characterized in that The step of obtaining the minimum value of the dish-shaped defect values ​​of all test units with abnormalities in the experimental test wafer as the critical defect value specifically includes: Performing WAT test or CP test on the experimental test wafers of all the test units to screen out the test units with abnormal experimental test wafers; The minimum value among the dish-shaped defect values ​​of the test units in which abnormalities occur in all experimental test wafers is obtained as the critical defect value.

8. A method for controlling interconnection process defects, characterized in that: The steps include: Obtaining target critical defect values ​​of wafers corresponding to the current batch of wafers that have abnormalities; Performing the same dielectric layer process on the current batch of wafers and the current control wafers, except that the current batch of wafers performs an interconnection process between two adjacent dielectric layer processes, wherein the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a dielectric layer etching sub-process, a metal filling sub-process, and a metal grinding sub-process; Obtaining a film thickness difference between a film thickness of a top dielectric layer of a current batch of wafers and a film thickness of a top dielectric layer of a current reference wafer as a current dishing defect value; It is determined whether the current dish-shaped defect value is greater than or equal to the target critical defect value. If the current dish-shaped defect value is greater than or equal to the target critical defect value, it is determined that the current batch of wafers is abnormal.

9. The method according to claim 8, characterized in that The step of obtaining the target critical defect value of wafer abnormality corresponding to the current batch of wafers specifically includes: Prepare a plurality of test units, each of the test units includes an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer have the same metal line width as the current batch of wafers, the experimental test wafer and the control test wafer perform the same dielectric layer process, only the experimental test wafer performs one interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of the plurality of test units gradually changes; Obtaining a film thickness difference between a film thickness of a top dielectric layer of an experimental test wafer and a film thickness of a top dielectric layer of a control test wafer in each of the test units as a dishing defect value of the test unit; The minimum value among the dish-shaped defect values ​​of the test units with abnormalities in all experimental test wafers is obtained as the target critical defect value.

10. The method according to claim 8, characterized in that The step of obtaining the target critical defect value of wafer abnormality corresponding to the current batch of wafers specifically includes: Prepare multiple test unit groups with different metal line widths, each of the test unit groups includes multiple test units with the same metal line width, each of the test units includes an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer perform the same dielectric layer process, only the experimental test wafer performs an interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of the multiple test units gradually changes; Obtaining a film thickness difference between a film thickness of a top dielectric layer of an experimental test wafer and a film thickness of a top dielectric layer of a control test wafer in each of the test units as a dishing defect value of the test unit; The minimum value of the dish-shaped defect values ​​of the test units with abnormalities in all experimental test wafers is obtained as the critical defect value, and a comparison table between the critical defect value and the metal line width is established; The comparison table is searched according to the metal line width of the current batch of wafers to obtain the corresponding critical defect value as the target critical defect value.

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