Reducing click and flip-flop noise in amplifiers

Abstract

The invention relates to reduction of click and flip-flop noise in amplifiers. In an example, a system (100) includes a loop filter (104) that includes one or more integrators (106). The system (100) includes a ramp generator (108). The system (100) includes a comparator (110) having a first input coupled to an output of the loop filter (104), a second input coupled to an output of the ramp generator (108), and having an output. The system (100) includes a muting loop (128) coupled to an input of the loop filter (104) and the output of the comparator (110). The system (100) includes a power stage (116) having an input coupled to the output of the comparator (110) and having an output. The system (100) includes a major loop (132) coupled to the output of the power stage (116) and the input of the loop filter (104). The system (100) includes an integral error detector having an input coupled to the loop filter (104) and having an output. The system (100) includes a dual comparator having an input coupled to the output of the integral error detector.

Description

Technical Field

[0001] The present disclosure relates generally to circuits, and more particularly to reducing click and pop noise in amplifiers. Background Art

[0002] Amplifiers are used to amplify signals, such as audio signals. However, artifacts may be generated when using amplifiers. For example, a Class D amplifier is an amplifier in which an amplifying device (e.g., a transistor) operates as a switch. The amplifying device operates by rapidly switching back and forth between power rails, using pulse width modulation or related techniques to produce a pulse train output. The pulse train output passes through a low pass filter that blocks high frequency pulses and provides an analog output current and voltage. In audio applications, a speaker may act as a low pass filter. However, when using a Class D amplifier, artifacts such as pops and clicks may be audible. Summary of the invention

[0003] In at least one example described, a system includes a loop filter, the loop filter including one or more integrators, the loop filter having an input and an output. The system also includes a ramp generator having an output. The system includes a comparator, the comparator having a first input coupled to the output of the loop filter and a second input coupled to the output of the ramp generator and having an output. The system also includes a mute loop, the mute loop coupled to the input of the loop filter and the output of the comparator. The system includes a power stage, the power stage having an input coupled to the output of the comparator and having an output. The system also includes a main loop, the main loop coupled to the output of the power stage and the input of the loop filter. The system includes an integral error detector, the integral error detector having an input coupled to the loop filter and having an output. The system also includes a dual comparator, the dual comparator having an input coupled to the output of the integral error detector and having an output.

[0004] In at least one example described, a system includes an amplifier. The amplifier includes a loop filter, the loop filter including one or more integrators, the loop filter having an input and an output. The amplifier includes a ramp generator having an output. The amplifier also includes a comparator, the comparator having a first input coupled to the output of the loop filter and a second input coupled to the output of the ramp generator and having an output. The amplifier includes a power stage, the power stage having an input coupled to the output of the comparator and having an output. The amplifier also includes a mute loop, the mute loop coupled to the input of the loop filter and the output of the comparator. The amplifier includes a main loop, the main loop coupled to the output of the power stage and the input of the loop filter. The amplifier also includes an integral error detector, the integral error detector having an input coupled to the loop filter and having an output. The amplifier includes a dual comparator, the dual comparator having an input coupled to the output of the integral error detector. The amplifier also includes an AND gate, the AND gate having an input coupled to the dual comparator and having an output. The amplifier includes a latch, the latch having an input coupled to the output of the AND gate and having an output.

[0005] In at least one example described, a system includes a loop filter, the loop filter including one or more integrators, the loop filter having an input and an output. The system also includes a ramp generator having an output, the ramp generator configured to provide a ramp signal. The system includes a comparator, the comparator having a first input coupled to the output of the loop filter and a second input coupled to the output of the ramp generator and having an output, the comparator configured to receive the ramp signal from the ramp generator. The system also includes a power stage, the power stage having an input coupled to the output of the comparator and having an output. The system includes a mute loop, the mute loop coupled to the input of the loop filter and the output of the comparator, the mute loop configured to provide feedback in a first state of the amplifier. The system also includes a main loop, the main loop coupled to the output of the power stage and the input of the loop filter, the main loop configured to provide feedback in a second state of the amplifier. The system includes an integral error detector, the integral error detector having an input coupled to the loop filter and having an output, the integral error detector configured to detect a voltage error in the loop filter. The system also includes a dual comparator having an input coupled to the output of the integrated error detector and having an output, the dual comparator configured to compare the voltage error to a reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Circuitry including an example amplifier with reduced click and pop noise is depicted.

[0007] Figure 2 is a graph illustrating waveforms of how click and pop noises may occur.

[0008] Figure 3 Circuitry including an example amplifier with reduced click and pop noise is depicted.

[0009] Figure 4 For illustration purposes Figure 1 and 3 A graph of the waveform of how a circuit arrangement can reduce click and pop noise.

[0010] Figure 5 An example graph of A-weighted crackle values.

[0011] Figure 6 is a flow chart of an example method for switching between a mute loop and a main loop in an amplifier.

[0012] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0013] In an example, a Class D amplifier has a high loop gain in the audio band (e.g., 20 Hz to 20 KHz) and has a flat closed loop frequency response. The Class D amplifier receives an input signal that passes through a high-order loop filter. The input signal is compared to a ramp generator signal at a fixed carrier frequency. Pulse Width Modulation (PWM) generates a stream of pulses at the carrier frequency. The width of each pulse is proportional to the amplitude of the input signal. The PWM signal is then sent to an output stage, also referred to as a power stage that may include an H-bridge. Finally, the signal is filtered again and provided at the output, for example, to a speaker.

[0014] A Class D amplifier may include two feedback loops. For example, some Class D amplifiers include a main feedback loop and a mute loop (also called a virtual feedback loop). The main feedback loop provides feedback from the output of the Class D amplifier to the input in a first operating state (e.g., "normal" operation). The mute loop provides feedback from the signal path to the input in a second operating state of the Class D amplifier, such as for powering on or off the amplifier. The power stage of the amplifier operates as a high voltage level shifter that can drive high voltages and high currents. For example, the power stage increases the power output of the amplifier.

[0015] If the main feedback loop is connected and operates when the amplifier is powered on or off, this loop may generate a ringing signal or overshoot at the output of the amplifier because the PWM pulse is provided to the power stage before the signal is stable. Therefore, in some amplifiers, a mute loop is provided. The mute loop is a virtual feedback loop that allows the signal in the amplifier to stabilize before the PWM pulse is provided to the power stage. A controller and / or a switch circuit system can be used to switch between the main feedback loop and the mute loop. For example, when the amplifier is powered on or off, the switch circuit system couples the mute loop to the input and decouples the main loop, so that the input signal is not always sent through the signal path. Some systems switch to the main feedback loop after the power-on process runs for a certain amount of time. However, high-frequency oscillations may always exist in high-order loop filters. If the amplifier exits the mute loop when the oscillation is at a high value, these oscillations may generate clicks and crackling noises. Due to the randomness of the device noise, crackling sounds of various sizes may occur in different iterations of the power-on or power-off process.

[0016] In the examples herein, the state of a signal in a monitoring loop filter, referred to as an error signal or an integrated error signal, is monitored. In response to an error signal (e.g., a voltage error) in the loop filter being below a threshold or not within a threshold range, the system switches from a main feedback loop to a mute loop, or vice versa. Compared to other systems, switching between loops in response to an error signal being below a threshold or not within a threshold range reduces click or crackle noise. Any suitable hardware, logic, or circuit system may be used to monitor and detect the error signal. The examples herein use area and power efficient hardware to sense the error signal. In addition, the examples herein may provide deterministic and limited weighted crackle values. The crackle value is deterministic because crackle occurs only when the error signal is below a threshold, and the crackle value is limited by the magnitude of the threshold. The user may set the threshold higher or lower to achieve a specific performance metric, such as a maximum crackle value.

[0017] Figure 1An example circuit system 100 is shown that includes or operates as an amplifier that can reduce click and pop noise compared to some other circuit arrangements. The circuit system 100 operates as a class D amplifier that amplifies an input signal to produce an output signal. The circuit system 100 includes a differential input 102, adders 103A and 103B, a loop filter 104 including one or more integrators 106, and a ramp generator 108. The circuit system 100 also includes comparators 110A and 110B (individually referred to as comparators 110, or collectively referred to as comparators 110). The circuit system 100 includes switch circuitry 112, also referred to as switches 112, switch controls (circuits) 114, and an output or power stage 116. Circuit system 100 also includes resistor 118, inductor 120, filter 122 (e.g., output filter), A-weighted filter 124, and output terminal 126 (in this case, the output terminal is the output of A-weighted filter 124). In one example, all elements of circuit system 100 are included on the same integrated circuit (IC) chip. In another example, all elements of circuit system 100 are included in the same IC package on multiple chips.

[0018] In this example arrangement, the circuit system 100 has a signal path from the differential input 102 to the output terminal 126, a main (feedback) loop 132 coupled from the output of the power stage 116 to the differential input 102, and a mute or dummy (feedback) loop 128 coupled from the signal path (in this case from the output of the switch 112) to the differential input 102. Thus, the switch 112, responsive to a control signal from the switch control 114, can be used to switch between the main loop 132 and the mute loop 128. In an example, the switch 112 includes any circuitry suitable for switching between loops, such as one or more transistor switches.

[0019] As shown, the mute loop 128 includes a loop 128A (e.g., a positive (P) branch of the loop) and a loop 128B (e.g., a negative (M) branch of the loop), each coupled between the switch 112 and the differential input 102. The mute loop 128 includes a mute level shifter 130A on the loop 128A and a mute level shifter 130B on the loop 128B. In an example, the mute level shifters 130A and 130B include circuitry to increase or decrease the value of the feedback signal from the output of the comparator 110 to an appropriate level for providing feedback to the loop filter 104. The mute level shifters 130A and 130B may include any suitable level shifting circuitry, such as a voltage divider, a Schmitt trigger, or a transistor circuit. The main loop 132 includes a loop 132A (e.g., a positive (P) branch of the loop) and a loop 132B (e.g., a negative (M) branch of the loop). As shown, loops 132A and 132B are represented as direct connections from the output of power stage 116 to differential input 102. However, loop 132A and / or loop 132B may include any suitable circuitry, such as to adjust an input signal at differential input 102 in response to an output signal from the output of power stage 116 and / or to scale the output signal. Figure 1 Also depicted are several signals such as input signal 134 , PWM signals 136A (PWM_OUTP) and 136B (PWM_OUTM), mute loop signals 138A (OUTP_MUTE) and 138B (OUTM_MUTE), power stage output signals OUTP 140A and OUTM 140B, and output signal 142 .

[0020] Circuit system 100 also includes adders 103A and 103B. Adder 103A has inputs coupled to differential input 102, mute loop 128A, and main loop 132A. Adder 103A has an output coupled to loop filter 104. Adder 103B has inputs coupled to differential input 102, mute loop 128B, and main loop 132B. Adder 103B has an output coupled to loop filter 104. Adders 103A and 103B combine the appropriate feedback signal (from main loop 132 or mute loop 128) with differential input signal 134.

[0021] The loop filter 104 includes an output coupled to the switch control 114 and an output coupled to the comparator 110. In an example, the loop filter 104 includes one or more integrators 106 to integrate the input signal 134. The loop filter 104 includes outputs that provide PWM signals 136A (PWM_OUTP) and 136B (PWM_OUTM) to the comparators 110A and 110B, respectively.

[0022] Comparators 110A and 110B each have two inputs and one output. One input of each comparator 110 receives a PWM signal (PWM signal 136A or 136B) from loop filter 104. Another input of each comparator 110 receives a ramp signal from the output of ramp generator 108. Each comparator 110 generates an output signal at its output, which is provided to switch 112.

[0023] The switch 112 receives the output signal from the comparator 110 at an input of the switch 112. Another input of the switch 112 is coupled to a switch control 114. The switch control 114 is any hardware, logic, or circuit system that controls the operation of the switch 112 in response to a signal detected in the loop filter 104. The switch control 114 includes an output that provides an output signal to the switch 112. The switch 112 has an output coupled to the mute loop 128 and an output coupled to an input of the power stage 116. In one state, the switch 112 provides the output signal to the mute loop 128. In another state, the switch 112 provides the output signal to the power stage 116. The switch control 114 controls where the output signal of the switch 112 is provided. As shown, the switch control 114 has an input coupled to the output of the loop filter 104. In an example, the switch control 114 detects a signal from the loop filter 104 and controls the switch 112 in response to the detected signal from the loop filter 104. Further to this example, switch control 114 provides control signals to switch 112. The control signals may include one or more control signals that turn one or more switches on and off. For example, the control signals include one or more gate control signals provided to one or more transistors of switch 112, which operate as one or more switches.

[0024] In this example, the power stage 116 is implemented as an H-bridge. The power stage 116 has an input receiving an output signal from the switch 112. The power stage 116 has an output coupled to a resistor 118 and an inductor 120. The power stage 116 generates power stage output signals OUTP 140A and OUTM 140B (e.g., differential signals) at its output. The power stage output signals OUTP 140A and OUTM 140B are provided to the main loop 132, which couples the output of the power stage 116 to the differential input 102. The power stage output signals OUTP 140A and OUTM 140B are also provided to a filter 122, which provides the output signal to an A-weighted filter 124. The filter 122 filters the signal from the power stage 116, and may include a low-pass filter, a band-pass filter, or other suitable filters. The A-weighted filter 124 is a filter that approximates the frequency sensitivity of the human ear. A-weighted filter 124 has an output terminal 126 that produces an output signal 142 .

[0025] In example operation, the circuit system 100 uses either the mute loop 128 or the main loop 132. As an example, during power-on operation, the circuit system 100 may start in the mute loop 128. Powering on using the mute loop 128 prevents noise in the circuit system 100 from being passed to the output of the amplifier during power-on operation. To use the mute loop 128, the switch 112 couples the output of the comparator 110 to the mute loop 128. The mute loop 128 couples the output of the comparator 110 to the differential input 102. The switch control 114 controls the operation of the switch 112. Through the mute loop 128, no signal is provided to the power stage 116, thus allowing the system to stabilize before switching to the main loop 132.

[0026] After power-on is complete, for example, the circuit system 100 switches from the mute loop 128 to the main loop 132. The switch control 114 controls the switch 112 to disengage the mute loop 128 and engage the main loop 132. To engage the main loop 132, the switch 112 is disconnected from the mute loop 128 and couples the output of the comparator 110 to the power stage 116. Thereafter, a signal from the output of the comparator 110 is provided to the power stage 116. The power stage output signals OUTP 140A and OUTM 140B are provided to the main loop 132, which couples the output of the power stage 116 to the differential input 102. The power stage output signals OUTP 140A and OUTM 140B are also provided to the filter 122, and an output signal 142 is generated.

[0027] In some systems, during power on or power off, after a set amount of time has passed, the switch 112 switches from the mute loop 128 to the main loop 132 (or vice versa). However, switching at a fixed time may cause the switch to occur when the noise in the circuit system 100 is at a high point, thereby causing crackling at the output. In the example herein, the switch 112 switches from the mute loop 128 to the main loop 132 (or vice versa) only when the signal in the loop is below a threshold or is not within a threshold range. The circuit system in the switch control 114 is used to monitor or detect the signal. The switch occurs in response to the signal being below a threshold or within a threshold, for example, in response to an error signal being below a threshold or within a threshold. This results in reduced click and crackle noise. In the example described below, the integrator 106 in the cross-loop filter 104 monitors the integrated error value. The switch control 114 detects the integrated error value and provides a signal to the switch 112 to switch between loops at the appropriate time.

[0028] Figure 2 Graph 200 is a graph of waveforms used to illustrate how click and pop noises may occur. Graph 200 includes waveforms 202, 204, 206, and 208. Points 210, 212, and 214 are also shown in graph 200.

[0029] Waveform 202 is an example of an integrated error signal across integrator 106. Integrated error signal 202 represents a signal obtained from loop filter 104. In an example, integrated error signal 202 represents a differential signal obtained from loop filter 104. In another example, integrated error signal 202 represents the difference between two components of the differential signal obtained from the first output and the second output of integrator 106 of loop filter 104. For waveform 202, the x-axis is time in microseconds, and the y-axis is voltage in millivolts (mV). Therefore, each time point on waveform 202 can be considered as an "integrated error value", which is a voltage value in this example. Waveforms 204, 206, and 208 are examples of exit points representing the mute loop 128. In particular, waveforms 204, 206, and 208 show three different signals indicating different points in time at which the switch 112 switches between the mute loop 128 and the main loop 132 in response to the enable signal being asserted, e.g., changing from a logic low value (e.g., 0V) to a logic high value (e.g., 1V). For waveforms 204, 206, and 208, the x-axis is time in microseconds and the y-axis is voltage in volts (V).

[0030] Waveform 204 represents a mute loop exit point in response to an enable signal asserted at time t1 of approximately 4 microseconds (e.g., corresponding to point 210 on waveform 202). Waveform 206 shows a mute loop exit point in response to an enable signal asserted at time t2 of approximately 22 microseconds (e.g., corresponding to point 212 on waveform 202). Waveform 208 shows a mute loop exit point in response to an enable signal asserted at time t3 of approximately 74 microseconds (e.g., corresponding to point 214 on waveform 202). In an example, the value of the integral error at the time of the exit point (e.g., the x-axis value of waveform 202) corresponds to or correlates with the magnitude of the crackle. If the integral error value is high when the switch occurs, a high crackle is generated. If the integral error value is low when the switch occurs, a low crackle is generated. In the examples herein, the value of the integral error is monitored, and the switch occurs only when the integral error is below or within a threshold.

[0031] Figure 3 A circuit system including an example amplifier with reduced click and pop noise is depicted. Circuit system 300 represents a portion of a Class D amplifier that amplifies an input signal to produce an output signal. Some components in circuit system 300 are described above with respect to circuit system 100, and like reference numerals represent like components. Some components in circuit system 100 are not shown in circuit system 300, but in some examples, the operation of circuit system 100 and circuit system 300 are similar.

[0032] The circuit system 300 includes a differential input 102, an integrator 106 (e.g., 106A, 106B, 106C, and 106D), a ramp generator 108, a comparator 110, a switch 112, a switch control 114, and a power stage 116. The circuit system 300 also includes a mute loop 128 (e.g., loops 128A and 128B), mute level shifters 130A and 130B, and a main loop 132 (e.g., loops 132A and 132B). The circuit system 300 also includes a summer 302. The switch control 114 includes an integral error detector 304 and a dual comparator 306, which includes comparators 308A and 308B. The switch control 114 includes an AND gate 310 and a latch 312, which may be implemented using other logic circuit systems that perform related functions. Figure 1 Several signals are also shown, including a reference voltage (V REF )314, EN_MUTE signal 316 and EN_MUTE_FINAL signal 318.

[0033] In this example, the circuit system 300 includes four integrators 106. Each integrator 106 includes an amplifier 320 and a capacitor 322. The circuit system 300 also includes a number of resistors 324A to 324R. Each of the integrators 106 generates an output voltage that is the integral of the input voltage of the integrator over time. The output signals of the integrators 106 are summed or combined at the summer 302 to provide the final loop filter output signal to the comparator 110.

[0034] In circuit system 300, integrator 106A has two inputs coupled to the outputs of adders 103A and 103B. Integrator 106A has two outputs coupled to resistors 324C and 324D. The output of integrator 106A is also coupled to integral error detector 304. Integrator 106A includes amplifier 320A, which has two inputs coupled to the outputs of adder 103. Amplifier 320A has two outputs coupled to resistors 324C and 324D, respectively. Integrator 106A has two capacitors 322A and 322B, each coupled between the input and output of amplifier 320A. INTG1_OUTP signal is generated across capacitor 322A, and INTG1_OUTM signal is generated across capacitor 322B. Resistor 324A is coupled across capacitor 322A, and resistor 324B is coupled across capacitor 322B.

[0035] Integrator 106B has two inputs coupled to resistors 324C and 324D, respectively. Integrator 106B has two outputs coupled to resistors 324E and 324F. Integrator 106B includes amplifier 320B, which has two inputs coupled to resistors 324C and 324D, respectively. Amplifier 320B has two outputs coupled to resistors 324E and 324F, respectively. Integrator 106B has two capacitors 322C and 322D, each coupled between the input and output of amplifier 320B. An INTG2_OUTP signal is generated across capacitor 322C, and an INTG2_OUTM signal is generated across capacitor 322D.

[0036] Integrator 106C has two inputs coupled to resistors 324E and 324F, respectively. Integrator 106C has two outputs coupled to resistors 324G and 324H. Integrator 106C includes amplifier 320C, which has two inputs coupled to resistors 324E and 324F. Amplifier 320C has two outputs coupled to resistors 324G and 324H, respectively. Integrator 106C has two capacitors 322E and 322F, each coupled between the input and output of amplifier 320C. The INTG3_OUTP signal is generated across capacitor 322E, and the INTG3_OUTM signal is generated across capacitor 322F.

[0037] Integrator 106D has two inputs coupled to resistors 324G and 324H, respectively. Integrator 106D has two outputs coupled to resistors 324I and 324J. Integrator 106D includes amplifier 320D, which has two inputs coupled to resistors 324G and 324H. Amplifier 320D has two outputs coupled to resistors 324I and 324J, respectively. Integrator 106D has two capacitors 322G and 322H, each coupled between the input and output of amplifier 320D. The INTG4_OUTP signal is generated across capacitor 322G, and the INTG4_OUTM signal is generated across capacitor 322H.

[0038] Summer 302 has two inputs coupled to resistors 324I and 324J, respectively. A first input of summer 302 receives three signals INTG1_OUTP, INTG2_OUTP, and INTG3_OUTP from resistors 324M, 324N, and 324O, respectively. The first input of summer 302 also receives the INTG4_OUTP signal from integrator 106D. A second input of summer 302 receives three signals INTG1_OUTM, INTG2_OUTM, and INTG3_OUTM from resistors 324P, 324Q, and 324R, respectively. The second input of summer 302 also receives the INTG4_OUTM signal from integrator 106D. Summer 302 has two outputs coupled to the inputs of comparator 110. Resistor 324K is coupled from a first output of summer 302 to a first input of summer 302. Resistor 324L is coupled from the second output of summer 302 to the second input of summer 302. Comparator 110 receives the ramp signal from ramp generator 108 and provides an output signal to switch 112. As described above, switch 112 switches between mute loop 128 and main loop 132. Switch 112 has an output coupled to mute level shifters 130A, 130B and power stage 116.

[0039] In the switch control 114, the integral error detector 304 has two inputs coupled to the two outputs of the integrator 106A. The integral error detector 304 has an output coupled to a comparator 306. The comparator 306 is a dual comparator including two internal comparators 308A and 308B. The output of the integral error detector 304 is coupled to a first input of the comparator 308A and a second input of the comparator 308B. The second input of the comparator 308A and the first input of the comparator 308B are coupled to a reference voltage V from any suitable voltage source. REF 314.

[0040] The outputs of comparators 308A and 308B are coupled to the input of an AND gate 310. AND gate 310 has an output coupled to the CLK input of a latch 312. Latch 312 has a D input that receives an EN_MUTE signal 316. Latch 312 provides an output signal EN_MUTE_FINAL signal 318 at the latch output.

[0041] In an example, the integral error detector 304 monitors or detects an integral error signal across the integrator 106A. In other examples, the integral error signal may be monitored at another location in the circuit system 300, such as across one or more other integrator outputs. The integral error detector 304 may include any hardware, logic, or circuit system to determine the integral error. The integral error may be determined by subtracting a value INTG_OUTM from INTG_OUTP, which is the output signal of the integrator 106A. The integral error detector 304 generates an integral error value and provides this value to the input of the comparator 306. Examples of integral error values ​​are shown as described below. Figure 4 Waveform 402 in FIG.

[0042] Comparator 306 compares the integrated error value provided by integrated error detector 304 to a threshold value. Since integrator 106 integrates a differential input signal that may be positive or negative, comparator 306 determines whether the integrated error is within a certain range, such as greater than -2 mV but less than +2 mV. An integrated error that is too low (e.g., below -2 mV) or too high (e.g., above +2 mV) may result in a crackling noise when entering or exiting the mute loop 128. The range (determined by the threshold value) may be set by the user to any suitable value. The threshold value is determined by V REF 314 provides. In this example, V REF 314 may be 2mV, which sets the range from -2mV to +2mV.

[0043] The integrated error is provided to the negative input of comparator 308A. REF314 is provided to the positive input of comparator 308A. The integrated error is provided to the positive input of comparator 308B. V REF 314 is provided to the negative input of comparator 308B. Thus, comparator 308A determines whether the integral error is less than +2mV. If so, comparator 308A provides a 1 at its output. Comparator 308B determines whether the integral error is greater than -2mV. If so, comparator 308B provides a 1 at its output. If both comparator 308A and comparator 308B provide a 1 output, then the integral error is between -2mV and +2mV, and the amplifier can exit the mute loop. If either comparator 308A or comparator 308B provides a 0 output, then the integral error is too high (in the positive or negative direction), and the amplifier remains in the mute loop until the integral error drops below the threshold.

[0044] The outputs of comparators 308A and 308B are coupled to the inputs of AND gate 310. AND gate 310 determines whether both comparators produce a 1 output. If so, AND gate 310 produces a 1 output. If not, AND gate 310 produces a 0 output. If AND gate 310 produces a 1 output, the amplifier can only exit the mute loop 128. If the integrated error is below the threshold, AND gate 310 provides a 1 output to the clock input of latch 312. If latch 312 receives a positive EN_MUTE signal 316 at the D input when the AND output is 1, latch 312 generates an EN_MUTE_FINAL signal 318 at the latch output. EN_MUTE_FINAL signal 318 indicates to switch 112 that the loop can be switched from the mute loop to the main loop, or vice versa. The EN_MUTE_FINAL signal 318 is provided only when the AND gate output is 1 (e.g., the integrated error is below a threshold), and the EN_MUTE signal 316 from the digital controller indicates that the system is ready to switch loops (e.g., during power-up or power-down). Figure 4 318. The interaction of these signals is described below. If the EN_MUTE signal 316 is received but the integrated error is above the threshold, then the latch 312 does not generate the EN_MUTE_FINAL signal 318. If the integrated error is below the threshold but the EN_MUTE signal 316 has not been received by the latch 312, then the latch 312 does not generate the EN_MUTE_FINAL signal 318. If both input conditions of the latch 312 are met, then the amplifier can switch from one loop to the other.

[0045] Switch control 114 provides one example of digital logic for detecting integration error and determining whether and when to switch loops. Other examples may use different digital logic but perform the functions described herein.

[0046] Figure 4 For illustration purposes Figure 1 and 3 Graph 400 of waveforms illustrating how a circuit arrangement of FIG. 404 can reduce click and pop noise. Graph 400 includes waveforms 402, 404, 406, and 408. Point 410 is also shown in graph 400.

[0047] Waveform 402 is an example representation of an integrated error value across integrator 106, such as determined by integrated error detector 304. For waveform 402, the x-axis is time in microseconds and the y-axis is voltage in mV. Waveform 404 represents an error comparator output signal (e.g., the output signal of AND gate 310). For waveform 404, the x-axis is time in microseconds and the y-axis is voltage in volts (V). Waveform 406 is an EN_MUTE signal 316 that may be provided by a digital controller in one example. For waveform 406, the x-axis is time in microseconds and the y-axis is voltage in volts (V). Waveform 408 is an EN_MUTE_FINAL signal 318 generated by the output of latch 312. For waveform 408, the x-axis is time in microseconds and the y-axis is voltage in volts (V).

[0048] Graph 400 shows an integrated error in a monitoring amplifier and when the integrated error is below a threshold (e.g., as determined by V REF 314). Waveform 402 shows the value of the integrated error provided by the integrated error detector 304. As an example, the threshold value may be positive or negative 2mV. If the integrated error is greater than -2mV and less than 2mV, the mute loop 128 may be exited. If the integrated error is below -2mV, the amplifier remains in the mute loop 128. If the integrated error is above 2mV, the amplifier remains in the mute loop 128. The integrated error detector 304 continuously monitors the integrated error. If the integrated error is greater than -2mV and less than 2mV in this example, the error comparator output goes high (e.g., waveform 404). As shown in the graph 400, the waveform 404 switches between high and low values ​​depending on the value of the integrated error in the waveform 402.

[0049] Graph 400 shows that the amplifier exits the mute loop only when the error comparator output is high (waveform 404) and the EN_MUTE signal 316 is high (waveform 406). In this example, waveform 406 is low until time t1. At time t1, waveform 406 goes high. This signal indicates that the digital controller, processor, or other component has instructed to switch from the mute loop 128 to the main loop 132. For example, the EN_MUTE signal 316 may go high after the power-on process is complete.

[0050] After the EN_MUTE signal 316 (waveform 406) goes high, the amplifier may exit the mute loop 128. However, as described herein, the amplifier does not exit the mute loop 128 until the integrated error is below a threshold. By waiting until the integrated error is below a threshold, click and pop noise is reduced. Here, at time t1, the integrated error is still above the threshold, as indicated by waveform 404 being low at time t1. At time t2 (point 410 on waveform 402), the value of the integrated error (waveform 402) has dropped below the threshold. Therefore, at time t2, waveform 404 goes high. Since both waveforms 404 and 406 are high at time t2, the amplifier may exit the mute loop 128 at time t2. The latch 312 generates the EN_MUTE_FINAL signal 318 at time t2, which is indicated by waveform 408 going high. As Figure 3 , the EN_MUTE_FINAL signal 318 is provided to the switch 112 , and the switch 112 switches from the mute loop 128 to the main loop 132 in response to the EN_MUTE_FINAL signal 318 .

[0051] Figure 5 An example graph 500 of A-weighted crackle values. Figure 5 Two waveforms are shown, 502 and 504. In graph 500, the x-axis is the iteration number, and the y-axis is the A-weighted crackle value in mV.

[0052] In graph 500, waveform 502 shows the snap value for a system that does not monitor the integrated error before entering or exiting the mute loop 128. Instead, this system exits or enters the mute loop after a set amount of time has passed. Fifteen iterations are shown on the x-axis. In those iterations, the snap value varies in magnitude and can be as high as 2.5e-3 mV in some instances.

[0053] Waveform 504 shows the crackle value of a system with an integral error detector 304 as described herein. In waveform 504, the integral error in the amplifier is monitored, and the mute loop 128 is entered or exited only if the error is below a threshold. Thus, the crackle value can be low and deterministic. Waveform 504 shows that for the fifteen iterations, the crackle values ​​are each below 2.0e-4. Thus, in the example herein, the crackle noise is significantly reduced.

[0054] Figure 6 6 is a flow chart of an example method 600 for switching between a mute loop and a main loop in an amplifier. The steps of method 600 may be performed in any suitable order. In some examples, the above with respect to Figure 1 and 3The depicted hardware components may perform method 600. In some examples, any suitable hardware, software, or digital logic may perform method 600.

[0055] The method 600 begins at 610, where an amplifier enters a mute loop, such as the mute loop 128. In one example, the amplifier may be a class D amplifier. The amplifier may enter the mute loop 128 for power-on or power-off operation. In other examples, the amplifier may enter the mute loop 128 to noise gate the amplifier. In an audio device, if the device is not producing any audio (e.g., during a silent portion of an audio track), the amplifier may be noise gated to temporarily shut down and save power.

[0056] The method 600 continues at 620 where the integrated error detector 304 monitors the error in the amplifier. As described above, in one example, the error may be monitored across the integrator 106 in the loop filter 104. Any suitable method, hardware, logic, or circuitry may be used to monitor the integrated error.

[0057] The method 600 continues at 630, where the amplifier receives a signal to exit the mute loop 128. In one example, the signal may come from a controller or processor. In one example, the amplifier may receive the signal to exit the mute loop 128 to begin powered-on operation. In another example, the amplifier may receive the signal to exit the mute loop 128 because noise gating is no longer needed.

[0058] The method 600 continues at 640 where the circuit system (e.g., the switch control 114) determines that the integrated error is below a threshold. The amplifier remains in the mute loop 128 until the integrated error is below the threshold to reduce the crackle noise. The threshold may be set by the user to meet certain performance metrics or specifications related to the crackle noise. Any suitable logic, hardware, or circuit system may be used to determine whether the integrated error is below a threshold.

[0059] The method 600 continues at 650, where in response to determining that the integrated error is below the threshold, the amplifier exits the mute loop 128. If the integrated error is above the threshold, the integrated error detector 304 continues to monitor the integrated error until it is safe to exit the mute loop 128. After the integrated error drops below the threshold, a signal may be sent from the switch control 114 to the switch 112 to switch from the mute loop 128 to the main loop 132. The amplifier then exits the mute loop 128 and operates using the main loop 132.

[0060] In some instances, there is additional power-up or power-down time because the loop must stabilize before entering or exiting the mute loop. However, for example, with a 1mV V REFThe time is less for a 384 kilohertz (kHz) Class D amplifier of the signal. In one example, the additional power-on or power-off time may increase by 10%, but the crackle reduction may be 10 times or more compared to other systems. The additional time for power-on or power-off may be reduced by switching to a higher ramp frequency from the ramp generator 108 during power-on or power-off. Increasing the ramp frequency allows the loop to stabilize faster, which in some examples may reduce the additional overhead time to a value less than 10%.

[0061] In the examples herein, if the system switches from the main feedback loop to the mute loop, the state of the signal in the loop filter is monitored, or vice versa. The mute loop may be useful during the disconnected state of the amplifier (e.g., noise gating), while the main loop is useful during the on state of the amplifier (e.g., normal operation). The system switches from one loop to another only when the value of the integrated error signal in the loop filter is below a threshold. If the error signal is below the threshold, the click or crackle noise that occurs during loop switching is reduced compared to other systems. The integrated error signal may be monitored and detected with any suitable hardware, logic, or circuit system. The examples described herein are also area and power efficient because existing hardware can be used to sense the error signal with the addition of a small amount of digital logic. The examples herein provide deterministic and finite weighted crackle values.

[0062] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0063] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function at the time of manufacture by the manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0064] Circuits or devices described herein as including certain components may alternatively be coupled to those components to form the described circuit systems or devices. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0065] The circuits described herein can be reconfigured to include replaced components to provide functionality that is at least partially similar to functionality available before component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the displayed resistor. For example, a resistor or capacitor shown and described as a single component herein may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described as a single component herein may alternatively be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0066] The use of the phrase "ground" in the foregoing description includes chassis ground, ground line ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "approximately" or "substantially" before a parameter means within + / -10% of the parameter. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

[0067] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnect between device elements, circuit elements, integrated circuits, devices, or semiconductor components, or the ends thereof. In addition, a voltage rail, or more simply a "rail," may also be referred to as a voltage terminal, and may generally mean a common node or set of coupled nodes in a circuit that are at the same potential.

Claims

1. A system comprising: a loop filter comprising one or more integrators, the loop filter having an input and an output; a ramp generator having an output; a comparator having a first input coupled to the output of the loop filter and a second input coupled to the output of the ramp generator, and having an output; a mute loop coupled to the input of the loop filter and the output of the comparator; a power stage having an input coupled to the output of the comparator and having an output; a main loop coupled to the output of the power stage and the input of the loop filter; an integrated error detector having an input coupled to the loop filter and having an output; and A dual comparator has an input coupled to the output of the integrated error detector and has an output.

2. The system of claim 1, wherein the system comprises a Class D amplifier.

3. The system of claim 1, further comprising a differential input coupled to the input of the loop filter. The system of claim 1 , wherein the power stage comprises an H-bridge.

5. The system of claim 1, further comprising: An output filter has an input coupled to the output of the power stage and has an output.

6. The system of claim 1, further comprising: A switch is coupled to the mute loop.

7. The system of claim 6, wherein the switch is further coupled to the comparator and the power stage.

8. A system comprising: An amplifier comprising: a loop filter comprising one or more integrators, the loop filter having an input and an output; a ramp generator having an output; a comparator having a first input coupled to the output of the loop filter and a second input coupled to the output of the ramp generator, and having an output; a power stage having an input coupled to the output of the comparator and having an output; a mute loop coupled to the input of the loop filter and the output of the comparator; a main loop coupled to the output of the power stage and the input of the loop filter; an integrated error detector having an input coupled to the loop filter and having an output; a dual comparator having an input coupled to the output of the integrated error detector; an AND gate having an input coupled to the dual comparator and having an output; and A latch has an input coupled to the output of the AND gate and has an output.

9. The system of claim 8, wherein the amplifier is a class D amplifier.

10. The system of claim 8, wherein the power stage comprises an H-bridge.

11. The system of claim 8, wherein the output of the latch is coupled to a switch.

12. The system of claim 11, wherein the switch is coupled to the mute loop and the main loop.

13. The system of claim 12, wherein the switch is further coupled to the comparator and the power stage.

14. A system comprising: a loop filter comprising one or more integrators, the loop filter having an input and an output; a ramp generator having an output, the ramp generator being configured to provide a ramp signal; a comparator having a first input coupled to the output of the loop filter and a second input coupled to the output of the ramp generator and having an output, the comparator being configured to receive the ramp signal from the ramp generator; a power stage having an input coupled to the output of the comparator and having an output; a mute loop coupled to the input of the loop filter and the output of the comparator, the mute loop configured to provide feedback in a first state of the amplifier; a main loop coupled to the output of the power stage and the input of the loop filter, the main loop configured to provide feedback in a second state of the amplifier; an integral error detector having an input coupled to the loop filter and having an output, the integral error detector configured to detect a voltage error in the loop filter; and A dual comparator having an input coupled to the output of the integrated error detector and having an output, the dual comparator configured to compare the voltage error to a reference voltage.

15. The system of claim 14, wherein the ramp generator is configured to switch to a higher ramp frequency in the first state of the amplifier.

16. The system of claim 14, further comprising: an AND gate having an input coupled to the output of the dual comparator and having an output; and A latch has an input coupled to the output of the AND gate.

17. The system of claim 16, wherein the latch is configured to provide a signal to switch between the mute loop and the main loop.

18. The system of claim 14, wherein the first state is an off-state of the amplifier and the second state is an on-state of the amplifier.

19. The system of claim 14, wherein the dual comparator is configured to indicate that the voltage error is below the reference voltage.

20. The system of claim 14, wherein the integrated error detector detects the voltage error across an integrator in the loop filter.

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