High-end ideal diode based on differential amplifier

Abstract

The invention discloses a high-end ideal diode based on a differential amplifier. A circuit comprises a PMOS main tube, a differential amplification circuit, a voltage comparator and a bias power supply. The two input ports of the differential amplification circuit are respectively connected with the drain electrode and the source electrode of the PMOS main tube and used for comparing the voltage, and the two output ports of the differential amplification circuit are connected to the two input ports of the voltage comparator for amplification; and the output signal of the voltage comparator is connected with and controls the conduction and cut-off of the PMOS main tube. Compared with the prior art, the circuit has the advantages that a backward flowing prevention function is provided, and a pre-stage circuit can be protected; the loss is low, and the quiescent current loss is small; the invention discloses a high-end ideal diode based on a differential amplifier.

Description

Technical Field

[0001] The invention relates to the technical field of power diodes, and in particular to a high-end ideal diode based on a differential amplifier. Background Art

[0002] Diodes are used more and more due to their unidirectional conduction characteristics and backflow prevention functions. In particular, Schottky diodes have a smaller voltage drop and are becoming more and more popular with designers. Since the voltage drop of Schottky diodes is still greater than the conduction voltage drop of MOS tubes, for some voltage-sensitive circuits, MOS tubes with low impedance characteristics are more preferred to improve product reliability.

[0003] At present, the Oring circuit is used in many occasions. Its function is to ensure that each single power supply is independent of each other and there is no backflow. It is most commonly used in current equalization circuits to meet different power requirements.

[0004] Therefore, a low-loss high-end ideal diode and an ultra-low-loss ideal diode are needed to further reduce the voltage drop and have the functions of preventing backflow and protecting the previous stage, so as to minimize the loss and extend the battery working time. Summary of the invention

[0005] The technical problem to be solved by the present invention is to overcome the deficiencies in the prior art and provide a high-end ideal diode based on a differential amplifier.

[0006] In order to solve the above technical problems, the technical solution provided by the present invention is: a high-end ideal diode based on a differential amplifier, the circuit comprising a PMOS tube, a differential amplifier circuit, a voltage comparator, and a bias power supply;

[0007] The dual input ports of the differential amplifier circuit are respectively connected to the drain and source of the PMOS tube to compare the voltages, and the dual output ports of the differential amplifier circuit are connected to the dual input ports of the voltage comparator for amplification;

[0008] The voltage comparator output signal is connected to the gate of the PMOS supervisor to control the on and off of the PMOS supervisor.

[0009] Preferably, the differential amplifier circuit comprises a transistor pair V2, V3 and resistors R1 to R5, wherein resistors R2 = R3, R4 = R5;

[0010] The two common ends of the transistor pair V2 and V3 are grounded via a resistor R1, and the input ends of the transistor pair V2 and V3 are connected to the drain and source of the PMOS main tube V1 through resistors R4 and R5 respectively as dual input ports of the differential amplifier;

[0011] Resistors R2 and R3 are connected between the two output ends of the transistor pair V2 and V3 and the bias power supply. The potential difference between the two output ends of the transistor pair V2 and V3 is connected to the inverting end and the non-inverting end of the voltage comparator as a dual output port. The output signal of the voltage comparator is connected to the gate of the PMOS main tube V1 to control the gate of the PMOS main tube V1.

[0012] Preferably, the transistor pair is an NPN pair of transistors V2 and V3, the base of the NPN pair of transistors V2 and V3 is the input terminal, the collector is the output terminal, and the emitter is the common terminal.

[0013] Preferably, the transistor pair is an NMOS pair of transistors V2 and V3, the gate of the NMOS pair of transistors V2 and V3 is the input terminal, the drain is the output terminal, and the source is the common terminal.

[0014] Preferably, the differential amplifier comprises a transistor pair V2, V3, and resistors R1 to R5, wherein resistors R2 = R3, R4 = R5;

[0015] The two input ends of the transistor pair V2 and V3 are used as dual input ports, connected to the drain and source of the PMOS main tube V1 through resistors R4 and R5, and their voltages are detected respectively. The two common ends of the transistor pair V2 and V3 are connected to the bias power supply through resistor R1;

[0016] The two output ends of the transistor pair V2 and V3 are grounded through resistors R2 and R3 respectively, and serve as dual output ports to output differential signals connected to the inverting end and the non-inverting end of the voltage comparator U1 respectively. The output signal of the voltage comparator controls the gate of the PMOS main tube V1.

[0017] Preferably, the transistor pair is a PNP pair of transistors V2 and V3, the base of the PNP pair of transistors V2 and V3 is the input terminal, the collector is the output terminal, and the emitter is the common terminal.

[0018] Preferably, the transistor pair is a PMOS transistor pair, the gate of the PMOS transistor pair V2 and V3 is the input terminal, the drain is the output terminal, and the source is the common terminal.

[0019] Compared with the prior art, the present invention has the advantages of combining the differential amplifier circuit (dual input ports, dual output ports) and the hysteresis voltage comparator characteristics, taking advantage of each other to achieve complementary advantages, thereby providing a high-end ideal diode that meets the use of a wide current range;

[0020] Under the same conditions, the on-resistance of the PMOS tube is larger than that of the NMOS tube, and it is suitable for occasions with smaller working current. Due to the dual amplification of the differential amplifier and the voltage comparator, it is suitable for working occasions with a wide current range;

[0021] The circuit has the function of preventing backflow and can protect the previous circuit; it has low loss and small static current loss; the circuit is simple, the cost is very low and the practicability is strong. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of a PMOS type (main tube) high-side ideal diode implemented for an NPN pair differential amplifier;

[0023] Figure 2 Schematic diagram of a PMOS type (main tube) high-side ideal diode implemented for an NMOS pair differential amplifier;

[0024] Figure 3 Schematic diagram of a PMOS type (main tube) high-side ideal diode implemented for a PNP pair differential amplifier;

[0025] Figure 4 Schematic diagram of a PMOS type (main tube) high-side ideal diode implemented for a PMOS pair differential amplifier;

[0026] Figure 5 yes Figure 1 Forward conduction simulation;

[0027] Figure 6 yes Figure 1 Reverse cutoff simulation;

[0028] Figure 7 yes Figure 2 Forward conduction simulation;

[0029] Figure 8 yes Figure 2 Reverse cutoff simulation;

[0030] Fig. 9 yes Figure 3 Forward conduction simulation;

[0031] Fig.10 yes Figure 3 Reverse cutoff simulation;

[0032] Fig.11 yes Figure 4 Forward conduction simulation;

[0033] Fig.12 yes Figure 4 Reverse cutoff simulation. DETAILED DESCRIPTION

[0034] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0035] The high-end ideal diode device is composed of a PMOS tube, a differential amplifier circuit, a voltage comparator, a bias power supply, etc. The tube type in the differential amplifier circuit can be one of NPN, NMOS, PNP, and PMOS. The dual input ports of the differential amplifier circuit are respectively connected to the drain and source of the PMOS tube and the voltage is compared. The signal of the dual output port of the differential amplifier circuit is loaded to the dual input port of the voltage comparator for amplification. The output signal of the voltage comparator controls the conduction and cutoff of the PMOS tube. When the input voltage VCC is not less than the output voltage Vout, the voltage comparator outputs a low level to control the drain-source channel of the PMOS tube V1 to be turned on; conversely, when the input voltage VCC is less than or equal to the output voltage Vout, the voltage comparator outputs a high level to control the drain-source channel of the PMOS tube V1 to be cut off, preventing the Vout current from flowing back to VCC and protecting the VCC power supply front-stage circuit.

[0036] The voltage comparator has a hysteresis loop transmission characteristic (also known as a Schmitt trigger). The threshold voltage of this voltage comparator changes with the output voltage at an accelerated rate, and the anti-interference ability is improved. The hysteresis voltage comparator has a hysteresis characteristic, that is, inertia, and thus has a certain anti-interference ability. The stronger the anti-interference ability, the worse the sensitivity. The PMOS supervisor can use PMOS tubes with different conduction current sizes. For high-power power supply control, the PMOS supervisor can choose the drain channel conduction impedance R DS(ON) It is a power tube device with a current of tens of milliohms and a large passing current. It has a small voltage drop when passing a large current, that is, it has a very low forward voltage and can be approximated as an ideal diode.

[0037] Implementation Method 1

[0038] A high-side ideal diode based differential amplifier, the circuit is as follows Figure 1 As shown, it includes a PMOS main tube V1, a differential amplifier, a voltage comparator U1, a bias power supply VBIAS, etc. The differential amplifier is composed of NPN pair tubes V2 and V3, resistors R1 to R5, etc., and is a common emitter circuit, wherein R2 = R3, R4 = R5. The two bases of the NPN pair tubes V2 and V3 are used as dual input ports of the differential amplifier to detect the drain and source voltages of the PMOS main tube V1 respectively. After the amplification of the pair tubes V2 and V3 of the differential amplifier, the two collector potential differences of the V2 tube and the V3 tube are used as dual output ports to output differential signals U+ and U- respectively. U- and U+ are connected to the inverting terminal and the non-inverting terminal of the voltage comparator U1 respectively. The voltage comparator U1 outputs a signal V1G to control the conduction and cutoff of the PMOS main tube V1.

[0039] The differential amplifier can overcome the problem of temperature drift. Under the action of differential mode signal, the current change of R1 is 0, that is, the resistor R1 has no feedback effect on the differential mode signal, which is equivalent to a short circuit. Therefore, the amplification ability of the differential mode signal is greatly improved, while simplifying the circuit and making the power supply and signal source "shared ground". The differential amplifier is also called a differential amplifier. The so-called "differential" means that the output voltage will change (change amount) only when there is a difference (change amount) in the potential between the dual input ports.

[0040] Differential amplifiers generally require ideal parameter symmetry, R2 = R3, R4 = R5, and the input characteristic curves and output characteristic curves of the NPN pair of tubes V2 and V3 completely overlap. Due to the dispersion of transistor characteristics, the parameters of any component cannot be ideally symmetrical, that is, the zero drift cannot be completely suppressed. However, in integrated circuits, since adjacent components have good symmetry and the parameters are basically equal, the ideal parameter symmetry can generally be achieved approximately. Therefore, the NPN pair of tubes V2 and V3 are preferably packaged together with NPN auxiliary tube chips to ensure that the parameters of the two tubes are basically equal.

[0041] The specific working principle is as follows.

[0042] When the DC power supply VCC=VCC1 is powered on (forward conduction), VBIAS>VCC1, and the current output by VCC first passes through the body diode of the PMOS V1 (Vout=VCC-V F , V F is the body diode conduction voltage drop), when the output current gradually increases, the internal power supply VCC is higher than the external voltage Vout (VCC>Vout), the voltage VA>VC, and the NPN tube V2 is more completely turned on than the NPN tube V3 (the conduction impedance of the V2 tube is R2 CE R3 is the on-resistance of V3 tube CE The conduction degree depends on the base voltage), which means that the voltage U+ is less than U-. The differential signals U- and U+ output by the differential amplifier are transmitted to the voltage comparator U1, and the voltage comparator U1 outputs a low level, that is, V1G≈0V, V1 GS =V1G-Vout≈V F -VCC<V TP (V TP The drain-source channel of the PMOS tube V1 is turned on, and the VCC current flows through the drain-source low-impedance channel of the PMOS tube V1 to the load RL (no longer through the body diode high-impedance channel of the PMOS tube V1). The drain-source channel of the PMOS tube V1 is turned on with a small impedance, that is, the conduction loss is less than the diode V F , reduce power loss and improve power utilization efficiency.

[0043] When the external voltage Vout = VCC2 is greater than the internal power supply VCC (Vout>VCC), VBIAS>VCC2-V TP , voltage VC>VA, NPN tube V3 conducts more thoroughly than NPN tube V2 (the conduction impedance of V3 tube R3 CE R2 is the on-resistance of V2 tube CE The conduction degree depends on the base voltage), that is, the voltage U-<U+, the differential signal U-, U+ output by the differential amplifier is transmitted to the voltage comparator U1, and the voltage comparator U1 outputs a high level, that is, V1G≈VBIAS, V1 GS =V1G-Vout≈VBIAS-VCC2>0V>V TP , the drain-source channel of the PMOS V1 is cut off, the power supply VCC is isolated from the external voltage Vout, and the current of the external power supply (other power supplies connected in parallel with the voltage Vout) cannot flow back into the power supply VCC1, thereby achieving the purpose of protecting the power supply VCC1.

[0044] Furthermore, the voltage comparator has a voltage comparator with a hysteresis loop transmission characteristic (also known as a Schmitt trigger). The threshold voltage of this voltage comparator changes with the change of the output voltage, and the anti-interference ability is improved. The hysteresis voltage comparator has a hysteresis characteristic, that is, inertia, and thus has a certain anti-interference ability. The stronger the anti-interference ability, the worse the sensitivity. The hysteresis voltage comparator circuit has two threshold voltages. The input voltage VCC causes the output voltage Vout to jump in the process of gradually increasing the threshold voltage VT1, and the input voltage VCC causes the output voltage Vout to jump in the process of gradually decreasing the threshold voltage VT2. VT1≠VT2, and the circuit has a hysteresis characteristic. The similarity with the single-limit voltage comparator is that when the input voltage changes in a single direction, the output voltage Vout only jumps once.

[0045] Furthermore, the PMOS tube V1 can use PMOS tubes with different conduction currents. For high-power power supply control, the PMOS tube can choose a drain channel conduction impedance R DS(ON) A power tube device with a current of several milliohms and a large flow rate. When a large current flows through it, the conduction voltage drop is small, that is, it has a very low forward voltage and can be approximated as an ideal diode.

[0046] Implementation Method 2

[0047] Circuit such as Figure 2 As shown, the circuit structure is basically the same as that of Implementation Method 1, except that: the differential amplifier circuit of Implementation Method 1 uses an NPN pair of tubes, and Implementation Method 2 uses an NMOS pair of tubes to replace the NPN pair of tubes V2 and V3, wherein R2=R3, R4=R5, and it belongs to a common source circuit. The specific working principle is basically the same as that of Implementation Method 1, and is described in detail in Implementation Method 1.

[0048] Implementation Method 3

[0049] A high-side ideal diode based differential amplifier, the circuit is as follows Figure 3 As shown, it includes a PMOS main tube V1, a differential amplifier, a voltage comparator U1, a bias power supply VBIAS, etc. The differential amplifier is composed of a PNP pair of tubes V2 and V3, resistors R1 to R5, etc., and belongs to a common emitter circuit, wherein R2 = R3, R4 = R5. The two bases of the PNP pair of tubes V2 and V3 are used as dual input ports to detect the drain and source voltages of the PMOS main tube V1 respectively. After the amplification of the PNP pair of tubes V2 and V3 of the differential amplifier, the two collectors of the V2 tube and the V3 tube are used as dual output ports to output differential signals U+ and U- respectively. U- and U+ are connected to the inverting terminal and the non-inverting terminal of the voltage comparator U1 respectively. The voltage comparator U1 outputs a signal V1G to control the conduction and cutoff of the PMOS main tube V1. The specific working principle is as follows.

[0050] When the DC power supply VCC=VCC1 is powered on (forward conduction), the current output by VCC first passes through the body diode of the PMOS V1 (Vout=VCC-V F , V F is the body diode conduction voltage drop), when the output current gradually increases, the internal power supply VCC is higher than the external voltage Vout (VCC>Vout), that is, the voltage VA>VC, the PNP tube V3 is more thoroughly turned on than the PNP tube V2 (the conduction impedance of the V3 tube is R3 CE R2 is the on-resistance of V2 tube CE The conduction degree depends on the difference between the bias power supply VBIAS and the base voltage), which means that the voltage U->U+, the differential signal U-, U+ output by the differential amplifier is transmitted to the voltage comparator U1, and the voltage comparator U1 outputs a low level, that is, V1G≈0V, V1 GS =V1G-Vout≈V F -VCC<V TP , the drain-source channel of the PMOS V1 is turned on, and the VCC current flows through the low-impedance drain-source channel of the PMOS V1 to the load RL (no longer through the high-impedance channel of the body diode of the PMOS V1). The on-resistance of the drain-source channel of the PMOS V1 is small, that is, the conduction loss is less than that of the diode V F , reduce power loss and improve power utilization efficiency.

[0051] When the external voltage Vout = VCC2 is greater than the internal power supply VCC (Vout>VCC), the voltage VC>VA, and the PNP tube V2 is more completely turned on than the PNP tube V3 (the on-resistance of the V2 tube is R2 CE R3 is the on-resistance of V3 tube CEThe conduction degree depends on the difference between the bias power supply VBIAS and the base voltage), that is, the voltage U+>U-. The differential signals U- and U+ output by the differential amplifier are transmitted to the voltage comparator U1. The voltage comparator U1 outputs a high level, that is, V1G≈VBIAS. When V1 GS =V1G-Vout≈VBIAS-VCC2>0V>V TP , the drain-source channel of the PMOS V1 is cut off, the power supply VCC is isolated from the external voltage Vout, and the current of the external power supply (other power supplies connected in parallel with the voltage Vout) cannot flow back into the power supply VCC1, thereby achieving the purpose of protecting the power supply VCC1.

[0052] Implementation Method 4

[0053] Circuit such as Figure 4 As shown, the circuit structure is basically the same as that of the third embodiment, except that the third embodiment uses a PNP pair of transistors for the differential amplifier circuit, while the fourth embodiment uses a PMOS pair of transistors to replace the PNP pair of transistors V2 and V3, which is a common source circuit, wherein R2 = R3, R4 = R5. The specific working principle is basically the same as that of the third embodiment, see the third embodiment for details, and will not be repeated here.

[0054] according to Figure 1 to Figure 4 The circuit schematic is simulated and tested using the National Instruments simulation software Multisim (version V14.0). The voltage comparator is LMC7211AIM5, a rail-to-rail op amp, and the output stage uses push-pull amplification to achieve an approximate full swing. The PMOS tube is NVTFS5124PLTAG from ON Semiconductor, with a minimum on-threshold voltage V TP(MIN) =-1.5V, maximum value V TP(MAX) =-2.5V, typical value V not given TP , the on-state current can reach -6A, and the on-state impedance R DS(ON) =0.26Ω(V GS =-10V), R DS(ON) =0.38Ω(V GS =-4.5V). The NMOS tube is made by NXP, model 2N7002E, and the minimum on-state voltage is V TN(MIN) =1V, maximum value V TN(MAX) =2.8V, typical value V is not given TN , conduction current I D 10A / 30V, on-resistance R DS(ON) ≤0.03Ω(V GS =10V), R DS(ON) ≤0.05Ω(V GS=4.5V); the NPN tube is from Generic Company, model 2N2222A; the PNP tube is from Generic Company, model 2N2905; the load resistance RL=10Ω, the specific simulation test is as follows.

[0055] Implementation Method 1 Simulation

[0056] DC power supply forward conduction simulation test: Set R1 = R2 = R3 = 10kΩ, R4 = R5 = 100kΩ, VBIAS = 30V, VCC = VCC1 = 12V (switch J1 is closed), such as Figure 5 As shown, when forward-conducting, the output voltage of the PMOS main tube V1 is Vout = 11.7V; the base current of the NPN auxiliary tube V2 is 4.25μA (test point PR6), and the base voltage VA = 11.6V (test point PR2), so it can be considered that the NPN auxiliary tube V2 is turned on; the base current of the NPN auxiliary tube V3 is 1.56μA (test point PR8), and the base voltage VC = 11.5V (test point PR1), so it can be considered that the NPN auxiliary tube V3 is turned on, and the NPN tube V2 is more thoroughly turned on than the NPN tube V3; U+ = 22.1V (test point PR9), U- = 27.0V (test point PR10), that is, U->U+, the voltage comparator U1 outputs a low level, that is, V1G = 6.76mV (test point PR4), V1 GS =V1G-Vout≈0V-11.7V=-11.7V<V TP , the drain-source channel of the PMOS V1 is turned on, and the on-state voltage drop is about 302.613mV (measured by a multimeter), which is lower than the on-state voltage drop of the diode V F =0.6V, the positive output current of the power supply is 1.17A, and the corresponding on-resistance is 302.613mV / 1.17A=258.6mΩ.

[0057] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed, that is, Vout = VCC2 = 25V, Vout > VCC, voltage VC = 16.1V, VA = 12.0V, U- = 15.5V, U+ = 30V, that is, voltage U+ > U-, NPN tube V3 (on state) is more thoroughly turned on than NPN tube V2 (off state), and voltage comparator U1 outputs a high level, that is, V1G ≈ 30.0V, V1 GS =V1G-Vout≈30.0V-25V=5V>V TP , the drain-source channel of PMOS V1 is cut off, such as Figure 6 As shown, the backflow current (node ​​VCC current: 533nA-14pA≈533nA) output by VCC2 to the power supply VCC1 can be ignored. It can be considered that VCC1 is isolated from the external voltage Vout, thereby achieving the purpose of protecting the power supply VCC1.

[0058] For different current usage scenarios, the resistance value of the load resistor RL is changed, and the simulation test results are shown in Table 1.

[0059] Table 1 Load current simulation test

[0060]

[0061] According to the load current simulation test in Table 1, it can be seen that R1=R2=R3=R4=R5=10kΩ, and this set of parameters has a better magnification: load RL=12kΩ, load current is 1mA, and the conduction voltage drop V1 of NMOS V1 DS =259.255μV (corresponding on-resistance R DS(ON) =259.255mΩ), which is in line with the data sheet parameters. After the differential amplifier amplifies the output, the difference between U+ and U- is 21.729mV. The differential amplifier amplification factor is Au = 21.729mV / 259.255μV = 83.81. The other two sets of parameters are amplified by less than 20 times. The typical offset voltage of the voltage comparator chip LMC7211AIM5 is VIO = 3mV. If there is no differential amplifier, the drain-source conduction current I of the NMOS V1 that allows the LMC7211AIM5 to work properly is D =VIO / R DS(ON) =3mV / 259.255mΩ=0.0115A=11.5mA; if a differential amplifier is used, the corresponding on-state current I D =0.0115A / 83.81=0.137mA. Theoretically, the on-current is greater than 0.137mA, which can reach the offset voltage of LMC7211AIM5. The combination circuit of differential amplifier and voltage comparator can be used in working occasions with a wide current range, expanding the application range.

[0062] Implementation Method 2 Simulation

[0063] DC power supply forward conduction simulation test: Set R1 = R2 = R3 = 10kΩ, R4 = R5 = 100kΩ, VBIAS = 30V, VCC = VCC1 = 12V (switch J1 is closed), such as Figure 7 As shown, when the PMOS is forward conducting, the output voltage Vout of the PMOS V1 is 11.7V; the voltage VA is 12.0, VC is 11.7V, U+ is 21V, U- is 29.2V, that is, U->U+, the voltage comparator U1 outputs a low level, that is, V1G is 6.76mV (test point PR4), V1 GS =V1G-Vout≈0V-11.7V=-11.7V<V TP, the drain-source channel of the PMOS V1 is turned on, and the on-state voltage drop is about 302.613mV (measured by a multimeter), which is lower than the on-state voltage drop of the diode V F =0.6V, the positive output current of the power supply is 1.17A, and the corresponding on-resistance is 302.613mV / 1.17A=258.6mΩ.

[0064] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed, that is, Vout = VCC2 = 25V, Vout > VCC, voltage VA = 12.0V, VC = 25V, U+ = 30V, U- = 15V, that is, U+ > U-, voltage comparator U1 outputs high level, that is, V1G = 30.0V (test point PR4), V1 GS =V1G-Vout≈30.0V-11.7V=18.3V>V TP , the drain-source channel of PMOS V1 is cut off, such as Figure 8 As shown, the backflow current (node ​​VCC current: 533nA-1.96nA=531nA) output by VCC2 to the power supply VCC1 can be ignored. It can be considered that VCC1 is isolated from the external voltage Vout, thereby achieving the purpose of protecting the power supply VCC1.

[0065] Implementation Method 3 Simulation

[0066] DC power supply forward conduction simulation test: Set R1 = R2 = R3 = 10kΩ, R4 = R5 = 100kΩ, VBIAS = 30V, VCC = VCC1 = 12V (switch J1 is closed), such as Fig. 9 As shown, when forward conducting, the output voltage of PMOS V1 is Vout = 11.7V; voltage VA = 12.7V (12.69V measured by multimeter), VC = 12.7V (12.678V measured by multimeter), U+ = 7.31V, U- = 9.20V, that is, U->U+, the voltage comparator U1 outputs a low level, that is, V1G = 6.76mV (test point PR4), V1 GS =V1G-Vout≈0V-11.7V=-11.7V<V TP , the drain-source channel of the PMOS V1 is turned on, and the on-state voltage drop is about 302.613mV (measured by a multimeter), which is lower than the on-state voltage drop of the diode V F =0.6V, the positive output current of the power supply is 1.17A, and the corresponding on-resistance is 302.613mV / 1.17A=258.6mΩ.

[0067] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed, that is, Vout = VCC2 = 25V, Vout > VCC, voltage VA = 14.4V, VC = 25V, U+ = 14.7V, U- = 5.97μV, that is, U+ > U-, voltage comparator U1 outputs high level, that is, V1G = 30V (test point PR4), V1 GS =V1G-Vout≈30V-11.7V=18.3V>V TP , the drain-source channel of PMOS V1 is cut off, such as Fig.10 As shown, the bias power supply VBIAS outputs a bias current of 23.9μA to the power supply VCC1, and VCC2 outputs a reverse current (node ​​VCC current: 24.3μA-23.9μA=0.4μA) to the power supply VCC1, which can be ignored. It can be considered that VCC1 is isolated from the external voltage Vout, thereby achieving the purpose of protecting the power supply VCC1.

[0068] Implementation Method 4 Simulation

[0069] DC power supply forward conduction simulation test: Set R1 = R2 = R3 = 10kΩ, R4 = R5 = 100kΩ, VBIAS = 30V, VCC = VCC1 = 12V (switch J1 is closed), such as Fig.11 As shown, when the PMOS is forward conducting, the output voltage Vout of the PMOS V1 is 11.7V; the voltage VA is 12.0V, VC is 11.7V, U+ is 3.99V, U- is 13V, that is, U->U+, the voltage comparator U1 outputs a low level, that is, V1G is 6.76mV (test point PR4), V1 GS =V1G-Vout≈0V-11.7V=-11.7V<V TP , the drain-source channel of the PMOS V1 is turned on, and the on-state voltage drop is about 302.613mV (measured by a multimeter), which is lower than the on-state voltage drop of the diode V F =0.6V, the positive output current of the power supply is 1.17A, and the corresponding on-resistance is 302.613mV / 1.17A=258.6mΩ.

[0070] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed, that is, Vout = VCC2 = 25V, Vout > VCC, voltage VA = 12.0V, VC = 25V, U+ = 15V, U- = 1.05mV, that is, U+ > U-, voltage comparator U1 outputs high level, that is, V1G = 30V (test point PR4), V1 GS =V1G-Vout≈30V-11.7V=18.3V>V TP , the drain-source channel of PMOS V1 is cut off, such as Fig.12As shown, the backflow current (node ​​VCC current: 533nA-24.7pA≈533nA) output by VCC2 to the power supply VCC1 can be ignored. It can be considered that VCC1 is isolated from the external voltage Vout, thereby achieving the purpose of protecting the power supply VCC1.

[0071] The present invention and its embodiments are described above, which is not restrictive. The drawings show only one embodiment of the present invention, and the actual structure is not limited thereto. In short, if ordinary technicians in the field are inspired by it and do not deviate from the purpose of the invention, they can creatively design a structure and embodiment similar to the technical solution, which should fall within the protection scope of the present invention.

Claims

1. A high-end ideal diode based on a differential amplifier, characterized in that: The circuit includes a PMOS tube, a differential amplifier circuit, a voltage comparator, and a bias power supply; The dual input ports of the differential amplifier circuit are respectively connected to the drain and source of the PMOS tube to compare the voltages, and the dual output ports of the differential amplifier circuit are connected to the dual input ports of the voltage comparator for amplification; The voltage comparator output signal is connected to the gate of the PMOS supervisor to control the on and off of the PMOS supervisor.

2. The high-end ideal diode based on a differential amplifier according to claim 1, characterized in that: The differential amplifier circuit includes a transistor pair V2, V3 and resistors R1 to R5, wherein resistors R2 = R3, R4 = R5; The two common ends of the transistor pair V2 and V3 are grounded via a resistor R1, and the input ends of the transistor pair V2 and V3 are connected to the drain and source of the PMOS main tube V1 through resistors R4 and R5 respectively as dual input ports of the differential amplifier; Resistors R2 and R3 are connected between the two output ends of the transistor pair V2 and V3 and the bias power supply. The potential difference between the two output ends of the transistor pair V2 and V3 is connected to the inverting end and the non-inverting end of the voltage comparator as a dual output port. The output signal of the voltage comparator is connected to the gate of the PMOS main tube V1 to control the gate of the PMOS main tube V1.

3. The high-end ideal diode based on a differential amplifier according to claim 2, characterized in that: The transistor pair is an NPN pair of transistors V2 and V3, wherein the base of the NPN pair of transistors V2 and V3 is an input terminal, the collector is an output terminal, and the emitter is a common terminal.

4. The high-end ideal diode based on a differential amplifier according to claim 2, characterized in that: The transistor pair is an NMOS pair of transistors V2 and V3, wherein the gate of the NMOS pair of transistors V2 and V3 is an input terminal, the drain is an output terminal, and the source is a common terminal.

5. The high-end ideal diode based on a differential amplifier according to claim 1, characterized in that: The differential amplifier includes a transistor pair V2, V3, and resistors R1 to R5, wherein resistors R2 = R3, R4 = R5; The two input ends of the transistor pair V2 and V3 are used as dual input ports, connected to the drain and source of the PMOS main tube V1 through resistors R4 and R5, and their voltages are detected respectively. The two common ends of the transistor pair V2 and V3 are connected to the bias power supply through resistor R1; The two output ends of the transistor pair V2 and V3 are grounded through resistors R2 and R3 respectively, and serve as dual output ports to output differential signals connected to the inverting end and the non-inverting end of the voltage comparator U1 respectively. The output signal of the voltage comparator controls the gate of the PMOS main tube V1.

6. The high-end ideal diode based on a differential amplifier according to claim 5, characterized in that: The transistor pair is a PNP pair of transistors V2 and V3, wherein the base of the PNP pair of transistors V2 and V3 is an input terminal, the collector is an output terminal, and the emitter is a common terminal.

7. The high-end ideal diode based on a differential amplifier according to claim 5, characterized in that: The transistor pair is a PMOS transistor pair, the gate of the PMOS transistor pair V2 and V3 is the input terminal, the drain is the output terminal, and the source is the common terminal.

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