Low-loss low-end ideal diode

Abstract

The invention relates to the technical field of diodes, in particular to a low-loss low-end ideal diode, a circuit consists of an NMOS (N-channel Metal Oxide Semiconductor) main tube and a differential amplifier circuit, four differential amplifiers are designed: two complementary MOS (Metal Oxide Semiconductor) tubes and diode geminate transistors, PMOS (P-channel Metal Oxide Semiconductor) geminate transistors and diode geminate transistors, PMOS geminate transistors and the like, and the differential amplifiers are equivalent to comparator circuits; the comparator is used for comparing the voltage difference between the grid electrode and the source electrode of the NMOS main tube, and when the power supply voltage is positively input, the NMOS main tube has very low conduction impedance, small static conduction voltage drop and relatively low loss; when the polarity of the power supply voltage is reversed, the NMOS main tube is cut off to prevent reverse current from flowing back to the power supply, so that the power supply circuit is protected; the circuit is used for a low-end ideal diode and is simple, low in cost and high in practicability.

Description

Technical Field

[0001] The invention relates to the technical field of power diodes, and in particular to a low-loss low-end ideal diode. Background Art

[0002] In electronic products, diodes are increasingly used because of their unidirectional conduction characteristics and their ability to prevent backflow. Diodes are one of the indispensable components. However, the conduction voltage drop (V F ) is about 0.6V, although the Schottky diode conduction voltage drop (V F ) is about 0.2~0.3V, with a small voltage drop, which is welcomed by many designers. Although Schottky diodes can meet some circuit design requirements, for circuits that require extremely low conduction voltage drop, the voltage drop of Schottky diodes is still greater than the voltage drop of MOS tubes, which is difficult to meet the needs of such circuits. For some voltage-sensitive circuits, MOS tubes with low impedance characteristics are more likely to be used to improve product reliability. Therefore, it is necessary to develop a unidirectional conduction device (ideal diode) with extremely low conduction voltage drop to reduce circuit power loss and improve power efficiency. Therefore, a low-loss ideal diode is needed to further reduce the voltage drop, and has the function of preventing backflow and protecting the previous stage, so as to minimize the loss and extend the battery working time.

[0003] According to the polarity of the controlled power supply, it is divided into High Side (high-end, high-side, high-side) load switch and Low Side (low-end, low-side, low-side) load switch, which are similar to controlling the live wire and neutral wire of the 220V AC power supply. High-end load switch: It connects or disconnects the power supply (battery or adapter) to a specific load through the control of an external enable signal. Compared with the low-end load switch, the high-end load switch "flows" current to the load, while the low-end load switch connects or disconnects the load to the negative pole, so it "draws" current from the load. The low-end ideal diode is installed between the load and the negative pole of the power supply as a low-end drive switch to control the conduction or disconnection of the negative pole of the power supply, so it "draws" current from the load.

[0004] The combination forms of low-end ideal diodes mainly include: NMOS main tube + NPN auxiliary tube, NMOS main tube + NMOS auxiliary tube, etc. In addition, the technical implementation scheme of low-end ideal diodes that is most similar to the present invention is as follows.

[0005] Diode solution: Diode is a natural Oring circuit because of its unidirectional conductivity. The most basic Oring circuit is to add a diode at the output end. Using a diode in series with the power supply is simple, but its disadvantage is that the voltage drop of the diode is 0.6V to 2V. As the input current increases, the voltage drop will also increase.

[0006] The NMOS main tube + NPN auxiliary tube technical solution (unidirectional conduction device patent number: TW200537799A) is a low-end ideal diode with unidirectional conductivity. The circuit uses a dual NPN auxiliary tube combination control logic circuit to control the power NMOS main tube, and uses two NPN tubes from the same manufacturer and the same batch, so that the parameters of the two NPN tubes can be basically equal, or preferably two NPN pairs of tubes packaged together, the parameters of the two are almost equal, so as to ensure proper switching and anti-backflow functions, and its insertion conduction voltage drop is low, which is suitable for ultra-low loss applications, and can be used as a low-loss low-end ideal power diode. The disadvantage is that the parameter requirements of the two NPN tubes are consistent, the bias resistance of the NPN tube is in the kilo-ohm level, and the static working current loss is in the milliampere level. The current loss is large, and the loss is large, such as Figure 1 shown.

[0007] NMOS main tube + NMOS auxiliary tube technical solution: (an ultra-low loss low-end ideal diode, patent number: CN202020206261.X), based on the above patent, it is improved by using dual NMOS auxiliary tubes to replace dual NPN auxiliary tubes, and simplifying the circuit. It is a low-end ideal diode with unidirectional conductivity. It is required to use two NMOS tubes from the same batch of the same manufacturer, so that the parameters of the two NMOS tubes can be basically equal, or preferably two NMOS pairs packaged together, the parameters of the two are almost equal. The circuit uses a dual NMOS auxiliary tube combination control logic circuit to control the power NMOS main tube. The bias resistance of the NMOS tube is in the megohm level, and the static operating current loss is in the microampere level. The current loss is small and the loss is small. Figure 2 shown.

[0008] NMOS tubes use electrons as "majority carriers". Compared with the "majority carrier" holes of PMOS tubes, electrons have higher mobility. At the same physical density, NMOS has higher transconductance and lower on-resistance than PMOS. The on-resistance of NMOS is generally 1 / 3 to 1 / 2 of that of PMOS of the same size. For the same on-resistance, NMOS generally requires less silicon wafers, so the gate capacitance and threshold voltage of NMOS are lower than those of PMOS.

[0009] NMOS tubes are used in a much wider range of applications than PMOS tubes. What PMOS tubes can do, NMOS tubes can also do. Almost all switching power supply topologies tend to use NMOS tubes (rather than PMOS tubes), such as forward, flyback, push-pull, half-bridge, full-bridge and other topologies. Under the same process and size area conditions, the on-resistance of PMOS tubes is larger than that of NMOS tubes, so the conduction loss of PMOS switch tubes is larger than that of NMOS. In addition, NMOS tubes have many applications, many demands, many models, and are cheap, making them suitable for use when connected to the negative pole of the power supply (low-end drive).

[0010] Therefore, it is necessary to propose a low-loss low-end ideal diode for the above problem, use a differential amplifier to compare the voltage difference between the source and drain of the NMOS tube, and then control the conduction and cutoff of the NMOS tube, and enrich the implementation methods of the low-end ideal diode. Summary of the invention

[0011] The technical problem to be solved by the present invention is to overcome the above technical defects and provide a low-loss low-end ideal diode.

[0012] In order to solve the above technical problems, the technical solution provided by the present invention is: a low-loss low-end ideal diode, including a circuit, the circuit is composed of a power supply VCC, an NMOS supervisor and a differential amplifier, the source of the NMOS supervisor V3 is connected to the power supply VCC through a resistor RL, and the drain is connected to the negative electrode of the power supply; the differential amplifier is used to compare the drain and source voltage difference of the NMOS supervisor;

[0013] When the NMOS tube is forward biased, the NMOS tube is turned on; when the NMOS tube is reverse biased, the NMOS tube is turned off.

[0014] Preferably, the differential amplifier includes a PMOS auxiliary tube V1, an NMOS auxiliary tube V2, diodes D1-D2 and resistors R1-R3;

[0015] The resistor R1 is arranged between the source of the PMOS auxiliary tube and the power supply VCC, the diode D1 is arranged between the drain of the PMOS auxiliary tube and the negative electrode of the power supply, and the resistor R3 is arranged between the gate of the PMOS auxiliary tube and the negative electrode of the power supply;

[0016] The resistor R2 is arranged between the drain of the NMOS auxiliary tube and the power supply VCC, the resistor R1 is also connected to the gate of the NMOS auxiliary tube, a diode D2 is also arranged between the source of the NMOS auxiliary tube and the source of the NMOS main tube, and the resistor R2 is also connected to the gate of the NMOS main tube V3.

[0017] Preferably, the differential amplifier includes an NMOS auxiliary tube V1, a PMOS auxiliary tube V2, diodes D1-D2 and resistors R1 and R2;

[0018] The drain of the NMOS auxiliary tube is connected to the power supply VCC through the resistor R1, the source is connected to the anode of the diode D1, and the resistor R1 is also connected to the gate of the NMOS main tube V3;

[0019] The source of the PMOS auxiliary tube is connected to the power supply VCC through the resistor R2, the drain is connected to the anode of the diode D2, the cathode of the diode D2 is connected to the source of the NMOS main tube, and the gate of the PMOS auxiliary tube is connected to the drain of the NMOS main tube.

[0020] Preferably, the differential amplifier comprises a PMOS pair of tubes V1, V2, diodes D1-D2 and resistors R1-R4;

[0021] The sources of the PMOS tubes V1 and V2 are connected to the resistors R1 and R2 respectively, and the drains are connected to the anodes of the diodes D1 and D2 respectively;

[0022] The gate of the PMOS pair tube V1 is connected to the drain of the NMOS main tube through the resistor R3, and the gate of the PMOS pair tube V2 is connected to the source of the NMOS main tube through the resistor R4;

[0023] The gate of the NMOS main tube is connected to the resistor R2, and the gate of the PMOS tube V2 is also connected to the resistor R1.

[0024] Preferably, the differential amplifier comprises a pair of PMOS tubes V1 and V2 and resistors R1 and R2;

[0025] The source of the PMOS pair tube V1 is connected to the power supply VCC, the drain is connected to the gate of the PMOS pair tube V2, the gate of the PMOS pair tube V1 is connected to the resistor R1, and the resistor R1 is connected to the drain of the NMOS main tube;

[0026] A resistor R2 is connected between the source of the PMOS transistor V2 and the power supply VCC. The resistor R2 is also connected to the gate of the NMOS transistor. The drain of the PMOS transistor V2 is connected to the source of the NMOS transistor.

[0027] The PMOS tube model is NVTFS5124PLTAG, and the NMOS tube model is BSP030.

[0028] Compared with the prior art, the advantages of the present invention are: the circuit has a backflow prevention function and can protect the previous stage circuit; it has lower loss and small static current loss; it uses a low-end NMOS tube switch and a differential amplifier, the circuit is simple, the cost is very low, and the practicability is strong. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is the ideal diode schematic diagram composed of NMOS main tube + NPN auxiliary tube in the existing technology;

[0030] Figure 2 This is the ideal diode schematic diagram composed of NMOS main tube + NMOS auxiliary tube in the prior art;

[0031] Figure 3 The schematic diagram of the ideal diode composed of complementary MOS tube + NMOS tube of the present invention (I);

[0032] Figure 4 The schematic diagram of the ideal diode composed of complementary MOS tube + NMOS tube of the present invention (II);

[0033] Figure 5 The schematic diagram of the ideal diode composed of a PMOS pair of transistors and an NMOS main tube of the present invention (III);

[0034] Figure 6 The schematic diagram of the ideal diode composed of a PMOS pair of transistors and an NMOS main tube of the present invention (IV);

[0035] Figure 7 for Figure 3 Forward conduction simulation;

[0036] Figure 8 for Figure 3 Reverse cutoff simulation;

[0037] Fig. 9 for Figure 4 Forward conduction simulation;

[0038] Fig.10 for Figure 4 Reverse cutoff simulation;

[0039] Fig.11 for Figure 5 Forward conduction simulation;

[0040] Fig.12 for Figure 5 Reverse cutoff simulation;

[0041] Fig.13 for Figure 6 Forward conduction simulation;

[0042] Fig.14 for Figure 6 Reverse cutoff simulation. DETAILED DESCRIPTION

[0043] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0044] Implementation method 1: Ideal diode composed of complementary MOS tube + NMOS tube (I)

[0045] Based on the NMOS pair (auxiliary tube) + NMOS main tube, the NMOS pair is changed to PMOS auxiliary tube and NMOS auxiliary tube, and the NMOS main tube remains unchanged to realize a low-loss low-end ideal diode. The circuit consists of PMOS auxiliary tube V1, NMOS auxiliary tube V2, NMOS main tube V3, diode pair D1, D2, resistors R1~R3, etc. Figure 3 As shown, the PMOS auxiliary tube V1 and the NMOS auxiliary tube V2 constitute a complementary MOS tube differential amplifier.

[0046] When the voltage VCC is positively input (VCC>V TN, VCC>-V TP , V TN 、V TP The gate voltage of V1 is 0V, and the source voltage VA is -V TP , remain stable, PMOS tube V1 is turned on; for NMOS tube V2, the gate voltage is VA. Due to the existence of diode D2, V2 tube is in the linear impedance area (weak conduction state), the resistance value of resistor R2 is relatively small, the voltage drop obtained by voltage division is small, VB is high level, NMOS tube V3 is turned on, and the conduction impedance is very low.

[0047] When the voltage VCC is input in reverse (the positive and negative poles of the power supply VCC are reversely connected); since the diode D1 is reversely cut off, the body diode of the PMOS tube V1 cannot be turned on, and the body diode of the NMOS tube V3 is reversely cut off and cannot be turned on, preventing the reverse current from flowing back to the power supply and protecting the power supply circuit. If the PMOS tube V1 and the NMOS tube V2 are MOS tubes inside the chip, there is no body diode, and the diodes D1 and D2 can be omitted.

[0048] Implementation Method 2: Ideal Diode Composed of Complementary MOS Tube + NMOS Tube (II)

[0049] Similarly, referring to the first embodiment, the NMOS pair is changed to a PMOS auxiliary tube and an NMOS auxiliary tube, and the NMOS main tube remains unchanged, so as to realize a low-loss low-end ideal diode. The circuit is composed of an NMOS auxiliary tube V1, a PMOS auxiliary tube V2, an NMOS main tube V3, a diode pair D1, D2, resistors R1-R2, etc. Figure 4 As shown, the NMOS auxiliary tube V1 and the PMOS auxiliary tube V2 constitute a complementary MOS tube differential amplifier.

[0050] When the voltage VCC is positively input (VCC>V TN , VCC>-V TP , V TN 、V TP The gate voltage of PMOS tube V2 is 0V, V2 tube is turned on, and the source voltage of V2 tube VB=-V TP ; The gate voltage of PMOS tube V1 is VA = -V TP , V1 tube is cut off, the drain voltage VB of V1 tube is high level, the gate voltage VB of NMOS tube V3 is high level, the source voltage is about 0V, the NMOS tube V3 is turned on, and the on-resistance is very low.

[0051] When the voltage VCC is input in reverse (power supply VCC polarity is reversed), since the diode D1 is reversely cut off, the body diode of the NMOS tube V1 cannot be turned on, and similarly, the body diode of the NMOS tube V3 is reversely cut off and cannot be turned on, preventing the reverse current from flowing back to the power supply and protecting the power supply circuit. If the NMOS tube V1 and the PMOS tube V2 are MOS tubes inside the chip, there is no body diode, and the diodes D1 and D2 can be omitted.

[0052] Implementation method 3: Ideal diode composed of PMOS pair and NMOS main tube (III)

[0053] Similarly, referring to the first embodiment, the NMOS pair is replaced with a PMOS pair, and the NMOS main tube remains unchanged, to realize a low-loss low-end ideal diode. The circuit is composed of a PMOS pair of tubes V1 and V2, an NMOS main tube V3, a diode pair of tubes D1 and D2, resistors R1 to R4, etc., as shown in FIG. Figure 5 As shown, the PMOS pair of tubes V1 and V2 constitute a PMOS pair of tubes differential amplifier.

[0054] When the voltage VCC is positively input (VCC>V TN , VCC>-V TP , V TN 、V TP The gate voltage of V1 is 0V, the source voltage VA is stable, VA = VCC × R4 / (R1 + R4), and the PMOS tube V1 is turned on; for the PMOS tube V2, the gate voltage of V2 is VA, the maximum source voltage VB of V2 is VCC, V2 is turned on and is in the linear impedance region, and the source voltage VB of V2 is stable, VB = VA-V TP (High level), the NMOS supervisor V3 is turned on, and the on-resistance is very low.

[0055] When the voltage VCC is input in reverse (power supply VCC polarity is reversed), since the diode D1 is reversely cut off, the body diode of the PMOS tube V1 cannot be turned on, and similarly, the body diode of the NMOS tube V3 is reversely cut off and cannot be turned on, preventing the reverse current from flowing back to the power supply and protecting the power supply circuit. If the PMOS tubes V1 and V2 are PMOS tubes in the chip, there is no body diode, and the diodes D1 and D2 can be omitted.

[0056] Implementation 4: Ideal diode composed of PMOS pair and NMOS main tube (IV)

[0057] Similarly, referring to the first embodiment, the NMOS pair of transistors is replaced by a PMOS pair of transistors, and the NMOS main tube remains unchanged, so as to realize a low-loss low-end ideal diode. The circuit is composed of the PMOS pair of transistors V1 and V2, the NMOS main tube V3, the resistors R1 and R2, etc., as shown in FIG. Figure 6 As shown, the PMOS pair of tubes V1 and V2 constitute a PMOS pair of tubes differential amplifier.

[0058] When the voltage VCC is positively input (VCC>V TN , VCC>-V TP , V TN 、V TP They are the turn-on threshold voltages of NMOS tube V3 and PMOS tube V1 / V2 respectively), the gate voltage of V1 is 0V, the source voltage of V1 is VCC, the PMOS tube V1 is turned on, and the drain voltage of V1 is VA≈VCC; for the PMOS tube V2, the gate voltage of V2 is VA=VCC, and the maximum value of the source voltage VB is VCC. Obviously, the PMOS tube V2 is cut off, the gate voltage of NMOS tube V3 is VB=VCC, and the source voltage is about 0V, the NMOS tube V3 is turned on, and the on-resistance is very low.

[0059] When the voltage VCC is input in reverse (VCC1 polarity is reversed), the gate and source impedance of the PMOS tube are very large and cannot be turned on. Similarly, the body diode of the NMOS tube V3 is reversely cut off and cannot be turned on, preventing reverse current from flowing back to the power supply and protecting the power supply circuit.

[0060] according to Figure 3 to Figure 6 The circuit schematic is simulated and tested using the National Instruments simulation software Multisim (version V14.0). The PMOS tube is from ON Semiconductor, model NVTFS5124PLTAG, and the minimum on-threshold voltage V TP(MIN) =-1.5V, maximum value V TP(MAX) =-2.5V, typical value V not given TP , the on-state current can reach -6A, and the on-state impedance R DS(ON) =0.26Ω(V GS =-10V), R DS(ON) =0.38Ω(V GS =-4.5V). The NMOS tube is made by NXP, model BSP030, and the minimum on-threshold voltage is V TN(MIN) =1V, maximum value V TN(MAX) =2.8V, typical value V is not given TN , the conduction current is up to 10A, the conduction resistance R DS(ON) =30mΩ(V GS =10V), R DS(ON) =50mΩ(V GS =4.5V). The diode model is 1N4007, with a conduction current of 3A (corresponding conduction voltage drop V FThe load resistance RL is 10Ω, and the specific simulation test is as follows.

[0061] Implementation Method 1 Simulation

[0062] DC power supply forward conduction simulation test: VCC = -VCC1 = -12V (switch J1 is closed, switch J2 is open), the gate voltage of V1 is 0V, the source voltage is 2.29V (test point PR3), the PMOS tube V1 is turned on; the gate voltage of NMOS tube V2 is 2.29V, the drain voltage is 9.72V, the V2 tube is in the linear impedance area, the resistance value of resistor R2 is relatively small, and the voltage drop is small. The gate and source voltage difference of V3 tube is 9.72V-24.2mV≈9.72V>V TN , NMOS V3 is turned on, the on-state voltage drop is 24.2mV, corresponding to the on-state impedance R DS(ON) =24.2mV / 1.20A=20.0mΩ, the impedance is very low, such as Figure 7 shown.

[0063] DC power supply reverse cutoff simulation test: When the voltage VCC is reversely input, VCC = -VCC2 = -12V (switch J2 is closed, switch J1 is open). Since the diode D1 is reversely cutoff, the body diode of the PMOS tube V1 cannot be turned on. Similarly, the body diode of the NMOS tube V3 is reversely cutoff and cannot be turned on, preventing the reverse current (-162nA, test point PR2) from flowing back to the power supply and protecting the power supply circuit. Figure 8 If the PMOS tube V1 and the NMOS tube V2 are MOS tubes inside the chip, there is no body diode, and the diodes D1 and D2 can be omitted.

[0064] Implementation Method 2 Simulation

[0065] DC power supply forward conduction simulation test: VCC = VCC1 = 12V (switch J1 is closed, switch J2 is open). For PMOS tube V2, the gate voltage is 0V, the source voltage VA = 2.3V, the current through R2 is (12V-2.3V) / 10kΩ = 0.97mA, and the corresponding V2 tube conduction impedance is V2R DS(ON) =(2.3V-0.6V) / 0.97mA=1.75kΩ, PMOS tube V2 is in the linear impedance region; that is, the gate voltage of V1 tube is VA=2.3V, the drain voltage is VB=9.23V, the current passing through R1 is (12V-9.23V) / 10kΩ=0.273mA, and the corresponding on-resistance of V1 tube is V1R DS(ON)=(9.23V-0.6V) / 0.273mA=31.611kΩ, NMOS tube V1 is also in the linear impedance region; the gate voltage of NMOS tube V3 is VB=9.23V, the source voltage is about 0V, NMOS tube V3 is turned on, the on-resistance is very low, the on-voltage drop is 24.7mV, and the corresponding on-resistance R DS(ON) =24.7mV / 1.20A=20.58mΩ, the impedance is very low, such as Fig. 9 shown.

[0066] DC power supply reverse cutoff simulation test: When the voltage VCC is reversely input, VCC = -VCC2 = -12V (switch J2 is closed, switch J1 is open). Since the diode D1 is reversely cutoff, the body diode of the PMOS tube V1 cannot be turned on. Similarly, the body diode of the NMOS tube V3 is reversely cutoff and cannot be turned on, preventing the reverse current (69.8nA, test point PR2) from flowing back to the power supply and protecting the power supply circuit. Fig.10 If the NMOS tube V1 and the PMOS tube V2 are MOS tubes inside the chip, there is no body diode, and the diodes D1 and D2 can be omitted.

[0067] Implementation Method 3 Simulation

[0068] DC power supply forward conduction simulation test: VCC = VCC1 = 12V (switch J1 is closed, switch J2 is open), the gate voltage of V1 is 0V, the source voltage VA remains stable, VA = VCC × R4 / (R1+R4) = 12V / 2 = 6.0V, and the PMOS tube V1 is in the linear region; for the PMOS tube V2, the gate voltage of V2 is VA = 6.0V, the source voltage of V2 is VB = 8.30V (the maximum is VCC = 12V), V2 is turned on and is in the linear impedance region, and the source voltage VB of V2 remains stable, VB = VA-V TP =8.30V (high level), the gate-source voltage difference of V3 is 8.30V-25.7mV=8.3V>V TN , NMOS V3 is turned on, the on-state voltage drop is 25.7mV, corresponding to the on-state impedance R DS(ON) =25.7mV / 1.20A=21.4mΩ, the impedance is very low, such as Fig.11 As shown, the on-resistance R DS(ON) Affected by the gate-source voltage difference of V3 tube, the larger the gate-source voltage difference, the lower the impedance.

[0069] DC power supply reverse cutoff simulation test: When the voltage VCC is reversely input, VCC = -VCC2 = -12V (switch J2 is closed, switch J1 is open). Since the diode D1 is reversely cutoff, the body diode of the PMOS tube V1 cannot be turned on. Similarly, the body diode of the NMOS tube V3 is reversely cutoff and cannot be turned on, preventing the reverse current (-5.12nA, test point PR2) from flowing back to the power supply and protecting the power supply circuit. Fig.12 If the PMOS tubes V1 and V2 are PMOS tubes in the chip, there is no body diode, and the diodes D1 and D2 can be omitted.

[0070] Implementation Method 4 Simulation

[0071] DC power supply forward conduction simulation test: VCC = VCC1 = 12V (switch J1 is closed, switch J2 is open), the gate voltage of V1 is 0V, the source voltage of V1 is VCC, the PMOS tube V1 is turned on, and the drain voltage of V1 is VA = VCC = 12V; for the PMOS tube V2, the gate voltage of V2 is VA = VCC = 12V, and the maximum value of the source voltage VB is VCC. Obviously, the PMOS tube V2 is cut off, VB = VCC, and the gate and source voltage difference of V3 is 12.0V-22.7mV≈12V>V TN , NMOS V3 is turned on, the on-state voltage drop is 22.7mV, corresponding to the on-state impedance R DS(ON) =22.7mV / 1.20A=18.9mΩ, the impedance is very low, such as Fig.13 As shown, the on-resistance R DS(ON) Affected by the gate-source voltage difference of V3 tube, the larger the gate-source voltage difference, the lower the impedance.

[0072] DC power supply reverse cutoff simulation test: When the voltage VCC is reversely input, VCC = -VCC2 = -12V (switch J2 is closed, switch J1 is open), the gate and source voltage difference of PMOS tube V1 is V1 GS =0V-(-VCC)=VCC>V TP , V1 tube is cut off, and the body diode of NMOS tube V3 is reversely cut off and cannot be turned on, preventing the reverse current (-5.13nA, test point PR4) from flowing back to the power supply and protecting the power supply circuit. Fig.14 shown.

[0073] The beneficial effects of the present invention are: compared with the milliampere level of current loss controlled by traditional power diodes or triodes, the static current loss is small, and there is no backflow current. The use of the circuit of the present invention reduces the static loss of the equipment, prolongs the working time of the battery, reduces the equipment maintenance cost, and greatly reduces the loss. It is suitable for the application of ultra-low loss ideal diode circuits in the Internet of Things NB-IoT. The circuit is very simple and has a very low cost advantage.

[0074] The present invention and its embodiments are described above, which is not restrictive. The drawings show only one embodiment of the present invention, and the actual structure is not limited thereto. In short, if ordinary technicians in the field are inspired by it and do not deviate from the purpose of the invention, they can creatively design a structure and embodiment similar to the technical solution, which should fall within the protection scope of the present invention.

Claims

1. A low-loss low-end ideal diode, comprising a circuit, characterized in that: The circuit is composed of a power supply VCC, an NMOS supervisor and a differential amplifier. The source of the NMOS supervisor V3 is connected to the power supply VCC through a resistor RL, and the drain is connected to the negative electrode of the power supply. The differential amplifier is used to compare the drain and source voltage difference of the NMOS supervisor. When the NMOS tube is forward biased, the NMOS tube is turned on; when the NMOS tube is reverse biased, the NMOS tube is turned off.

2. A low-loss low-end ideal diode according to claim 1, characterized in that: The differential amplifier includes a PMOS auxiliary tube V1, an NMOS auxiliary tube V2, diodes D1-D2 and resistors R1-R3; The resistor R1 is arranged between the source of the PMOS auxiliary tube and the power supply VCC, the diode D1 is arranged between the drain of the PMOS auxiliary tube and the negative electrode of the power supply, and the resistor R3 is arranged between the gate of the PMOS auxiliary tube and the negative electrode of the power supply; The resistor R2 is arranged between the drain of the NMOS auxiliary tube and the power supply VCC, the resistor R1 is also connected to the gate of the NMOS auxiliary tube, a diode D2 is also arranged between the source of the NMOS auxiliary tube and the source of the NMOS main tube, and the resistor R2 is also connected to the gate of the NMOS main tube V3.

3. A low-loss low-end ideal diode according to claim 1, characterized in that: The differential amplifier includes an NMOS auxiliary tube V1, a PMOS auxiliary tube V2, diodes D1-D2 and resistors R1 and R2; The drain of the NMOS auxiliary tube is connected to the power supply VCC through the resistor R1, the source is connected to the anode of the diode D1, and the resistor R1 is also connected to the gate of the NMOS main tube V3; The source of the PMOS auxiliary tube is connected to the power supply VCC through the resistor R2, the drain is connected to the anode of the diode D2, the cathode of the diode D2 is connected to the source of the NMOS main tube, and the gate of the PMOS auxiliary tube is connected to the drain of the NMOS main tube.

4. The low-loss low-end ideal diode according to claim 1, characterized in that: The differential amplifier includes a pair of PMOS tubes V1, V2, diodes D1-D2 and resistors R1-R4; The sources of the PMOS tubes V1 and V2 are connected to the resistors R1 and R2 respectively, and the drains are connected to the anodes of the diodes D1 and D2 respectively; The gate of the PMOS pair tube V1 is connected to the drain of the NMOS main tube through the resistor R3, and the gate of the PMOS pair tube V2 is connected to the source of the NMOS main tube through the resistor R4; The gate of the NMOS main tube is connected to the resistor R2, and the gate of the PMOS tube V2 is also connected to the resistor R1.

5. The low-loss low-end ideal diode according to claim 1, characterized in that: The differential amplifier includes a pair of PMOS tubes V1 and V2 and resistors R1 and R2; The source of the PMOS pair tube V1 is connected to the power supply VCC, the drain is connected to the gate of the PMOS pair tube V2, the gate of the PMOS pair tube V1 is connected to the resistor R1, and the resistor R1 is connected to the drain of the NMOS main tube; A resistor R2 is connected between the source of the PMOS transistor V2 and the power supply VCC. The resistor R2 is also connected to the gate of the NMOS transistor. The drain of the PMOS transistor V2 is connected to the source of the NMOS transistor.

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