Flexible circuit substrate for bearing wafer and electronic device

Abstract

The invention provides a flexible circuit substrate for bearing a wafer and an electronic device, and the flexible circuit substrate comprises an insulating base material which is provided with a conductive copper layer, a first tin layer, a second tin layer and a first solder mask layer. The first tin layer has a first tin thickness, the second tin layer has a second tin thickness, and the first tin thickness is smaller than the second tin thickness. A first tin surface of the first tin layer and a second tin surface of the second tin layer substantially belong to the same plane.

Description

Technical Field

[0001] The present disclosure relates to a flexible circuit substrate, and in particular to a flexible circuit substrate capable of carrying a chip. Background Art

[0002] Flexible circuit substrates are often used in electronic devices with limited space to carry chips because they can be bent. For this, you can refer to the flexible tape circuit substrate products of Chipbond Technology Co., Ltd., which can be used in various electronic devices such as flat-panel displays, wearable devices, mobile phones, tablets, notebook computers, automotive panels, industrial control panels, etc.

[0003] Flexible circuit substrates are mostly tape-shaped films. In the industry, the combination of flexible circuit substrates and chips has various names depending on the different assembly modes, such as TCP (Tape Carrier Package) or COF (Chip On Film). Both TCP and COF use flexible circuit substrates as carriers for packaging chips, and use heat pressing to connect the gold bumps on the chip with the inner leads of the copper wiring pattern on the flexible circuit substrate.

[0004] In the prior art, in order to connect the flexible circuit substrate to the gold bumps of the chip, the presence of gold-tin eutectic is necessary, where gold is provided by the gold bumps of the chip, and tin is provided by the tin formed on the surface of the inner pins. Therefore, the surface of the inner pins is plated with a tin layer. In addition to the inner pins, the copper wiring pattern also has conductive terminals such as outer pins that connect to other electronic components, and these terminals are usually also plated with tin. The non-pin area on the copper wiring pattern is protected by covering with solder mask ink.

[0005] It is worth mentioning that as the space inside the electronic device becomes smaller and smaller, the degree to which the flexible circuit substrate needs to be bent is also increasing. Therefore, it is necessary to ensure the bendability of the flexible circuit substrate, that is, to ensure that the circuit pattern will not be damaged due to repeated or long-term bending. Patent document 1 (Chinese patent CN107006116 B) discloses a solution of setting a double solder mask structure above the circuit pattern in the bendable area of ​​the flexible circuit substrate, thereby alleviating the curvature of the bendable area, thereby reducing the physical stress experienced by the circuit pattern. Patent document 2 (Chinese patent publication CN110121234A) discloses a similar approach. In addition to setting a double solder mask structure in the bendable area, it is also proposed to set a thin tin layer above the circuit pattern to fully protect the circuit pattern, and in the part outside the bendable area, a thick tin layer is set to cover the thin tin layer. In addition to providing the purpose of connecting with the chip or other electronic components, the thick tin layer also enhances the protection effect of the circuit pattern. Summary of the invention

[0006] After research, the inventors of the present disclosure found that the above-mentioned conventional technology still has many problems in actual operation. For example, the double solder mask structure in Patent Document 1 hinders bending due to the increased thickness, and is not suitable for the trend of increasingly smaller bending radius required by current flexible circuit substrates. In Patent Document 2, the thin tin layer not covered by the thick tin layer will form a visible height difference on the surface of the flexible circuit substrate with other thick tin layers covered with the thin tin layer. The inventors of the present disclosure found that when the flexible circuit substrate is bent, the height difference on the surface of the tin layer is prone to accumulate stress, causing cracks. In addition, the height difference formed on the surface will also cause troubles in subsequent processing.

[0007] In view of the above, an embodiment of the present disclosure proposes a novel flexible circuit substrate, wherein a thin tin layer is arranged above the circuit pattern (i.e., the conductive copper layer) in the bendable area, thereby protecting the conductive copper layer below from corrosion, collision or scratching, and further avoiding reliability issues. After research, the inventors of the present disclosure found that the solder mask is not as protective of the conductive copper layer as the tin layer, so there is still a need to protect the conductive copper layer by the tin layer. On the other hand, even though the hardness of tin is higher than that of copper, by providing a thinner tin layer in the bendable area, the appropriate bendability and softness of the flexible circuit substrate can still be maintained. Specifically, in the embodiment of the present disclosure, the surfaces of the thin tin layer and the thick tin layer belong to the same plane, that is, the height is the same and there is no visible height difference, which avoids the problem of stress concentration.

[0008] In another embodiment, a novel flexible circuit substrate is provided, wherein the copper thickness of the circuit pattern (i.e., the conductive copper layer) in the bendable area is thicker, while the copper thickness of the circuit pattern (i.e., the conductive copper layer) outside the bendable area is thinner. The thicker copper in the bendable area can provide better ductility, thereby maintaining the bending resistance of the circuit pattern in the bendable area and avoiding premature damage due to repeated or prolonged bending.

[0009] According to an embodiment of the present disclosure, a flexible circuit substrate for carrying a chip includes:

[0010] an insulating substrate;

[0011] A conductive copper layer with a wiring pattern is located on the insulating substrate, and the conductive copper layer has a first region and a second region that are electrically connected to each other;

[0012] A first tin layer is located above the first region of the conductive copper layer, and the first tin layer has a first tin thickness;

[0013] A second tin layer is located above the second region of the conductive copper layer, the second tin layer having a second tin thickness; and

[0014] A first solder resist layer at least partially covers the first tin layer;

[0015] wherein a first tin surface of the first tin layer not bonded to the conductive copper layer and a second tin surface of the second tin layer not bonded to the conductive copper layer are substantially in the same plane;

[0016] The first tin thickness is smaller than the second tin thickness.

[0017] According to another embodiment of the present disclosure, a flexible circuit substrate for carrying a chip includes:

[0018] an insulating substrate;

[0019] A conductive copper layer with a wiring pattern is on the insulating substrate, and has a first area and a second area that are conductive to each other. The conductive copper layer located in the first area has a first copper thickness, and the conductive copper layer located in the second area has a second copper thickness, and the first copper thickness is greater than the second copper thickness.

[0020] The disclosed embodiment also provides an electronic device, which includes the flexible circuit substrate as described above and a chip, wherein the chip is disposed on the flexible circuit substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic structural diagram of a flexible circuit substrate according to a first embodiment of the present disclosure;

[0022] Figure 2 is a schematic structural diagram of a flexible circuit substrate according to a second embodiment of the present disclosure;

[0023] Figure 3A , Figure 3B , Figure 3C and Figure 3D is a schematic structural diagram of a flexible circuit substrate according to another embodiment of the present disclosure;

[0024] Figure 4 is a schematic structural diagram of a flexible circuit substrate according to another embodiment of the present disclosure;

[0025] Figure 5 FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The following will refer to the attached drawings to demonstrate the preferred embodiments of the present disclosure. In order to avoid blurring the content of the present disclosure, the following description also omits the conventional components, related materials, and related processing technologies. At the same time, in order to clearly illustrate the present disclosure, the components in the attached drawings may not be drawn according to the actual size or relative proportion.

[0027] Please refer to Figure 1As shown, it is a first embodiment of the flexible circuit substrate 1 disclosed in the present invention, comprising an insulating substrate 10 , a conductive copper layer 20 , a first tin layer 30 , a second tin layer 33 , and a solder mask 40 .

[0028] The insulating substrate 10 is a substrate, and the conductive copper layer 20 which has not yet been patterned can be formed on the insulating substrate 10 by sputtering. The insulating substrate 10 can use a soft material that is resistant to chemicals and heat, such as polyester, polyamide, polyimide, etc. The thickness of the insulating substrate 10 is generally 12 to 85 μm, preferably 20 to 50 μm. The thickness of the conductive copper layer 20 is, for example, 2 to 20 μm, preferably 5 to 12 μm. The insulating substrate plated with a conductive copper layer is generally called a copper foil substrate (CCL, Copper CladLaminate), and reference can be made to the commercially available copper foil substrate products S'PERFLEX or METALOYAL. Subsequently, the conductive copper layer 20 on the insulating substrate 10 can be formed into a wiring pattern by conventional photolithography and etching methods, which will not be described in detail here.

[0029] like Figure 1 As shown, in this embodiment, the conductive copper layer 20 with the wiring pattern has a first area A1 and two second areas A2 located on both sides of the first area A1. The conductive copper layer 20 located in the first area A1 and the conductive copper layer 20 located in the second area A2 are electrically connected to each other. Preferably, the conductive copper layer 20 located in the first area A1 and the conductive copper layer 20 located in the second area A2 belong to the same circuit. It should be noted that in other embodiments, the number and position of the first area A1 and the second area A2 can also be changed, not limited to Figure 1 Example shown.

[0030] Preferably, the first area A1 of the conductive copper layer 20 is located in the bendable area of ​​the flexible circuit substrate 1. The so-called bendable area of ​​the flexible circuit substrate 1 refers to the part with a measurable curvature when the flexible circuit substrate 1 is set in an electronic device and is bent, that is, the part that will be subjected to the stress caused by the bending. However, the first area A1 does not necessarily have to completely overlap with the bendable area of ​​the flexible circuit substrate 1. In other embodiments, the range of the first area A1 may be larger or smaller than the bendable area of ​​the flexible circuit substrate 1. Preferably, the first area A1 covers the part that is subjected to the maximum stress when the flexible circuit substrate 1 is bent. In contrast, the second area A2 is usually located at a position that does not need to be bent, for example, it can be located in the so-called pin area, that is, the position where the crystal sheet or various electronic components (not shown in the figure) can usually be connected, but the present disclosure is not limited to this.

[0031] Further Figure 1As shown, a first tin layer 30 is provided above the first area A1 of the conductive copper layer 20, and a second tin layer 33 is provided above the second area A2 of the conductive copper layer 20. The first tin layer 30 and the second tin layer 33 do not overlap each other, and the first tin layer 30 has a thickness T1, and the second tin layer 33 has a thickness T2. In one embodiment, the thickness T1 is preferably less than 0.2 μm, more preferably less than or equal to 0.1 μm, for example, it can be 0.03 μm, 0.05 μm, or 0.08 μm. The thickness T2 can be between 0.2 μm and 2 μm, for example, it can be 0.3 μm, 1 μm, or 1.5 μm. In other embodiments, as long as the thickness T1 is less than the thickness T2, the values ​​of the thicknesses T1 and T2 can also have other choices, and are not limited to the above values ​​or ranges.

[0032] On the other hand, in this embodiment, the total thickness of the conductive copper layer 20 plus the first tin layer 30 or the conductive copper layer 20 plus the second tin layer 33 remains the same. Therefore, when the first area A1 of the conductive copper layer 20 has a thickness T3 and the second area A2 of the conductive copper layer 20 has a thickness T4, since the thickness T1 of the first tin layer 30 is less than the thickness T2 of the second tin layer 33, the thickness T3 will be greater than the thickness T4.

[0033] It is worth noting that the present disclosure is not limited to this. In other words, in other embodiments, the aforementioned feature that the thickness T1 is greater than the thickness T2 and the feature that the thickness T3 is greater than the thickness T4 do not necessarily hold simultaneously, and the total thickness of the conductive copper layer 20 plus the first tin layer 30 or the second tin layer 33 does not necessarily have to be consistent. In one embodiment, the difference between the thickness T3 and the thickness T4 may be between 0.1 μm and 1.9 μm, for example, 0.3 μm, 1 μm, or 1.8 μm.

[0034] As shown in the figure, the first tin layer 30 has a tin surface S1, which is located on the opposite side of the bonding surface with the conductive copper layer 20; similarly, the second tin layer 33 has a tin surface S2, which is also located on the opposite side of the bonding surface with the conductive copper layer 20. Specifically, in addition to satisfying the condition that the thickness T1 is less than the thickness T2, the tin surface S1 of the first tin layer 30 and the tin surface S2 of the second tin layer are substantially at the same height and belong to the same plane. That is, from the surface of the flexible circuit substrate 1 relative to the conductive copper layer 20 (i.e. Figure 1), even though the first tin layer 30 and the second tin layer 33 have different thicknesses, there is no significant height difference on the top. In one embodiment, even when observed with a scanning electron microscope (SEM) at a magnification of 300,000, the tin surface S1 and the tin surface S2 still appear to belong to the same plane without a significant height difference. It is also noted that for general technicians familiar with the production of flexible circuit substrates, the surfaces of tin layers that undergo the same tin plating process are considered to belong to the same plane. Although the first tin layer 30 and the second tin layer 33 undergo different tin plating processes and have different thicknesses, the tin surface S1 and the tin surface S2 are still the same height and belong to the same plane as the surfaces of tin layers that undergo the same tin plating process.

[0035] On the contrary, the difference in thickness between the first tin layer 30 and the second tin layer 33 will be buried below (that is, at the interface with the conductive copper layer 20), and will not be exposed. In other words, the horizontal range of the first tin layer 30 and the second tin layer 33 should be judged from below. In this way, even if the first tin layer 30 and the second tin layer 33 have different thicknesses, they can form a flat surface together with the same height, which can reduce the accumulation of stress during bending, avoid uneven force, and avoid the trouble of uneven surface during subsequent processing.

[0036] In addition, the first tin layer 30 is covered with a solder mask 40. The solder mask 40 can be attached to the first tin layer 30 by adhesive lamination or printing. The solder mask 40 has the effect of protecting the conductive copper layer 20 from corrosion, collision or scratching, and can also alleviate the influence of stress on the conductive copper layer 20 during bending. In one embodiment, the solder mask 40 can also be used as a mask to form the second tin layer 33, so the solder mask 40 only covers the first tin layer 30, but not the second tin layer 33. However, the present disclosure is not intended to be limited to this.

[0037] The solder mask 40 may be a cover layer (CL), may include materials such as solder resist components, or may be formed by screen printing using conventional epoxy resin (o-Cresol Novalac / Phenol / DGEBA) type ink or other suitable ink. In one embodiment, the thickness of the solder mask 40 may be in the range of 1 to 50 μm, for example, 40 μm or preferably 50 μm.

[0038] Please refer to Figure 2 As shown, it is a second embodiment of the flexible circuit substrate 1 disclosed in the present invention. Figure 1Compared with the first embodiment shown, the main difference is that the conductive copper layer 20 with the wiring pattern also has two third areas A3 and is respectively located between the first area A1 and the two second areas A2. The conductive copper layer 20 located in the third area A3 is electrically connected to the conductive copper layer 20 located in the first area A1 and the conductive copper layer 20 located in the second area A2. Preferably, the conductive copper layer 20 located in the third area A3 belongs to the same circuit as the conductive copper layer 20 located in the first area A1 and the conductive copper layer 20 located in the second area A2. It should also be noted that in other embodiments, the number and position of the third area A3 can also be changed, and are not limited to Figure 2 Example shown.

[0039] Further Figure 2 As shown, there is a third tin layer 35 above the third area A3 of the conductive copper layer 20. The first tin layer 30, the third tin layer 35, and the second tin layer 33 are connected to each other without overlapping, and their surfaces are coplanar. Specifically, the thickness of the third tin layer 35 is between the thickness T1 of the first tin layer 30 and the thickness T2 of the second tin layer 33. The thickness of the third tin layer 35 can be gradually increased (or decreased) along the distance in the horizontal direction to serve as a buffer between the thickness T1 of the first tin layer 30 and the thickness T2 of the second tin layer 33, so as to further avoid the obvious thickness difference causing stress concentration during bending. On the other hand, in this embodiment, the total thickness of the conductive copper layer 20 in the first area A1, the second area A2, and the third area A3 after adding the first tin layer 30, the second tin layer 33, and the third tin layer 35 respectively remains consistent. Therefore, the thickness of the conductive copper layer 20 located in the third area A3 is between the thickness of the conductive copper layer 20 located in the first area A1 and the thickness of the conductive copper layer 20 located in the second area A2, and when the thickness of the third tin layer 35 can be gradually increased (or decreased) along the horizontal distance, the thickness of the conductive copper layer 20 located in the third area A3 will also be gradually decreased (or increased) accordingly, which also helps to reduce the concentration of stress. However, the present disclosure is not intended to be limited to this. In other embodiments, the total thickness of the conductive copper layer 20 in the first area A1, the second area A2, and the third area A3 after adding the first tin layer 30, the second tin layer 33, and the third tin layer 35, respectively, does not necessarily have to be consistent. In addition, the thickness of the third tin layer 35 or the thickness of the conductive copper layer 20 located in the third area A3 can be gradually increased (or decreased) linearly or nonlinearly, or can be gradually increased (or decreased) in a stepwise manner.

[0040] In one embodiment, the horizontal length of a single third region A3 may be between 5 μm and 200 μm, such as 50 μm, 100 μm or 150 μm. The horizontal lengths of different third regions A3 are not necessarily the same.

[0041] In addition Figure 2In the embodiment of the present invention, the solder mask 40 covers both the first tin layer 30 and the third tin layer 35, but the present disclosure is not intended to be limited thereto. In another embodiment, the solder mask 40 only needs to cover at least the boundary between the first tin layer 30 and the third tin layer 35, but does not cover the boundary between the second tin layer 33 and the third tin layer 35. In another embodiment (not shown in the figure), the solder mask 40 further covers the boundary between the second tin layer 33 and the third tin layer 35.

[0042] Please refer to FIG. 3A to FIG. 3D As shown, it is another embodiment of the flexible circuit substrate 1 disclosed in the present invention. Figure 1 Compared with the first embodiment, the main difference is that the flexible circuit substrate 1 further includes a solder mask layer 45 formed on the solder mask layer 40 and / or the second tin layer 33. The solder mask layer 45 can be made of the same material as or different from the solder mask layer 40.

[0043] Specifically, in Figure 3A In the embodiment, the solder mask 45 only covers a portion of the solder mask 40 but does not cover the second tin layer 33 . This approach can further enhance the bending resistance of the bendable area in the flexible circuit substrate 1 by protecting a small portion of the solder mask 45 .

[0044] Selectively, in Figure 3B In the embodiment of the present invention, the solder mask 45 covers the entire solder mask 40 and also covers a portion of the second tin layer 33. This approach not only strengthens the above Figure 3A The advantages of the embodiment are achieved, and since all the solder mask layer 40 is covered, it is also possible to prevent the solder mask layer 40 from being peeled off from the first tin layer 30 in subsequent processes.

[0045] Selectively, in Figure 3C In the embodiment of Figure 3B The solder mask 45 only covers part (not all) of the solder mask 40, but also covers part of the second tin layer 33, and specifically covers the boundary between the solder mask 40 and the second tin layer 33. This method can not only prevent the solder mask 40 at the edge from being peeled off from the first tin layer 30 in the subsequent process, but also prevent the solder mask 45 from having too much solder mask 45 on the solder mask 40, which would cause difficulty in bending the flexible circuit substrate 1 due to excessive thickness.

[0046] Selectively, in Figure 3D In the embodiment, a portion of the solder mask 45 is as Figure 3C The solder mask layer 45 covers the boundary between the solder mask layer 40 and the second tin layer 33, and the other part of the solder mask layer 45 is similar to Figure 3A Only part of the solder mask 40 is covered, but the second tin layer 33 is not covered. This approach is a combination of Figure 3A and Figure 3C Advantages.

[0047] In addition, in an embodiment not shown in the figure, the solder mask 45 only covers a portion of the second tin layer 33 but does not cover the solder mask 40 . The solder mask 45 may maintain a gap with the solder mask 40 , but may also be adjacent to the solder mask 40 .

[0048] In another embodiment not shown, the area of ​​the solder mask layer 45 on the flexible circuit substrate 1 accounts for more than 10% of the area of ​​the solder mask layer 40 on the flexible circuit substrate 1. However, the present disclosure is not intended to be limited to this.

[0049] In addition, it is noted that FIG. 3A to FIG. 3D The various embodiments of the solder mask 40 and the solder mask 45 shown in FIG. Figure 2 An embodiment of the present invention (that is, a case where the third area A3 is used as a buffer area).

[0050] Please refer to Figure 4 As shown, it is another embodiment of the flexible circuit substrate 1 disclosed in the present invention. Figure 1 The first embodiment shown and Figure 2 Compared with the second embodiment shown, the main difference is that the conductive copper layer 20 with the wiring pattern further has a fourth area A4, so that the first area A1 and the third area A3 are both located between the fourth area A4 and the second area A2. The conductive copper layer 20 located in the fourth area A4 is electrically connected to the conductive copper layer 20 located in the first area A1, the conductive copper layer 20 located in the third area A3, and the conductive copper layer 20 located in the second area A2. Preferably, the conductive copper layer 20 located in the fourth area A4 belongs to the same circuit as the conductive copper layer 20 located in the first area A1, the conductive copper layer 20 located in the third area A3, and the conductive copper layer 20 located in the second area A2. It should also be noted that in other embodiments, it may also be omitted. Figure 4 The third area A3 is not limited to Figure 4 Example shown.

[0051] Further Figure 4 As shown, compared with the conductive copper layer 20 in the first area A1, the second area A2, and the third area A3, which all have a tin layer on top, the conductive copper layer 20 in the fourth area A4 does not have a tin layer on top, but is directly covered with a solder mask 48. At the same time, the thickness T5 of the conductive copper layer 20 in the fourth area A4 is also greater than the thickness of the conductive copper layer 20 in the first area A1, the second area A2, and the third area A3. In addition, the surface of the conductive copper layer 20 in the fourth area A4 is preferably coplanar with the surfaces of the first tin layer 30, the third tin layer 35, and the second tin layer 33.

[0052] Preferably, the fourth area A4 of the conductive copper layer 20 is located in the bendable area of ​​the flexible circuit substrate 1. The range of the fourth area A4 may be larger or smaller than the bendable area of ​​the flexible circuit substrate 1. Preferably, the fourth area A4 covers the portion that is subjected to the maximum stress when the flexible circuit substrate 1 is bent. Although the solder mask 48 is not as protective as the tin layer for the conductive copper layer 20, on the other hand, in the case where there is no tin layer above the fourth area A4 (and a thin tin layer above the first area A1), the bendability and flexibility of the flexible circuit substrate 1 can be increased (that is, the flexible circuit substrate 1 is easier to be bent), so the flexible circuit substrate 1 can be applied to a smaller space, and the greater thickness T5 (and thickness T3) of the conductive copper layer 20 also increases the bending resistance of the circuit pattern in the bendable area, thereby avoiding the circuit breakage caused by the bending of the flexible circuit substrate 1.

[0053] In one embodiment, the solder mask 48 can also be used as a mask to form the first tin layer 30, so the solder mask 48 only covers the conductive copper layer 20 of the fourth area A4, but does not cover the first tin layer 30. However, the present disclosure is not intended to be limited to this. In addition, the solder mask 48 can be made of the same or different materials as the solder mask 40.

[0054] Figure 5 The electronic device 100 of the embodiment of the present disclosure includes a flexible circuit substrate 1 and a chip 2 disposed on the flexible circuit substrate 1. For details of the flexible circuit substrate 1, please refer to the above-mentioned Figures 1 to 4 The electronic device 100 may be, for example, a flat panel display, a wearable device, a mobile phone, a tablet computer, a notebook computer, a car panel, or an industrial control panel, and the chip 2 may be, for example, a chip for driving an image display. Figure 5 As shown, due to the small space in the electronic device 100, the flexible circuit substrate 1 must be bent during use. This part should be known to those skilled in the art and will not be described in detail here. In addition, in an embodiment not shown, the electronic device 100 does not need to be a finished product that can be used immediately by the end consumer, and as long as the chip 2 is already set on the flexible circuit substrate 1, the electronic device 100 can also be a semi-finished product that needs to be processed later.

[0055] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the scope of the patent application of the present disclosure; any other equivalent changes or modifications that do not deviate from the spirit disclosed in the present disclosure should be included in the scope of the attached patent application.

[0056]

Explanation of symbols

[0057] Flexible circuit board 1

[0058] Wafer 2

[0059] Insulating substrate 10

[0060] Conductive copper layer 20

[0061] First tin layer 30

[0062] Second tin layer 33

[0063] The third tin layer 35

[0064] Solder mask 40

[0065] Solder mask 45

[0066] Solder mask 48

[0067] Electronic device 100

[0068] Zone 1 A1

[0069] Zone 2 A2

[0070] Area 3 A3

[0071] Area 4 A4

[0072] Tin surface S1, S2

[0073] Thickness T1, T2, T3, T4, T5.

Claims

1. A flexible circuit substrate for carrying a chip, comprising: an insulating substrate; A conductive copper layer with a wiring pattern is located on the insulating substrate, and the conductive copper layer has a first region and a second region that are electrically connected to each other; A first tin layer is located above the first region of the conductive copper layer, and the first tin layer has a first tin thickness; A second tin layer is located above the second region of the conductive copper layer, the second tin layer having a second tin thickness; and in, A first tin surface of the first tin layer not bonded to the conductive copper layer and a second tin surface of the second tin layer not bonded to the conductive copper layer belong to the same plane; The first tin thickness is smaller than the second tin thickness.

2. The flexible circuit substrate according to claim 1, wherein: The conductive copper layer also has a third area, which is located between the first area and the second area and is electrically conductive with the first area and the second area. The flexible circuit substrate also has a third tin layer, which is located above the third area of ​​the conductive copper layer and has a third tin thickness between the first tin thickness and the second tin thickness.

3. The flexible circuit substrate according to claim 1, wherein: The conductive copper layer located in the first region has a first copper thickness, and the conductive copper layer located in the second region has a second copper thickness, and the first copper thickness is greater than the second copper thickness.

4. The flexible circuit substrate according to claim 3, wherein: The conductive copper layer also has a third region, and the third region is located between the first region and the second region. The thickness of the conductive copper layer located in the third region is between the first copper thickness and the second copper thickness.

5. The flexible circuit substrate according to claim 3, wherein: The conductive copper layer also has a fourth region. The first region is located between the fourth region and the second region. The fourth region is electrically connected to the first region and the second region. The thickness of the conductive copper layer located in the fourth region is greater than the first copper thickness.

6. The flexible circuit substrate according to claim 5, further comprising: a first solder resist layer at least partially covering the first tin layer; and A second solder resist layer at least partially covers the fourth area of ​​the conductive copper layer, and no tin layer is provided between the fourth area of ​​the conductive copper layer and the second solder resist layer.

7. The flexible circuit substrate according to claim 1, wherein: The first area is located in the bendable area of ​​the flexible circuit substrate.

8. The flexible circuit substrate according to any one of claims 1 to 5 and 7, further comprising a first solder mask layer at least partially covering the first tin layer, wherein: The first solder resist layer does not cover the second tin layer, and the thickness of the first solder resist layer is in the range of 1 to 50 μm. 9 . The flexible circuit substrate according to claim 8 , further comprising a third solder mask layer, at least partially covering the first solder mask layer and / or the second tin layer.

10. A flexible circuit substrate for carrying a chip, comprising: an insulating substrate; A conductive copper layer with a wiring pattern is located on the insulating substrate, the thickness of the conductive copper layer is in the range of 2 to 20 μm, the conductive copper layer has a first area and a second area that are electrically connected to each other, the conductive copper layer located in the first area has a first copper thickness, and the conductive copper layer located in the second area has a second copper thickness, and the first copper thickness is greater than the second copper thickness.

11. The flexible circuit substrate according to claim 10, wherein: The conductive copper layer also has a third region, and the third region is located between the first region and the second region. The thickness of the conductive copper layer located in the third region is between the first copper thickness and the second copper thickness.

12. The flexible circuit substrate according to claim 10, wherein: The conductive copper layer also has a fourth region. The first region is located between the fourth region and the second region. The fourth region is electrically connected to the first region and the second region. The thickness of the conductive copper layer located in the fourth region is greater than the first copper thickness.

13. The flexible circuit substrate according to claim 12, further comprising: a first tin layer located above the first region of the conductive copper layer; a first solder resist layer at least partially covering the first tin layer; and A second solder resist layer at least partially covers the fourth area of ​​the conductive copper layer, and no tin layer is provided between the fourth area of ​​the conductive copper layer and the second solder resist layer.

14. The flexible circuit substrate according to claim 10, further comprising: a first tin layer located above the first region of the conductive copper layer; a second tin layer located above the second region of the conductive copper layer; and A first solder resist layer at least partially covers the first tin layer. 15 . The flexible circuit substrate according to claim 14 , wherein the first tin layer has a first tin thickness, the second tin layer has a second tin thickness, and the first tin thickness is different from the second tin thickness.

16. The flexible circuit substrate according to any one of claims 10 to 15, wherein: The first area is located in the bendable area of ​​the flexible circuit substrate.

17. An electronic device comprising: The flexible circuit substrate according to claim 1 or 10; and A chip is disposed on the flexible circuit substrate.

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