Via hole wiring design method and printed circuit board

Abstract

The invention relates to a via hole wiring design method and a printed circuit board, which can better control via hole impedance on the printed circuit board and meet the requirement of a high-speed link on impedance matching. The via hole wiring design method comprises the steps that a target via hole is found from a printed circuit board, the target via hole is a via hole pair which is connected between two wiring layers with the interval smaller than a preset interval threshold value, and the wiring mode of the two wiring layers is the same-direction wire outgoing mode; increasing the via hole routing spacing of the target via hole in a via hole anti-pad area of a routing layer; and / or reducing the via hole routing spacing of the target via hole in the via hole anti-pad area of the other routing layer; symmetrically arranging two layers of via hole wires of the target via hole in the via hole anti-pad area respectively; and impedance simulation processing is carried out on the printed circuit board, and via hole wiring parameters are further adjusted to realize impedance matching.

Description

Technical Field

[0001] The present application relates to the technical field of circuit boards, and in particular to a via routing design method and a printed circuit board. Background Art

[0002] With the rapid development of the communications industry, the speed of high-speed differential signals is getting higher and higher. For example, in order to achieve a higher speed, the PAM4 (English: 4-Level Pulse Amplitude Modulation; Chinese: Four-Level Pulse Amplitude Modulation) signal mode has emerged. Since the differential signal generally works by taking the difference between the two signal receiving levels, and the PAM4 signal mode takes the difference between multiple levels on the signal, compared with the NRZ (English: Non-Return-to-Zero; Chinese: Non-Return-to-Zero) signal, the PAM4 signal has higher requirements for high-speed links, resulting in more important impedance matching of Via (electrical connection hole, referred to as via) on high-speed differential links; that is, Impedance matching and Return loss are becoming more and more important.

[0003] At present, the via routing on the printed circuit board (PCB) is generally not specially processed, and the via impedance only needs to be controlled within the matching specification range. However, with the increasing transmission rate, impedance matching that only meets the specification requirements cannot achieve better performance, especially in PAM4 high-speed links with poor copper loss. Summary of the invention

[0004] In view of the problem that the via routing method on the existing printed circuit board (Printed Circuit Board, PCB) is difficult to meet the impedance matching requirements of high-speed links such as PAM4; the present application provides a via routing design method and a printed circuit board, which can better control the via impedance on the printed circuit board and meet the impedance matching requirements of high-speed links.

[0005] In order to achieve at least one of the above advantages or other advantages and purposes of the present application, the present application provides a via routing design method, including:

[0006] Find a target via from a printed circuit board, wherein the target via is a via pair connected between two routing layers with a spacing less than a preset spacing threshold and with the routing modes of the two routing layers being the same-direction vias;

[0007] Increase the via routing spacing of the target via in the via anti-pad region of one routing layer; and / or decrease the via routing spacing of the target via in the via anti-pad region of another routing layer;

[0008] Arranging two layers of via routing of the target via symmetrically within the via anti-pad region; and

[0009] By performing impedance simulation on the printed circuit board, the via routing parameters are further adjusted to achieve impedance matching.

[0010] In one embodiment of the present application, the preset spacing threshold is 30 mil.

[0011] In one embodiment of the present application, the step of finding a target via from a printed circuit board comprises the steps of:

[0012] Comparing the distance between any two routing layers in the printed circuit board with the preset spacing threshold in sequence, so as to select two routing layers whose spacing is smaller than the preset spacing threshold as a target routing layer pair; and

[0013] From the via pairs connected to the target routing layer pair, a via pair with outgoing lines in the same direction is screened out to serve as the target via.

[0014] In one embodiment of the present application, the step of increasing the via routing spacing of the target via in the via anti-pad region of a routing layer; and / or decreasing the via routing spacing of the target via in the via anti-pad region of another routing layer comprises the steps of:

[0015] The via-line spacing after the increase is controlled to be between 1.5 and 2.5 times the via-line spacing before the increase; and / or

[0016] The via-line spacing after reduction is controlled to be between 0.3 and 0.7 times of the via-line spacing before reduction.

[0017] In one embodiment of the present application, the increased via routing spacing is equal to twice the differential routing spacing of the corresponding routing layer; the decreased via routing spacing is equal to 0.5 times the differential routing spacing of the corresponding routing layer.

[0018] In one embodiment of the present application, the step of increasing the via routing spacing of the target via in the via anti-pad region of a routing layer; and / or decreasing the via routing spacing of the target via in the via anti-pad region of another routing layer, further includes the steps of:

[0019] While increasing the via routing spacing in a routing layer, increasing the via routing line width of the target via in the via anti-pad area of ​​the corresponding routing layer; and / or

[0020] While reducing the via routing spacing in another routing layer, the via routing line width of the target via in the via anti-pad area of ​​the corresponding routing layer is kept unchanged.

[0021] In one embodiment of the present application, a pair of via routing lines of the target via in the via anti-pad region of each routing layer are parallel to each other.

[0022] In one embodiment of the present application, the step of symmetrically arranging the two layers of via routing of the target via respectively within the via anti-pad region comprises the steps of:

[0023] Taking the perpendicular midline between the P via and the N via in the target via as the axis of symmetry, the two-layer via routing of the target via is symmetrically arranged.

[0024] In one embodiment of the present application, the step of symmetrically arranging the two layers of via routing of the target via respectively within the via anti-pad region further includes the steps of:

[0025] The transitional routing between the via routing after the spacing adjustment and the differential routing in the corresponding routing layer is adaptively adjusted so that the transitional routing extends obliquely from the via routing to the corresponding differential routing.

[0026] According to another aspect of the present application, the present application further provides a printed circuit board, wherein the printed circuit board includes a via routing structure designed by any of the via routing design methods described above.

[0027] According to another aspect of the present application, the present application further provides a printed circuit board, comprising:

[0028] A circuit substrate having a pair of routing layers arranged at intervals and having a spacing less than a preset spacing threshold and a via anti-pad area penetrating the two routing layers; and

[0029] A via routing structure, wherein the via routing structure comprises a pair of vias arranged at intervals within the via anti-pad area and two pairs of via routings respectively connecting the two vias with the differential routings of the two routing layers within the via anti-pad area and extending in the same direction on the two routing layers; wherein the via routing spacing of the via routing structure in one routing layer is greater than the differential routing spacing in the corresponding routing layer; and / or, the via routing spacing of the via routing structure in another routing layer is less than the differential routing spacing in the corresponding routing layer.

[0030] In one embodiment of the present application, the via routing structure further includes a transition routing extending obliquely from the via routing outside the via anti-pad region to the corresponding differential routing for connection.

[0031] In one embodiment of the present application, in a routing layer where the via routing spacing is greater than the differential routing spacing, the via routing line width is greater than the differential routing line width; in a routing layer where the via routing spacing is less than the differential routing spacing, the via routing line width is equal to the differential routing line width.

[0032] In summary, the via routing design method of the present application is aimed at the target vias that are connected to two routing layers with a smaller spacing and have the same direction of routing: increase the via routing spacing of the target via in the via anti-pad area of ​​one routing layer; and / or, reduce the via routing spacing of the target via in the via anti-pad area of ​​another routing layer, so that the distance between the two layers of via routing of the target via in the via anti-pad area of ​​the two routing layers can be increased to reduce the self-coupling electromagnetic effect between the two layers of via routing, which is helpful to achieve the purpose of impedance matching later. In other words, the via routing design method of the present application increases the distance between the two layers of via routing of the target via through the above-mentioned winding method, so that the self-coupling electromagnetic effect between the two layers of via routing can be reduced, which is conducive to the effect of impedance matching after subsequent adjustment through impedance simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of a flow chart of a via routing design method according to an embodiment of the present application;

[0034] Figure 2A A schematic structural diagram of a routing layer for increasing the via routing spacing in the via routing design method according to the above embodiment of the present application is shown;

[0035] Figure 2B A schematic structural diagram of another routing layer for reducing the via routing spacing in the via routing design method according to the above embodiment of the present application is shown;

[0036] Figure 2C A schematic structural diagram of two routing layers stacked in the via routing design method according to the above embodiment of the present application is shown;

[0037] Figure 3 A schematic flow chart of the step of finding a target via in the via routing design method according to the above embodiment of the present application is shown;

[0038] Figure 4 A schematic flow chart of a via routing spacing adjustment step in a via routing design method according to the above embodiment of the present application is shown;

[0039] Figure 5 A schematic flow chart of the via routing symmetrical arrangement step in the via routing design method according to the above embodiment of the present application is shown;

[0040] Fig. 6AA schematic diagram of the structure of a printed circuit board designed according to a general design method of a comparative example of the present application is shown;

[0041] Figure 6B A schematic structural diagram of a printed circuit board designed according to the via routing design method of the above embodiment of the present application is shown;

[0042] Fig. 7A A schematic diagram of an impedance curve obtained by performing impedance simulation on the printed circuit boards of the comparative example and the embodiment is shown;

[0043] Figure 7B A schematic diagram of a return loss curve obtained by performing impedance simulation on the printed circuit boards of the comparative example and the embodiment is shown;

[0044] Figure 8 is a schematic structural diagram of a printed circuit board according to another embodiment of the present application.

[0045] Description of main component symbols:

[0046] 1. Printed circuit board; 10. Circuit substrate; 11. Routing layer; 110. Differential routing; 12. Via anti-pad area; 20. Via routing structure; 21. Via; 22. Via routing; 23. Transition routing.

[0047] The above description of the main component symbols is combined with the accompanying drawings and specific implementation methods to further illustrate the present application in detail. DETAILED DESCRIPTION

[0048] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0049] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0050] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0051] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0052] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0053] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0054] Considering that with the increasing propagation rate, the existing via routing method on the printed circuit board is difficult to meet the high impedance matching requirements of high-speed links such as PAM4. Therefore, the present application creatively provides a via routing design method and a printed circuit board, which can better control the via impedance on the printed circuit board and meet the impedance matching requirements of high-speed links.

[0055] Specifically, according to another aspect of the present application, Figure 1 As shown, an embodiment of the present application provides a via routing design method, which may include the steps of:

[0056] S100: Find a target via from a printed circuit board, wherein the target via is a via pair connected between two routing layers with a spacing less than a preset spacing threshold and with the routing of the two routing layers extending in the same direction;

[0057] S200: increasing the via routing spacing of the target via in the via anti-pad region of a routing layer; and / or decreasing the via routing spacing of the target via in the via anti-pad region of another routing layer;

[0058] S300: symmetrically arranging two layers of via routing of the target via in the via anti-pad area; and

[0059] S400: By performing impedance simulation processing on the printed circuit board, the via routing parameters are further adjusted to achieve impedance matching.

[0060] More specifically, the preset spacing threshold mentioned in the present application can be implemented as 30 mil (mil, milli-inch) but is not limited to. In other words, the distance between the two routing layers connected to the target via is preferably less than 30 mil, and the target via is connected in the same direction between the two routing layers.

[0061] It is worth noting that, as the distance between the two routing layers is smaller, the distance between the two layers of via routing in the via anti-pad area of ​​the two routing layers with the target vias extending in the same direction is smaller, the self-coupling electromagnetic effect generated is greater, and the impact on impedance matching is greater; therefore, the via routing design method of the present application is aimed at the target vias connected to two routing layers with a spacing of less than 30 mils and extending in the same direction: Figure 2A As shown, the via trace spacing of the target via in the via anti-pad area of ​​a trace layer is increased; and / or, as shown Figure 2B As shown in the figure, reduce the via trace spacing of the target via in the via anti-pad area of ​​another trace layer. Figure 2C As shown, the distance between the two layers of via routing in the via anti-pad area of ​​the two routing layers of the target via is increased to reduce the self-coupling electromagnetic effect between the two layers of via routing, which is helpful to achieve the purpose of impedance matching later. In other words, the via routing design method of the present application increases the distance between the two layers of via routing of the target via through the above-mentioned winding method, so that the self-coupling electromagnetic effect between the two layers of via routing is reduced, which is conducive to the effect of impedance matching after subsequent adjustment through impedance simulation.

[0062] In addition, if FIG. 2A to FIG. 2CAs shown, each target via is generally composed of P vias and N vias arranged at intervals in the corresponding via anti-pad region, and the via routing of each target via in each routing layer generally includes a P line connected to the P via and an N line connected to the N via. It is understandable that the via routing spacing mentioned in this application refers to the distance between the P line and the N line of the target via in the via anti-pad region of each routing layer.

[0063] For example, Figure 3 As shown, step S100 of the via routing design method of the present application may include the following steps:

[0064] S110: sequentially comparing the distance between any two routing layers in the printed circuit board with the preset spacing threshold, so as to select two routing layers whose spacing is smaller than the preset spacing threshold as a target routing layer pair; and

[0065] S120: From the via pairs connected to the target routing layer pair, select via pairs with outgoing lines in the same direction as the target vias.

[0066] Alternatively, if Figure 4 As shown, step S200 of the via routing design method of the present application includes the steps of:

[0067] S210: Control the via-line spacing after the increase to be between 1.5 times and 2.5 times the via-line spacing before the increase; and / or

[0068] S220: Control the via-line spacing after reduction to be between 0.3 and 0.7 times of the via-line spacing before reduction.

[0069] It is worth noting that the spacing of the via routing mentioned in the present application before being enlarged is usually equal to the spacing of the via routing before being reduced, and is equal to the differential routing spacing of the corresponding routing layer outside the via anti-pad area; that is, the spacing of the via routing mentioned in the present application before being enlarged and before being reduced is equal to the distance between the P line and the N line of the corresponding routing layer in the reference area.

[0070] Preferably, in step S210: the increased via routing spacing is equal to 2 times the differential routing spacing of the corresponding routing layer. In addition, in step S220: the decreased via routing spacing is equal to 0.5 times the differential routing spacing of the corresponding routing layer.

[0071] Alternatively, if Figure 4 As shown, step S200 of the via routing design method of the present application further includes the steps of:

[0072] S230: while increasing the via routing spacing in a routing layer, increasing the via routing line width of the target via in the via anti-pad area of ​​the corresponding routing layer; and / or

[0073] S240: While reducing the via routing spacing in another routing layer, the via routing line width of the target via in the via anti-pad area of ​​the corresponding routing layer is maintained unchanged.

[0074] It is worth noting that since the self-coupling electromagnetic effect between vias with larger spacing becomes worse, resulting in larger impedance, the via routing design method of the present application reduces routing impedance by increasing the via routing line width, which is conducive to ensuring impedance matching. It is understandable that when the via routing spacing becomes smaller, the via routing design method of the present application keeps the corresponding via routing line width unchanged, because increasing the line width at this time easily causes the via routing with smaller spacing to be too close together, making it difficult to process and prone to short circuit problems.

[0075] In addition, if Figure 2C As shown, in step S200 of the via routing design method of the present application: a pair of via routings of the target via in the via anti-pad area of ​​each routing layer can be parallel to each other so as to maximize or minimize the via routing spacing of the target via in the via anti-pad area of ​​the corresponding routing layer, so that the distance between the two layers of via routings of the target via in the via anti-pad area of ​​the two routing layers is increased as much as possible.

[0076] Alternatively, if Figure 5 As shown, step S300 of the via routing design method of the present application includes the steps of:

[0077] S310: Taking the perpendicular midline between the P via and the N via in the target via as the axis of symmetry, symmetrically arrange the two layers of via routing of the target via.

[0078] In this way, the via routing design method of the present application can symmetrically arrange the two layers of via routing of the target via so that the two layers of via routing will not be staggered and overlapped within the via anti-pad area, so as to ensure that the distance between the two layers of via routing is as large as possible, so as to better reduce the self-coupling electromagnetic effect between the two layers of via routing. It can be understood that, if Figure 2C As shown, the median vertical line mentioned in the present application refers to a straight line that is perpendicular to the center line between the P via and the N via and passes through the center position of the center line, so that the P line and N line of the target via in each routing layer are symmetrically distributed relative to the median vertical line to maximize the distance between the via routings of the two layers.

[0079] Alternatively, if Figure 5 As shown, step S300 of the via routing design method of the present application further includes the steps of:

[0080] S320: Adaptively adjust the transition routing between the via routing after the spacing adjustment and the differential routing in the corresponding routing layer, so that the transition routing extends obliquely from the via routing to the corresponding differential routing.

[0081] In this way, the transition routing mentioned in the present application can meet the requirements of the processing technology to better connect the via routing and the differential routing within the process range. It can be understood that the transition routing mentioned in the present application is located outside the via anti-pad area of ​​the routing layer, such as Figure 2C The trace portion within the red frame shown is used to electrically connect the via trace with the corresponding differential trace.

[0082] Finally, the via routing design method of the present application is adjusted in more detail through 3D impedance simulation to obtain an optimized printed circuit board to achieve better impedance matching. Fig. 6A The printed circuit board designed by the general design method shown in FIG. 1 (hereinafter referred to as the printed circuit board before optimization, as a comparative example) and the printed circuit board shown in FIG. Figure 6B The printed circuit board designed by the via routing design method of the present application (hereinafter referred to as the optimized printed circuit board, as an embodiment) is subjected to impedance simulation, and the impedance and return loss can be read by extracting the S parameter model through passive simulation to obtain the following: Fig. 7A The impedance curve shown and Figure 7B The return loss curve is shown in Fig. 7A and Figure 7B The green curve in the figure is the impedance curve and return loss curve of the printed circuit board before optimization. Fig. 7A and Figure 7B The blue curve in the figure is the impedance curve and return loss curve of the optimized printed circuit board. Fig. 7A and Figure 7B It is easy to see from the impedance curve and return loss curve shown that the printed circuit board designed by the via routing design method of the present application can achieve a better impedance matching effect.

[0083] It is worth mentioning that, according to another aspect of the present application, another embodiment of the present application further provides a printed circuit board. Specifically, Figure 8As shown, the printed circuit board 1 may include a circuit substrate 10 and a via routing structure 20. The circuit substrate 10 has a pair of routing layers 11 arranged at intervals and with a spacing less than a preset spacing threshold, and a via anti-pad area 12 that penetrates the two routing layers 11. The via routing structure 20 includes a pair of vias 21 that are arranged at intervals within the via anti-pad area 12, and two pairs of via routing lines 22 that connect the two vias 21 with the differential routing lines 110 of the two routing layers 11 in the via anti-pad area 12 and are routed in the same direction in the two routing layers 11; wherein the via routing spacing of the via routing structure 20 in one routing layer 11 is greater than the differential routing spacing in the corresponding routing layer 11; and / or, the via routing spacing of the via routing structure 20 in another routing layer 11 is less than the differential routing spacing in the corresponding routing layer 11.

[0084] It is worth noting that, in an example of the present application, the via routing structure 20 further includes a transition routing 23 extending obliquely from the via routing 22 outside the via anti-pad area 12 to the corresponding differential routing 110 for connection.

[0085] Optionally, in a routing layer 11 where the via routing spacing is greater than the differential routing spacing, the via routing line width is greater than the differential routing line width; in a routing layer 11 where the via routing spacing is less than the differential routing spacing, the via routing line width is equal to the differential routing line width. In other words, via routing lines 22 with larger spacing are thickened to reduce the impedance of the via routing lines 22, facilitating subsequent impedance matching; via routing lines 22 with smaller spacing are not thickened to keep the original line width unchanged.

[0086] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A via routing design method, characterized in that: Includes steps: Find a target via from a printed circuit board, wherein the target via is a via pair connected between two routing layers with a spacing less than a preset spacing threshold and with the routing modes of the two routing layers being the same-direction vias; Increase the via trace spacing of the target via in the via anti-pad area of ​​a trace layer; and / or, reducing the via trace spacing of the target via in the via anti-pad area of ​​another trace layer; Arranging two layers of via routing of the target via symmetrically within the via anti-pad region; and By performing impedance simulation on the printed circuit board, the via routing parameters are further adjusted to achieve impedance matching.

2. The via routing design method according to claim 1, characterized in that: The preset spacing threshold is 30 mil.

3. The via routing design method according to claim 1, characterized in that: The step of finding a target via hole from a printed circuit board comprises the steps of: Comparing the distance between any two routing layers in the printed circuit board with the preset spacing threshold in sequence, so as to select two routing layers whose spacing is smaller than the preset spacing threshold as a target routing layer pair; and From the via pairs connected to the target routing layer pair, a via pair with outgoing lines in the same direction is screened out to serve as the target via.

4. The via routing design method according to any one of claims 1 to 3, characterized in that: The step of increasing the via routing spacing of the target via in the via anti-pad region of a routing layer; and / or decreasing the via routing spacing of the target via in the via anti-pad region of another routing layer, comprises the steps of: The via-line spacing after the increase is controlled to be between 1.5 and 2.5 times the via-line spacing before the increase; and / or The via-line spacing after reduction is controlled to be between 0.3 and 0.7 times of the via-line spacing before reduction.

5. The via routing design method according to claim 4, characterized in that: The increased via-to-wire spacing is equal to twice the differential routing spacing of the corresponding routing layer; the decreased via-to-wire spacing is equal to 0.5 times the differential routing spacing of the corresponding routing layer.

6. The via routing design method according to claim 4, characterized in that: The step of increasing the via routing spacing of the target via in the via anti-pad region of a routing layer; and / or decreasing the via routing spacing of the target via in the via anti-pad region of another routing layer, further comprises the steps of: While increasing the via routing spacing in a routing layer, increase the via routing line width of the target via in the via anti-pad area of ​​the corresponding routing layer; and / or While reducing the via routing spacing in another routing layer, keep the via routing line width of the target via in the via anti-pad area of ​​the corresponding routing layer unchanged.

7. The via routing design method according to any one of claims 1 to 3, characterized in that: A pair of via routing lines of the target via in the via anti-pad region of each routing layer are parallel to each other.

8. The via routing design method according to any one of claims 1 to 3, characterized in that: The step of symmetrically arranging the two layers of via routing of the target via hole within the via anti-pad region comprises the steps of: Taking the perpendicular midline between the P via and the N via in the target via as the axis of symmetry, the two-layer via routing of the target via is symmetrically arranged.

9. The via routing design method according to claim 8, characterized in that: The step of symmetrically arranging the two layers of via routing of the target via hole in the via anti-pad area also includes the steps of: The transitional routing between the via routing after the spacing adjustment and the differential routing in the corresponding routing layer is adaptively adjusted so that the transitional routing extends obliquely from the via routing to the corresponding differential routing.

10. A printed circuit board, characterized in that The printed circuit board includes a via-line structure designed by the via-line design method as claimed in any one of claims 1 to 9.

11. A printed circuit board, characterized in that include: A circuit substrate having a pair of routing layers arranged at intervals and having a spacing less than a preset spacing threshold and a via anti-pad area penetrating the two routing layers; and A via routing structure, wherein the via routing structure comprises a pair of vias arranged at intervals within the via anti-pad region and two pairs of via routing lines respectively connecting the two vias with differential routing lines of the two routing layers within the via anti-pad region and extending in the same direction on the two routing layers; The via routing structure has a via routing spacing in one routing layer that is greater than the differential routing spacing in the corresponding routing layer; and / or the via routing structure has a via routing spacing in another routing layer that is less than the differential routing spacing in the corresponding routing layer.

12. The printed circuit board according to claim 11, characterized in that: The via routing structure also includes a transition routing extending obliquely from the via routing to the corresponding differential routing outside the via anti-pad region for connection.

13. The printed circuit board according to claim 11 or 12, characterized in that: In the routing layer where the via routing spacing is greater than the differential routing spacing, the via routing line width is greater than the differential routing line width; in the routing layer where the via routing spacing is less than the differential routing spacing, the via routing line width is equal to the differential routing line width.

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