TEM sample preparation method
By pre-grounding the adjacent pattern in the target layer on the chip sample and determining the target position using the bright contrast pattern characteristics, the problems of low positioning accuracy and low efficiency during FIB sample preparation in the prior art are solved, and higher positioning accuracy and sample preparation efficiency are achieved.
Patent Information
- Application Number
- CN202510008267.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-05-06
AI Technical Summary
After the chip production process is reduced, the key size and spacing of metal patterns are reduced, resulting in the linear markings easily affecting multiple structures during FIB sample preparation, making it difficult to clarify the target position, and making samples is time-consuming and efficient.
By delaminating the chip sample, the adjacent pattern adjacent to the target position in the target layer is grounded in advance, and the bright contrast pattern features are generated using the grounded adjacent pattern, and the target position is determined through the bright contrast pattern during the FIB cutting process.
The positioning accuracy of the target position and the success rate of TEM sample preparation are improved, the time and steps required for sample preparation are reduced, and the efficiency is improved.
Smart Images
Figure CN119936084A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a semiconductor integrated circuit manufacturing method, in particular to a TEM sample preparation method. Background Art
[0002] In the process of chip failure analysis, transmission electron microscopy (TEM) is an extremely important method for observing the physical properties of samples. TEM samples are prepared by focused ion beam (FIB). As the chip manufacturing process shrinks, the critical dimension (CD) of metal patterns and the spacing (space) between metals decrease, and the challenge of FIB sample preparation is becoming greater and greater. The existing method generally uses FIB to make linear marks before the target layer, so that when this mark is found during the FIB sample preparation process, combined with the layout, the specific location of the target structure can be known.
[0003] However, this existing method has the following disadvantages:
[0004] 1. In advanced processes, the CD of metal and the space between metals are relatively small, and linear markings are likely to affect more structures, making it impossible to clearly identify the target location. Figure 1 As shown, it is a photograph of the FIB mark formed during the existing TEM sample preparation; it can be seen that there are multiple metal patterns, i.e., metal lines, on the chip sample 101. In order to mark the target position with defects, the existing method is to use FIB mark 102. FIB mark 102 is a linear mark formed by FIB cutting. It can be seen that when the CD and the spacing of the metal lines are relatively small, since the width of the FIB cutting will remain at a certain value, the width of the FIB mark 102 will be the sum of the CD and spacing of multiple metal lines, so it will affect more structures, and finally make it impossible to clearly identify the target position.
[0005] 2. Linear markings also need to be combined with the layout, making sample preparation time-consuming and inefficient. Summary of the invention
[0006] The technical problem to be solved by the present invention is to provide a TEM sample preparation method, which can improve the success rate and efficiency of TEM sample preparation.
[0007] In order to solve the above technical problems, the TEM sample preparation method provided by the present invention comprises the following steps:
[0008] Step 1: Delayer the chip sample to expose the target layer to be analyzed.
[0009] Step 2: grounding the adjacent graphics in the target layer, wherein the adjacent graphics are graphics adjacent to the target position.
[0010] Step three, performing FIB cutting on the chip sample to form a TEM sample; during the FIB cutting process, when a bright voltage contrast (BVC) pattern is found, the bright voltage contrast pattern is the adjacent pattern, and the target position is determined by the adjacent pattern.
[0011] A further improvement is that the target layer is a metal layer, and the patterns in the target layer are metal lines.
[0012] A further improvement is that in step 2, the grounding structure of the adjacent pattern is realized by FIB cutting and metal deposition methods.
[0013] A further improvement is that in step 2, after the ground structure of the adjacent pattern is formed, the step further includes:
[0014] Secondary electron imaging was performed to confirm the bright contrast pattern of the adjacent pattern.
[0015] A further improvement is that the secondary electron imaging is achieved by FIB or SEM.
[0016] A further improvement is that in step 2, after confirming that the bright contrast pattern of the adjacent pattern is normal, the method further includes:
[0017] A first insulating layer is formed, wherein the area covered by the first insulating layer includes the target position and the surface of the adjacent pattern in the adjacent area of the target position, and the first insulating layer is used to ensure that only the adjacent pattern that is grounded will present a bright contrast pattern in the subsequent FIB cutting.
[0018] A further improvement is that the critical dimension of the graphics of the target layer is smaller than the width of the FIB cutting line, and the spacing between the graphics of the target layer is smaller than the width of the FIB cutting line.
[0019] A further improvement is that the number of graphics spaced apart between the adjacent graphics and the target graphics corresponding to the target position is greater than or equal to 0 and less than 10.
[0020] The present invention performs de-layering on chip samples and then grounds adjacent graphics adjacent to the target position in the target layer in advance. The grounded adjacent graphics generate characteristics of bright contrast graphics. In the process of FIB cutting to form TEM samples, the bright contrast graphics are used to determine the adjacent graphics, and the target position is determined according to the determined adjacent graphics. The size of the bright contrast graphics of the adjacent graphics directly corresponds to the key size of a graphic, so that the target position can be accurately positioned. When the linear mark formed by FIB cutting is used to locate the target position in the existing method, the positioning accuracy of the target position is low because the linear mark easily affects more graphic structures. Therefore, the present invention can improve the positioning accuracy of the target position, thereby improving the success rate of TEM sample preparation.
[0021] In addition, in the process of forming TEM samples by FIB cutting of the present invention, after a bright contrast pattern is found, the target position is directly determined without combining the layout to determine the target position, so the present invention can also improve the efficiency of TEM sample preparation. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0023] Figure 1 This is a photo of the FIB mark formed during the existing TEM sample preparation;
[0024] Figure 2 Flow chart of the TEM sample preparation method according to an embodiment of the present invention;
[0025] Figure 3A-Figure 6B Schematic diagram of the structure of the chip sample in each step of the TEM sample preparation method according to an embodiment of the present invention;
[0026] Figure 7A-7C The TEM sample preparation method according to an embodiment of the present invention is applied to photographs of various steps in the TEM sample preparation process of a chip sample of a specific process. DETAILED DESCRIPTION
[0027] like Figure 2 As shown, the flow chart of the TEM sample preparation method according to the embodiment of the present invention; FIG. 3A to FIG. 6B As shown, a schematic diagram of the structure of the chip sample 201 in each step of the TEM sample preparation method according to an embodiment of the present invention; the TEM sample preparation method according to an embodiment of the present invention comprises the following steps:
[0028] Step 1: Figure 3A As shown, the chip sample 201 is subjected to a de-layering process to expose the target layer to be analyzed.
[0029] In the embodiment of the present invention, the target layer is a metal layer, and the pattern in the target layer is a metal line. Figure 3AIn FIG. 1 , the graphics corresponding to the target layer are marked with a marker 203. Figure 3A The bottom metal line 202 of the target layer is also shown. In the target layer, the target pattern corresponding to the target position is marked with a mark 203a.
[0030] Figure 3A is a top view, Figure 3B For the corresponding cross-sectional view, please refer to Figure 3B shown.
[0031] In some embodiments, the critical dimension of the target layer pattern is smaller than the width of the FIB cutting line, and the spacing between the target layer patterns is smaller than the width of the FIB cutting line. For example, the critical dimension and spacing of the second metal layer (M2) and the first metal layer (M1) are relatively small, which is not conducive to using the linear mark formed by the FIB cutting line to mark the target position.
[0032] Step 2: Figure 4A As shown, the adjacent pattern 203b in the target layer is grounded, and the adjacent pattern 203b is a pattern adjacent to the target position. Figure 4A is a top view, Figure 4B The corresponding cross-sectional view.
[0033] In the embodiment of the present invention, the grounding structure adjacent to the pattern 203 b is realized by FIB cutting and metal deposition methods.
[0034] After the ground structure adjacent to the pattern 203b is formed, the method further includes:
[0035] Secondary electron imaging is performed to confirm the bright contrast pattern of the adjacent pattern 203b. In some embodiments, secondary electron imaging is achieved by FIB or SEM. By confirming the bright contrast pattern of the adjacent pattern 203b, it is ensured that the bright contrast pattern can be found in the subsequent FIB cutting. On the contrary, if the bright contrast pattern of the adjacent pattern 203b cannot be displayed normally, it is necessary to reselect a grounding wire of the adjacent pattern 203b until the bright contrast pattern of the adjacent pattern 203b is confirmed to be correct.
[0036] In the embodiment of the present invention, the number of graphics spaced apart between the neighboring graphic 203 b and the target graphic corresponding to the target position is greater than or equal to 0 and less than 10. Figure 4A In the example, the number of graphics spaced between the adjacent graphics 203b and the target graphics 203a is 0. In other embodiments, the number of graphics spaced between the adjacent graphics 203b and the target graphics 203a can be a single digit, as long as the target graphics 203a can be found through the adjacent graphics 203b.
[0037] In the embodiment of the present invention, after confirming that the bright contrast pattern adjacent to the pattern 203b is normal, the method further includes:
[0038] like Figure 5 As shown, a first insulating layer 204 is formed, and the area covered by the first insulating layer 204 includes the target position and the surface of the adjacent pattern 203b in the adjacent area of the target position. The first insulating layer 204 is used to ensure that only the grounded adjacent pattern 203b will present a bright contrast pattern in the subsequent FIB cutting.
[0039] Step 3: FIB cutting is performed on the chip sample 201 to form a TEM sample; during the FIB cutting process, when a bright contrast pattern is found, the bright contrast pattern is the adjacent pattern 203b, and the target position is determined by the adjacent pattern 203b.
[0040] like Fig. 6A As shown, in the process of FIB cutting to form a TEM sample, the adjacent pattern 203b will be found first, which is obtained based on the bright contrast pattern.
[0041] like Figure 6B As shown, since the positional relationship between the adjacent pattern 203b and the target pattern 203a is determined, the FIB cutting is continued, and the target pattern 203a can be obtained according to the positional relationship between the adjacent pattern 203b and the target pattern 203a.
[0042] According to the embodiment of the present invention, after de-layering the chip sample 201, the adjacent graphic 203b adjacent to the target position in the target layer is grounded in advance, and the grounded adjacent graphic 203b is used to generate the characteristics of the bright contrast graphic. In the process of FIB cutting to form a TEM sample, the adjacent graphic 203b is determined by the bright contrast graphic, and the target position is determined according to the determined adjacent graphic 203b. The size of the bright contrast graphic of the adjacent graphic 203b directly corresponds to the key size of a graphic, so that the target position can be accurately positioned. However, when the linear mark formed by FIB cutting is used to locate the target position in the existing method, the positioning accuracy of the target position is low because the linear mark easily affects more graphic structures. Therefore, the embodiment of the present invention can improve the positioning accuracy of the target position, thereby improving the success rate of TEM sample preparation.
[0043] In addition, in the process of forming TEM samples by FIB cutting according to the embodiment of the present invention, after a bright contrast pattern is found, the target position is directly determined without combining the layout to determine the target position. Therefore, the embodiment of the present invention can also improve the efficiency of TEM sample preparation.
[0044] like 7A to 7C As shown, the TEM sample preparation method according to the embodiment of the present invention is applied to the photographs of each step of the TEM sample preparation process of a chip sample of a specific process; Fig. 7AAs shown, the chip sample 201' has been delayed to the M2 barrier layer, and the target layer pattern 203' is the metal line of the M2 barrier.
[0045] The commonly used TEM sample preparation method is to use FIB to make linear marks and combine them with the layout to locate the specific position of the target structure. As the chip process is reduced, the CD of the metal and the space between the metals are reduced. When using the existing technology to prepare samples, it is very easy to cut through the failure position of the sample, causing the FIB sample preparation to fail.
[0046] In the method of the embodiment of the present invention, Figure 7B As shown, the metal adjacent to the target position, that is, the adjacent pattern 203b' is grounded through FIB, and the adjacent pattern 203b' will generate BVC. The target pattern 203a is positioned by the adjacent pattern 203b, which can improve the success rate of TEM sample preparation.
[0047] Figure 7B is a photo of the surface morphology of the chip sample 201'. Figure 7C As shown, Figure 7B Corresponding cross-sectional morphology photographs.
[0048] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A TEM sample preparation method, characterized in that: The steps include: Step 1: De-layering the chip sample to expose the target layer to be analyzed; Step 2: grounding the adjacent graphics in the target layer, wherein the adjacent graphics are graphics adjacent to the target position; Step 3, performing FIB cutting on the chip sample to form a TEM sample; During the FIB cutting process, when a bright contrast pattern is found, the bright contrast pattern is the adjacent pattern, and the target position is determined by the adjacent pattern.
2. The TEM sample preparation method according to claim 1, wherein: The target layer is a metal layer, and the patterns in the target layer are metal lines.
3. The TEM sample preparation method according to claim 2, characterized in that: In step 2, the grounding structure of the adjacent pattern is realized by FIB cutting and metal deposition.
4. The TEM sample preparation method according to claim 3, characterized in that: In step 2, after the ground structure of the adjacent pattern is formed, the method further includes: Secondary electron imaging was performed to confirm the bright contrast pattern of the adjacent pattern.
5. The TEM sample preparation method according to claim 4, characterized in that: The secondary electron imaging is achieved by FIB or SEM.
6. The TEM sample preparation method according to claim 4, characterized in that: In step 2, after confirming that the bright contrast pattern of the adjacent pattern is normal, the step further includes: A first insulating layer is formed, wherein the area covered by the first insulating layer includes the target position and the surface of the adjacent pattern in the adjacent area of the target position, and the first insulating layer is used to ensure that only the adjacent pattern that is grounded will present a bright contrast pattern in the subsequent FIB cutting.
7. The TEM sample preparation method according to claim 1, characterized in that: The critical dimension of the pattern of the target layer is smaller than the width of the FIB cutting line, and the spacing between the patterns of the target layer is smaller than the width of the FIB cutting line.
8. The TEM sample preparation method according to claim 1, characterized in that: The number of graphics spaced apart between the adjacent graphics and the target graphics corresponding to the target position is greater than or equal to 0 and less than 10.