Multi-chip IGBT module chip open circuit failure monitoring method and system

Abstract

The invention relates to the technical field of IGBT module monitoring, and particularly discloses a multi-chip IGBT module chip open circuit failure monitoring method and system.The method comprises the steps that firstly, health sensitive parameters for monitoring multi-chip IGBT module chip open circuit failure are determined, then health sensitive parameter values of a multi-chip IGBT module are measured and converted into analog voltage signals VPG, and the analog voltage signals VPG are converted into analog voltage signals VPG; then determining a failure threshold value VREF3 of an analog voltage signal VPG for judging that the multi-chip IGBT module has the chip open-circuit failure, and finally comparing the actually measured analog voltage signal VPG with the failure threshold value VREF3 to judge whether the multi-chip IGBT module has the chip open-circuit failure or not. Under the condition that the packaging of the multi-chip IGBT module is not unsealed, the chip open-circuit failure monitoring of the multi-chip IGBT module is realized, only the grid voltage signal needs to be acquired, the influence factors are few, the measurement is easy, the non-invasive property is realized, the chip open-circuit failure in-situ monitoring of the multi-chip IGBT module can be realized, and the chip open-circuit failure in-situ monitoring device can be used in a plug-and-play manner or can be integrated in a driving circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of IGBT module monitoring, and in particular to a method and system for monitoring chip open circuit failure of a multi-chip IGBT module. Background Art

[0002] Insulated gate bipolar transistor (IGBT) modules have been widely used in industrial fields such as rail transportation, electric vehicles, and renewable energy generation. In high-power power electronic converters, in order to improve the current-carrying capacity of the power module, a multi-chip IGBT module consisting of multiple IGBT and diode chips in parallel is usually used. Safety and long-term reliability have always been important concerns in the design of power electronic converters. However, a survey shows that the IGBT module is the component with the highest probability of failure in power electronic converters. Among them, bond wire failure is the main failure mode of IGBT modules. For multi-chip IGBT modules, due to differences in chip characteristics and package layout, the bond wires on the chip with greater electrothermal stress fail first, and accelerate the failure of the remaining bond wires on the chip, eventually leading to chip open circuit failure. Therefore, introducing condition monitoring technology to identify chip open circuit failures of multi-chip IGBT modules has become an economical and effective way to improve the reliability of high-power power electronic converters.

[0003] There have been many studies on the monitoring of chip open circuit failure status in multi-chip IGBT modules. The existing methods can be divided into sensor method and health sensitive parameter method. The sensor method requires the installation of additional sensors inside the module, which significantly increases the monitoring cost and device operation risk; while the health sensitive parameter method is widely used due to its fast response speed and low invasiveness. According to the different influencing mechanisms of bond wire failure, the health sensitive parameter method can be further divided into: resistance-inductance-based monitoring method and capacitance-based monitoring method. Although the resistance-inductance-based monitoring method can identify chip open circuit failure, its discrimination is small and it is easily disturbed by the failure of some bond wires. In contrast, the capacitance-based monitoring method can avoid the interference of partial bond wire failure and has a high discrimination, becoming the most potential chip open circuit failure monitoring method.

[0004] At present, the main monitoring methods based on capacitance are: opening delay time t don , turn-off delay time t doff , front threshold voltage V GE(pre-th) , gate charge Q G , crosstalk voltage V GEB , Turn-off voltage change rate dV CE / dt, gate voltage fall time t gfHowever, the above methods have many disadvantages, such as many influencing factors, high invasiveness, susceptibility to power circuit interference, and measurement difficulties, which are not conducive to the in-situ monitoring of chip open circuit failures in multi-chip IGBT modules. Summary of the invention

[0005] The present invention provides a multi-chip IGBT module chip open circuit failure monitoring method and system, which solves the technical problem that the existing multi-chip IGBT module chip open circuit failure monitoring method has many influencing factors, high invasiveness, susceptibility to interference, low discrimination and difficulty in measurement.

[0006] In order to solve the above technical problems, the present invention provides a method for monitoring chip open circuit failure of a multi-chip IGBT module, comprising the steps of:

[0007] Determine a health sensitive parameter for monitoring chip open circuit failure of a multi-chip IGBT module, where the health sensitive parameter is related to the number n of effective chip branches in the multi-chip IGBT module and is at least not affected by bus voltage and load current;

[0008] Measure the health sensitive parameter values ​​of multi-chip IGBT modules and convert them into analog voltage signals V PG ;

[0009] Determine the analog voltage signal V that determines the chip open circuit failure of the multi-chip IGBT module PG The failure threshold V REF3 ;

[0010] Based on the measured analog voltage signal V PG and failure threshold V REF3 Determine whether a multi-chip IGBT module has a chip open circuit failure.

[0011] Furthermore, the health sensitive parameter is determined as the gate voltage of the multi-chip IGBT module rising from 0 to the set voltage V SET The time is the gate voltage precharge time t PG , set voltage V SET Set it below the flat band voltage at the maximum operating voltage of the multi-chip IGBT module.

[0012] Furthermore, by taking the measured analog voltage signal V PG and failure threshold V REF3 For comparison, if V PG Below the failure threshold V REF3 , it is determined that the multi-chip IGBT module has a chip open circuit failure. If V PG Above the failure threshold V REF3 , it is determined that the multi-chip IGBT module has no chip open circuit failure.

[0013] Furthermore, the health sensitive parameter value of the multi-chip IGBT module is measured and converted into an analog voltage signal V PG The specific steps include:

[0014] Capture the equivalent pulse of the gate voltage signal during the turn-on and turn-off process of the multi-chip IGBT module;

[0015] The equivalent pulses representing the gate voltage pre-charge time t are obtained based on the captured turn-on and turn-off processes of the multi-chip IGBT module. PG Digital pulses;

[0016] Eliminate gate voltage precharge time t PG The pulse of the shut-off process is converted into an amplitude representing t PG The analog voltage signal V PG .

[0017] Furthermore, the capturing of equivalent pulses of gate voltage signals during the on / off process of the multi-chip IGBT module specifically comprises the following steps:

[0018] The collected multi-chip IGBT module gate voltage signal is voltage matched by a resistor divider composed of voltage divider resistors R1 and R2;

[0019] The output voltage V of the resistor divider is added by a non-inverting adder ge Raise a DC voltage E C , ensuring that the output signal V gep Within the input voltage range allowed by the window comparator;

[0020] The output signal V of the in-phase adder gep Input to the window comparator, respectively with the input reference voltage V REF1 and V REF2 Compare and output the corresponding comparison result V a and V b , V REF2 That is, set the voltage V SET ;

[0021] Comparison results V a and V b The signals are output to the logic sub-circuit through digital isolators U4 and U5 respectively, and the equivalent pulses of the on-off process of the multi-chip IGBT module are obtained respectively.

[0022] Furthermore, the equivalent pulse acquisition based on the captured multi-chip IGBT module turn-on and turn-off process represents the gate voltage pre-charge time t PG The digital pulse comprises the following steps:

[0023] The output signal of the window comparator Va and V b The corresponding equivalent pulse is input to the logic AND gate U6 to obtain the digital pulse V represented by the pulse width. gg ;

[0024] The output signal of the window comparator V b The corresponding equivalent pulse is input to the RC delay circuit, and the output signal of the RC delay circuit is proportional to V b The corresponding equivalent pulses are input to the logic AND gate U7 together to obtain the enable signal OE.

[0025] Furthermore, the gate voltage pre-charge time t PG The pulse of the shut-off process is converted into an amplitude representing t PG The analog voltage signal V PG , specifically including the steps:

[0026] The output signal V of the logic AND gate U6 is gg Input to the signal input terminal of the tri-state buffer U8, and input the output signal OE of the logic AND gate U7 to the enable terminal of the tri-state buffer U8;

[0027] The output signal V of the tri-state buffer U8 buf Input to the RC integration circuit composed of resistor R8 and capacitor C3, and get the amplitude representing t PG The analog voltage signal V PG .

[0028] Furthermore, the analog voltage signal V based on the actual measurement PG and failure threshold V REF3 Determining whether a chip open circuit failure occurs in a multi-chip IGBT module specifically includes the following steps:

[0029] The enable signal OE passes through the RC delay circuit and the logic NOT gate U 10 , thus obtaining the D flip-flop U 11 The clock signal CLK;

[0030] The output signal V PG With the input reference voltage V REF3 Input high speed comparator U9 for comparison;

[0031] The output signal of high-speed comparator U9 is input to D flip-flop U 11 The data input terminal;

[0032] D Flip Flop 11 Output voltage signal V representing the health status of chip branch of multi-chip IGBT module dia ;

[0033] If the output voltage Vdia If it is low level, the multi-chip IGBT module is in a healthy state;

[0034] If the output voltage V dia If the voltage is high, the multi-chip IGBT module will fail due to chip open circuit.

[0035] The present invention also provides a multi-chip IGBT module chip open circuit failure monitoring system, which applies the multi-chip IGBT module chip open circuit failure monitoring method, and the key is that the system includes a health sensitive parameter determination module, a measurement module, a failure threshold determination module and a diagnosis module, the health sensitive parameter determination module is used to determine the health sensitive parameter for monitoring the multi-chip IGBT module chip open circuit failure, the measurement module is used to measure the health sensitive parameter value of the multi-chip IGBT module and convert it into an analog voltage signal V PG The failure threshold determination module is used to determine the analog voltage signal V that determines the occurrence of chip open circuit failure in the multi-chip IGBT module. PG The failure threshold V REF3 The diagnostic module is based on the measured analog voltage signal V PG and failure threshold V REF3 Determine whether a multi-chip IGBT module has a chip open circuit failure.

[0036] Preferably, the measurement module adopts a measurement circuit, and the measurement circuit includes a signal processing subcircuit, a logic subcircuit and a signal conversion subcircuit;

[0037] The signal processing subcircuit includes a resistor divider composed of voltage-dividing resistors R1 and R2, a common-mode adder composed of a high-speed operational amplifier U1, resistors R3, R4, R5, R6 and a capacitor C1, a window comparator composed of high-speed comparators U2 and U3, digital isolators U4 and U5, an input reference voltage V REF1 、V REF2 , DC voltage E C The voltage divider resistors R1 and R2 are connected in series and coupled between the gate G and the auxiliary emitter AE of the multi-chip IGBT module. The midpoint of the voltage divider resistors R1 and R2 is connected in series and coupled to the in-phase input terminal of the high-speed operational amplifier U1 through the resistor R4. The DC voltage E C The resistor R5 is coupled to the non-inverting terminal of the high-speed operational amplifier U1, the resistor R3 is coupled between the inverting input terminal of the high-speed operational amplifier U1 and the reference ground, the resistor R6 and the capacitor C1 are connected in parallel and coupled between the inverting input terminal and the output terminal of the high-speed operational amplifier U1, and the output terminal of the high-speed operational amplifier U1 is respectively coupled to the non-inverting input terminal of the high-speed comparator U2 and the inverting input terminal of the high-speed comparator U3, and the input reference voltage V REF1 、V REF2The outputs of the high-speed comparator U2 and the high-speed comparator U3 are respectively coupled to the inverting input terminal of the high-speed comparator U2 and the non-inverting input terminal of the high-speed comparator U3, and the outputs of the high-speed comparator U2 and the high-speed comparator U3 are respectively coupled to the input terminals of the digital isolators U4 and U5;

[0038] The logic subcircuit includes an RC delay circuit composed of a resistor R7 and a capacitor C2 and two logic AND gates U6 and U7; the resistor R7 and the capacitor C2 are connected in series and coupled between the output end of the digital isolator U4 and the digital reference ground, the input end of the logic AND gate U6 is respectively coupled to the midpoint of the RC delay circuit and the output end of the digital isolator U4, and the input end of the logic AND gate U7 is respectively coupled to the output end of the digital isolator U4 and the output end of the digital isolator U5;

[0039] The signal conversion subcircuit includes a three-state buffer U8 and an RC integration circuit composed of a resistor R8 and a capacitor C3; the enable end of the three-state buffer U8 is coupled to the output end of the logic AND gate U6, the signal input end of the three-state buffer U8 is coupled to the output end of the logic AND gate U7, the resistor R8 and the capacitor C3 are connected in series and coupled between the output end of the three-state buffer U8 and the digital reference ground, and the output voltage at the midpoint of the series connection between the resistor R8 and the capacitor C3 is V representing the gate voltage pre-charge time. PG .

[0040] The multi-chip IGBT module chip open circuit failure monitoring method and system provided by the present invention first determine the health sensitive parameters for monitoring the multi-chip IGBT module chip open circuit failure, then measure the health sensitive parameter values ​​of the multi-chip IGBT module and convert them into analog voltage signals V PG , and then determine the analog voltage signal V that determines the chip open circuit failure of the multi-chip IGBT module PG The failure threshold V REF3 Finally, the measured analog voltage signal V PG and failure threshold V REF3 The comparison is performed to determine whether the multi-chip IGBT module has a chip open circuit failure. The present invention realizes chip open circuit failure monitoring of the multi-chip IGBT module without unpacking the multi-chip IGBT module package, and only needs to collect the gate voltage signal, with few factors affected, easy to measure, non-invasive, plug-and-play or integrated in the drive circuit, and easy to realize the in-situ monitoring of chip open circuit failure of the multi-chip IGBT module, and has strong practical application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a flow chart of a method for monitoring chip open circuit failure of a multi-chip IGBT module provided by an embodiment of the present invention;

[0042] Figure 2 It is the structure and circuit diagram of the multi-chip IGBT module provided by the embodiment of the present invention;

[0043] Figure 3 is the collector-emitter voltage v during the turn-on process of the multi-chip IGBT module provided by the embodiment of the present invention CE , collector current i C , gate voltage v GE , gate current i G Waveform diagram of

[0044] Figure 4 is a circuit diagram of a measurement circuit provided by an embodiment of the present invention;

[0045] Figure 5 This is an ideal waveform diagram of key nodes of a multi-chip IGBT module gate voltage pre-charge time measurement circuit provided by an embodiment of the present invention;

[0046] Figure 6 This is a double pulse test circuit diagram of a multi-chip IGBT module provided by an embodiment of the present invention;

[0047] Figure 7 The multi-chip IGBT modules under two working conditions provided by the embodiment of the present invention are different bus voltages V DC V PG Result graph;

[0048] Figure 8 The multi-chip IGBT module under two working conditions provided by the embodiment of the present invention is different from the load current I L V PG Result graph;

[0049] Fig. 9 The multi-chip IGBT module under two working conditions provided by the embodiment of the present invention is at different junction temperatures T j V PG Result graph;

[0050] Fig.10 is a circuit diagram of a diagnostic circuit provided by an embodiment of the present invention;

[0051] Fig.11 It is a waveform diagram of intermediate nodes and output signals of a diagnostic circuit under different working conditions provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The following specifically illustrates the implementation mode of the present invention in conjunction with the accompanying drawings. The embodiments are provided for illustrative purposes only and cannot be understood as limiting the present invention. The accompanying drawings are provided for reference and illustration only and do not constitute a limitation on the scope of patent protection of the present invention, because many changes can be made to the present invention without departing from the spirit and scope of the present invention.

[0053] The embodiment of the present invention provides a method for monitoring chip open circuit failure of a multi-chip IGBT module. Figure 1 As shown in the flowchart, the steps include:

[0054] Determine a health sensitive parameter for monitoring chip open circuit failure of a multi-chip IGBT module, where the health sensitive parameter is related to the number n of effective chip branches in the multi-chip IGBT module and is at least not affected by bus voltage and load current;

[0055] Measure the health sensitive parameter values ​​of multi-chip IGBT modules and convert them into analog voltage signals V PG ;

[0056] Determine the analog voltage signal V that determines the chip open circuit failure of the multi-chip IGBT module PG The failure threshold V REF3 ;

[0057] Based on the measured analog voltage signal V PG and failure threshold V REF3 Determine whether a multi-chip IGBT module has a chip open circuit failure.

[0058] The structure and circuit of a specific multi-chip IGBT module are as follows: Figure 2 As shown, this module is a FF150R12ME3G welding type IGBT module. Figure 2 (a) shows the internal structure of the FF150R12ME3G welding type IGBT module. Figure 2 (b) is the equivalent circuit of the FF150R12ME3G welding IGBT module. The FF150R12ME3G welding IGBT module contains two switches connected in series to form a half-bridge structure. Each switch consists of three chip branches, and each branch consists of an IGBT chip and a FWD chip. Figure 2 In (a), the first capital letter of the parameter designation means: Q for IGBT chip, D for diode chip, G for gate, AE for auxiliary emitter, C for collector, and E for emitter. The first subscript of the parameter designation means: T for top and B for bottom. The second subscript (if any) specifies the chip number. Figure 2 In (b), R gint , L g , C GC , C GE and C CE They are the internal gate resistance, gate loop parasitic inductance, gate-collector capacitance, gate-emitter capacitance and collector-emitter capacitance of each chip branch. T is the parasitic inductance of the upper tube power terminal, L C is the parasitic inductance of the midpoint power terminal, L B It is the parasitic inductance of the lower tube power terminal.

[0059] Collector-emitter voltage v during the turn-on process of a multi-chip IGBT module CE , collector current i C , gate voltage v GE , gate current i G The waveform diagram is as follows Figure 3 As shown, V DC ,I L 、V PO 、V FB 、V TH 、V GP 、V GON 、V GOFF and I GP They are DC bus voltage, load current, gate peak voltage, flat band voltage, threshold voltage, Miller platform voltage, turn-on gate voltage, turn-off gate voltage and Miller platform current. According to the characteristics of collector current, the present invention divides the turn-on process of multi-chip IGBT module into two stages:

[0060] (1) Precharge phase (t0-t3): During this phase, the gate control signal flips from 0 to 1, and the gate voltage v GE It starts to rise from time t0 and reaches V at time t1, t2, and t3 respectively. PO 、V FB and V TH In the pre-charge stage, the conductive channel has not yet been formally formed, and the collector current i C and the collector-emitter voltage v CE There will be no major changes.

[0061] (2) Fast turn-on stage (t>t3): When v GE Exceeding the threshold voltage V TH , the conductive channel is formally formed, and the multi-chip IGBT module formally enters the fast conduction stage. The collector current i C Starts to rise rapidly, the collector-emitter voltage v CE Start to descend rapidly.

[0062] The expression of the gate voltage in the pre-charge phase is:

[0063]

[0064] Where n is the number of effective chip branches in the multi-chip IGBT module, R gint is the internal gate resistance of a single chip branch, R gext is the external gate resistor, R gint is the internal gate resistance of a single chip branch, C GE is the gate-emitter capacitance of a single chip, V GONis the turn-on gate voltage, V GOFF is the turn-off gate voltage, V SET To define t PG The voltage at the end time, t represents the time, and e represents the natural base.

[0065] The gate voltage rises from 0 to the set voltage V SET The time is defined as the precharge time t PG , then the pre-charge time t PG The relationship between the number of parallel chip branches n can be expressed as:

[0066]

[0067] When a chip open circuit failure occurs, the number of parallel chip branches n inside the module decreases, and the gate voltage pre-charge time t PG decreases, so t PG It can be used as a health sensitive parameter to monitor chip open circuit failure.

[0068] Furthermore, we need to analyze t PG Relationship between bus voltage, load current and junction temperature.

[0069] (1)t PG With bus voltage V DC Relationship between: Gate-emitter capacitance C during switching GE The expression is:

[0070]

[0071] Among them, C OXD is the gate oxide capacitance, which is independent of the bus voltage. dep is the depletion layer capacitance, which is inversely proportional to the bus voltage. PG The terminal voltage V SET Set the flat band voltage V FB The following can eliminate the influence of bus voltage change. Furthermore, the flat band voltage V FB Affected by the bus voltage, due to the short channel effect, as the bus voltage increases, V FB Therefore, the present invention reduces V SET It is set below the flat-band voltage at the maximum operating voltage of the multi-chip IGBT module to eliminate the influence of bus voltage changes.

[0072] (2)t PG With load current I L Relationship between: In the pre-charging stage, the conductive channel in the IGBT gate region has not been formally formed. No matter how the load current changes, the collector current i flowing through the multi-chip IGBT module CThe current is 0, so t PG With load current I L Not relevant.

[0073] (3)t PG and junction temperature T j The relationship between: t PG In the expression of gint Affected by the change of junction temperature, t PG About R gint Differentiating it gives:

[0074]

[0075] Among them, R gint The temperature sensitivity is very small, only 1-2mV / ℃. In addition, the external gate resistor R gext The presence of further inhibits R gint Therefore, the effect of junction temperature change on t PG Only a slight effect.

[0076] Therefore, in this embodiment, the health sensitive parameter is determined as the gate voltage pre-charge time t of the multi-chip IGBT module. PG The health sensitive parameter can also be set to other parameters, but the parameter must be related to the number n of effective chip branches in the multi-chip IGBT module and at least not affected by the bus voltage and load current.

[0077] In order to effectively measure the health sensitive parameter values ​​(gate voltage pre-charge time t PG ) and converts it into an analog voltage signal V PG , this embodiment specifically adopts the steps:

[0078] Capture the equivalent pulse of the gate voltage signal during the turn-on and turn-off process of the multi-chip IGBT module;

[0079] The equivalent pulses representing the gate voltage pre-charge time t are obtained based on the captured turn-on and turn-off processes of the multi-chip IGBT module. PG Digital pulses;

[0080] Eliminate gate voltage precharge time t PG The pulse of the shut-off process is converted into an amplitude representing t PG The analog voltage signal V PG .

[0081] This embodiment designs a measurement circuit to implement the above three steps. Figure 4As shown in the circuit diagram of the provided measuring circuit, the measuring circuit specifically includes a signal processing subcircuit, a logic subcircuit and a signal conversion subcircuit, which are respectively used to implement the above three steps.

[0082] The main function of the signal processing subcircuit is to capture t PG The start and end time of Figure 4 As shown, the signal processing subcircuit includes a resistor divider composed of voltage divider resistors R1 and R2, a common-mode adder composed of a high-speed operational amplifier (OPA) U1, resistors R3, R4, R5, R6 and capacitor C1, a window comparator composed of high-speed comparators (CMP) U2 and U3, digital isolators (ISO) U4 and U5, and an input reference voltage V REF1 、V REF2 (Input reference voltage V REF2 V SET ), DC voltage E C The voltage divider resistors R1 and R2 are connected in series and coupled between the gate G and the auxiliary emitter AE of the multi-chip IGBT module. The midpoint of the voltage divider resistors R1 and R2 is connected in series and coupled to the in-phase input terminal of the high-speed operational amplifier U1 through the resistor R4. The DC voltage E C The resistor R5 is coupled to the non-inverting terminal of the high-speed operational amplifier U1, the resistor R3 is coupled between the inverting input terminal of the high-speed operational amplifier U1 and the reference ground, the resistor R6 and the capacitor C1 are connected in parallel and coupled between the inverting input terminal and the output terminal of the high-speed operational amplifier U1, and the output terminal of the high-speed operational amplifier U1 is respectively coupled to the non-inverting input terminal of the high-speed comparator U2 and the inverting input terminal of the high-speed comparator U3, and the input reference voltage V REF1 、V REF2 They are respectively coupled to the inverting input terminal of the high-speed comparator U2 and the non-inverting input terminal of the high-speed comparator U3 . The outputs of the high-speed comparator U2 and the high-speed comparator U3 are respectively coupled to the input terminals of the digital isolators U4 and U5 .

[0083] The workflow of the signal processing subcircuit is:

[0084] The collected multi-chip IGBT module gate voltage signal is voltage matched by a resistor divider composed of voltage divider resistors R1 and R2;

[0085] The output voltage V of the resistor divider is added by a non-inverting adder ge Raise a DC voltage E C , ensuring that the output signal V gep Within the window comparator’s allowed input voltage range and suppressing the gate spike voltage V PO interference;

[0086] The output signal V of the in-phase adder gep Input to the window comparator, respectively with the input reference voltage VREF1 and V REF2 Compare and output the corresponding comparison result V a and V b ;

[0087] The comparison result V a and V b The signals are output to the logic sub-circuit through digital isolators U4 and U5 respectively, and the equivalent pulses of the on-off process of the multi-chip IGBT module are obtained respectively.

[0088] It should be pointed out that the feedback loop of the in-phase adder is connected in parallel with capacitor C1, whose main function is to perform phase compensation and form a low-pass filter to suppress the gate peak voltage V PO The capacitance design principle for the interference to the measurement is:

[0089]

[0090] Among them, t r_PG is the duration of the gate voltage pre-charge phase.

[0091] The main function of the logic subcircuit is to convert the comparison result of the window comparator into a pulse width representative t PG The digital pulse is used to generate the enable signal of the signal conversion sub-circuit. Figure 4 As shown, the logic subcircuit includes an RC delay circuit composed of a resistor R7 and a capacitor C2 and two logic AND gates (AND) U6 and U7. The resistor R7 and the capacitor C2 are connected in series and coupled between the output terminal of the digital isolator U4 and the digital reference ground. The input terminal of the logic AND gate U6 is respectively coupled to the midpoint of the RC delay circuit and the output terminal of the digital isolator U4, and the input terminal of the logic AND gate U7 is respectively coupled to the output terminal of the digital isolator U4 and the output terminal of the digital isolator U5.

[0092] The workflow of the logic subcircuit is:

[0093] The output signal of the window comparator V a and V b The corresponding equivalent pulse is input to the logic AND gate U6 to obtain the digital pulse V represented by the pulse width. gg ;

[0094] The output signal of the window comparator V b The corresponding equivalent pulse is input to the RC delay circuit, and the output signal of the RC delay circuit is proportional to V b The corresponding equivalent pulses are input to the logic AND gate U7 together to obtain the enable signal OE.

[0095] The main function of the signal conversion subcircuit is to eliminate the pulse of the shutdown process and convert t PG Converted into analog voltage signal V PG .like Figure 4 As shown, the signal conversion subcircuit includes a three-state buffer (3S-buf) U8 and an RC integration circuit composed of a resistor R8 and a capacitor C3. The enable terminal of the three-state buffer U8 is coupled to the output terminal of the logic AND gate U6, the signal input terminal of the three-state buffer U8 is coupled to the output terminal of the logic AND gate U7, the resistor R8 and the capacitor C3 are connected in series and then coupled between the output terminal of the three-state buffer U8 and the digital reference ground, and the output voltage at the midpoint of the series connection between the resistor R8 and the capacitor C3 is V, which represents the gate voltage pre-charge time. PG .

[0096] The workflow of the signal conversion subcircuit is:

[0097] The output signal V of the logic AND gate U6 is gg Input to the signal input terminal of the tri-state buffer U8, and input the output signal OE of the logic AND gate U7 to the enable terminal of the tri-state buffer U8;

[0098] The output signal V of the tri-state buffer U8 buf Input to the RC integration circuit composed of resistor R8 and capacitor C3, and get the amplitude representing t PG The analog voltage signal V PG .

[0099] The design principle of the RC integration circuit in the signal conversion subcircuit is based on the input voltage range allowed by the microprocessor ADC. Taking a microprocessor with an allowable input voltage range of 3.3V as an example, the value selection principle of the RC integration circuit is as follows while ensuring a 20% safety margin:

[0100]

[0101] Figure 5 This is the ideal waveform diagram of the key nodes of the multi-chip IGBT module gate voltage pre-charge time measurement circuit, where t delay is the delay time introduced by the RC delay circuit in the logic subcircuit, and HI-Z is the high impedance state. After signal processing and logic subcircuit, the gate voltage of the multi-chip IGBT module has a pulse width of t PG Digital pulse V gg and enable signal OE. PG Within the range (t0~t1), OE is high level, and the output signal V buf At t0, it flips from low level to high level and starts charging capacitor C3. The voltage V on C3 PG It rises exponentially from 0. During the t1-t5 period, OE turns to low level, V buf In high impedance state, V PG Maintain the value at t1. This state continues until t5, when OE turns high again and V PGStart discharging to 0. It should be pointed out that the t1-t5 phase includes the multi-chip IGBT module shutdown process, thus eliminating the impact of the digital pulse during the shutdown process.

[0102] In this embodiment, by constructing Figure 6 The multi-chip IGBT module double pulse test circuit shown in the figure performs full-operation test on a healthy multi-chip IGBT module and a multi-chip IGBT module with an open circuit failure in one chip branch, and records the V PG , and set the failure threshold V for determining chip open circuit failure in multi-chip IGBT modules based on the experimental results REF3 . Figure 6 In the process, the upper IGBT device is always in the off state, the lower IGBT device is in the normal switching state, and the load inductance L load Connected in parallel at both ends of the upper IGBT device, V DC is the DC power supply voltage, C DC is the DC side support capacitor, R gext is the external gate resistor, V GG is the gate control signal.

[0103] In the specific experiment, the embodiment of the present invention adopts Figure 2 The multi-chip IGBT module FF150R12ME3G with three parallel chip branches was tested under healthy conditions and an open circuit failure condition in which an open circuit failure occurred in one chip branch. The experimental circuit constructed according to Figure 6 The relevant parameters of the experimental circuit are set as shown in Table 1. The multi-chip IGBT module chip open circuit failure is cut off by Figure 2 Q B1 All emitter bond wires are simulated.

[0104] Table 1

[0105]

[0106] Figure 7 The multi-chip IGBT modules under two working conditions at different bus voltages V DC V PG Results: (a) is the time domain waveform, (b) is the voltage V DC V PG Overview. Figure 7 It can be seen that V under healthy conditions and open circuit failure conditions PG With bus voltage V DC It doesn’t matter. V under two working conditions PG Basically unchanged, V under healthy conditions PGThe average value is about 2.669V, the highest value is 2.675V, and the lowest value is 2.655V. The V PG The average value is about 1.733V, the highest value is 1.738V, and the lowest value is 1.729V.

[0107] Figure 8 The multi-chip IGBT modules under two working conditions at different load currents I L V PG Results: (a) is the time domain waveform, (b) is the voltage V DC V PG Overview. Figure 8 It can be seen that V under healthy conditions and open circuit failure conditions PG With load current I L It doesn’t matter. V under two working conditions PG Basically unchanged, V under healthy conditions PG The average value is about 2.672V, the highest value is 2.675V, and the lowest value is 2.671V. The V PG The average value is about 1.732V, the highest value is 1.735V, and the lowest value is 1.729V.

[0108] Fig. 9 The multi-chip IGBT modules under two working conditions at different junction temperatures T j V PG Results: (a) is the time domain waveform, (b) is the waveform at different junction temperatures T j V PG Overview. Fig. 9 It can be seen that V under healthy conditions and open circuit failure conditions PG and junction temperature T j The correlation is not significant. V PG The changes are not significant, and V under healthy conditions PG The average value is about 2.675V, the highest value is 2.707V, and the lowest value is 2.643V. The V PG The average value is about 1.729V, the highest value is 1.783V, and the lowest value is 1.673V.

[0109] from Figures 7 to 9 It can be seen that under the two working conditions, V PG Both are relatively stable, and V PG There is a significant difference. Using the rounding method, at different bus voltages V DC , different load current I L , different junction temperature T j V under healthy conditions PGBoth are 2.7V (V He ), while V PG Both are 1.7V (V Fa ). In order to accurately distinguish these two working conditions, this embodiment determines the failure threshold V of the multi-chip IGBT module when the chip open circuit failure occurs. REF3 Set to:

[0110] V REF3 ∈[V Fa +α(V He -V Fa ),V Fa -α(V He -V Fa )](7)

[0111] The value of the coefficient factor α must satisfy V Fa +α(V He -V Fa ) is greater than V under all open circuit failure conditions PG The maximum value, V Fa -α(V He -V Fa ) is less than V under all healthy conditions PG The minimum value of .

[0112] In order to accurately distinguish between healthy working conditions and open circuit failure conditions, α should not be too small. In this embodiment, α is selected between (0.1, 0.5]. Finally, this embodiment determines that α is equal to 0.4, then the failure threshold V REF3 Select from [2.1,2.3]V. In this example, the failure threshold V is selected. REF3 is 2.3V.

[0113] By measuring the analog voltage signal V PG and failure threshold V REF3 For comparison, if V PG Below the failure threshold V REF3 , it is determined that the multi-chip IGBT module has a chip open circuit failure. If V PG Above the failure threshold V REF3 , it is determined that the multi-chip IGBT module has no chip open circuit failure.

[0114] In addition to testing a multi-chip IGBT module with an open circuit failure in one chip branch, a multi-chip IGBT module with open circuit failure in more than two chip branches can also be tested. By setting failure thresholds that are sufficient to distinguish between healthy conditions and open circuit failure conditions in which open circuit failures occur in one chip branch, two chip branches to n-1 chip branches, the number of open circuit failures in chip branches can be obtained.

[0115] In order to convert the measured analog voltage signal V PG and failure threshold V REF3 By comparison, a diagnosis result is obtained. The embodiment of the present invention designs a diagnosis circuit, such as Fig.10 As shown in the circuit diagram, the diagnostic circuit mainly includes a high-speed comparator U9, an RC delay circuit composed of a resistor R9 and a capacitor C4, a logic NOT gate U 10 , D flip-flop U 11 , input reference voltage V REF3 (Failure threshold). The input terminals of the high-speed comparator U9 are respectively connected to the input reference voltage V REF3 and the measurement circuit output V PG Resistor R9 and capacitor C4 are connected in series and coupled between the output terminal of logic AND gate U6 and the digital reference ground. 10 The input terminal is connected in series with the midpoint of resistor R9 and capacitor C4, and the D flip-flop U 11 The input terminals are connected to the output terminals of high speed comparator U9 and logic NOT gate U 10 The output terminal is coupled to the D flip-flop U 11 The output terminal is a voltage signal V that represents the health status of the chip branch of the multi-chip IGBT module. dia .

[0116] The workflow of the diagnostic circuit is as follows:

[0117] The enable signal OE passes through the RC delay circuit and the logic NOT gate U 10 , thus obtaining the D flip-flop U 11 The clock signal CLK;

[0118] The output signal V of the measuring circuit PG With the input reference voltage V REF3 Input high speed comparator U9 for comparison;

[0119] The output signal of high-speed comparator U9 is input to D flip-flop U 11 The data input terminal;

[0120] D Flip Flop 11 Output voltage signal V representing the health status of chip branch of multi-chip IGBT module dia .

[0121] If the output voltage V dia If it is low level, the multi-chip IGBT module is in a healthy state;

[0122] If the output voltage V dia If the voltage is high, the multi-chip IGBT module will fail due to chip open circuit.

[0123] Fig.11 Figure 2 is the waveform diagram of the intermediate nodes and output signals of the diagnostic circuit under different working conditions, where (a) is the healthy working condition and (b) is the open circuit failure condition. Fig.11 It can be seen that when the multi-chip IGBT module does not have a chip open circuit failure, the D trigger U 11 The output signal V dia When the multi-chip IGBT module fails due to chip open circuit, the D trigger U 11 The output signal V dia is high, which verifies the effectiveness of the diagnostic circuit.

[0124] It should also be noted that the above-mentioned measurement circuit and diagnosis circuit are only a preferred implementation mode, and other circuits and implementation modes that can achieve the same functions may also be used.

[0125] The embodiment of the present invention also provides a multi-chip IGBT module chip open circuit failure monitoring system, which applies the above-mentioned multi-chip IGBT module chip open circuit failure monitoring method. The system includes a health sensitive parameter determination module, a measurement module, a failure threshold determination module and a diagnosis module. The health sensitive parameter determination module is used to determine the health sensitive parameter for monitoring the multi-chip IGBT module chip open circuit failure. The measurement module is used to measure the health sensitive parameter value of the multi-chip IGBT module and convert it into an analog voltage signal V PG The failure threshold determination module is used to determine the analog voltage signal V that determines the occurrence of chip open circuit failure in the multi-chip IGBT module. PG The failure threshold V REF3 The diagnostic module is based on the measured analog voltage signal V PG and failure threshold V REF3 Determine whether a multi-chip IGBT module has a chip open circuit failure. These modules are electronic modules that can achieve corresponding functions, and the measurement module and the diagnosis module can use the above measurement circuit and diagnosis circuit.

[0126] In summary, the multi-chip IGBT module chip open circuit failure monitoring method and system provided by the embodiment of the present invention first determine the health sensitive parameter for monitoring the multi-chip IGBT module chip open circuit failure, and then measure the health sensitive parameter value of the multi-chip IGBT module and convert it into an analog voltage signal V PG , and then determine the analog voltage signal V that determines the chip open circuit failure of the multi-chip IGBT module PG The failure threshold V REF3 Finally, the measured analog voltage signal V PG and failure threshold V REF3The comparison is performed to determine whether the multi-chip IGBT module has a chip open circuit failure. The present invention realizes chip open circuit failure monitoring of the multi-chip IGBT module without unpacking the multi-chip IGBT module package, and only needs to collect the gate voltage signal, with few factors affected, easy to measure, non-invasive, plug-and-play or integrated in the drive circuit, and easy to realize the in-situ monitoring of chip open circuit failure of the multi-chip IGBT module, and has strong practical application value.

[0127] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A method for monitoring chip open circuit failure of a multi-chip IGBT module, characterized in that: Includes steps: Determine a health sensitive parameter for monitoring chip open circuit failure of a multi-chip IGBT module, where the health sensitive parameter is related to the number n of effective chip branches in the multi-chip IGBT module and is at least not affected by bus voltage and load current; Measure the health sensitive parameter values ​​of multi-chip IGBT modules and convert them into analog voltage signals V PG ; Determine the analog voltage signal V that determines the chip open circuit failure of the multi-chip IGBT module PG The failure threshold V REF3 ; Based on the measured analog voltage signal V PG and failure threshold V REF3 Determine whether a multi-chip IGBT module has a chip open circuit failure.

2. The method for monitoring chip open circuit failure of a multi-chip IGBT module according to claim 1, characterized in that: The health sensitive parameter is determined as the gate voltage of the multi-chip IGBT module rising from 0 to the set voltage V SET The time is the gate voltage precharge time t PG , set voltage V SET Set it below the flat band voltage at the maximum operating voltage of the multi-chip IGBT module.

3. The method for monitoring chip open circuit failure of a multi-chip IGBT module according to claim 2, characterized in that: By measuring the analog voltage signal V PG and failure threshold V REF3 For comparison, if V PG Below the failure threshold V REF3 , it is determined that the multi-chip IGBT module has a chip open circuit failure. If V PG Above the failure threshold V REF3 , it is determined that the multi-chip IGBT module has no chip open circuit failure.

4. The method for monitoring chip open circuit failure of a multi-chip IGBT module according to claim 3, characterized in that: The method measures the health sensitive parameter value of the multi-chip IGBT module and converts it into an analog voltage signal V PG The specific steps include: Capture the equivalent pulse of the gate voltage signal during the turn-on and turn-off process of the multi-chip IGBT module; The equivalent pulses representing the gate voltage pre-charge time t are obtained based on the captured turn-on and turn-off processes of the multi-chip IGBT module. PG Digital pulses; Eliminate gate voltage precharge time t PG The pulse of the shut-off process is converted into an amplitude representing t PG The analog voltage signal V PG .

5. The method for monitoring chip open circuit failure of a multi-chip IGBT module according to claim 4, characterized in that: The capturing of the equivalent pulse of the gate voltage signal during the on-off process of the multi-chip IGBT module specifically comprises the following steps: The collected multi-chip IGBT module gate voltage signal is voltage matched by a resistor divider composed of voltage divider resistors R1 and R2; The output voltage V of the resistor divider is added by a non-inverting adder ge Raise a DC voltage E C , ensuring that the output signal V gep Within the input voltage range allowed by the window comparator; The output signal V of the in-phase adder gep Input to the window comparator, respectively with the input reference voltage V REF1 and V REF2 Compare and output the corresponding comparison result V a and V b , V REF2 That is, set the voltage V SET ; Comparison results V a and V b The signals are output to the logic sub-circuit through digital isolators U4 and U5 respectively, and the equivalent pulses of the on-off process of the multi-chip IGBT module are obtained respectively.

6. The method for monitoring chip open circuit failure of a multi-chip IGBT module according to claim 5, characterized in that: The equivalent pulse acquisition based on the captured multi-chip IGBT module turn-on and turn-off process represents the gate voltage pre-charge time t PG The digital pulse comprises the following steps: The output signal of the window comparator V a and V b The corresponding equivalent pulse is input to the logic AND gate U6 to obtain the digital pulse V represented by the pulse width. gg ; The output signal of the window comparator V b The corresponding equivalent pulse is input to the RC delay circuit, and the output signal of the RC delay circuit is proportional to V b The corresponding equivalent pulses are input to the logic AND gate U7 together to obtain the enable signal OE.

7. The method for monitoring chip open circuit failure of a multi-chip IGBT module according to claim 6, characterized in that: The gate voltage precharge time t PG The pulse of the shut-off process is converted into an amplitude representing t PG The analog voltage signal V PG , specifically including the steps: The output signal V of the logic AND gate U6 is gg Input to the signal input terminal of the tri-state buffer U8, and input the output signal OE of the logic AND gate U7 to the enable terminal of the tri-state buffer U8; The output signal V of the tri-state buffer U8 buf Input to the RC integration circuit composed of resistor R8 and capacitor C3, and get the amplitude representing t PG The analog voltage signal V PG .

8. The method for monitoring chip open circuit failure of a multi-chip IGBT module according to claim 7, characterized in that: The measured analog voltage signal V PG and failure threshold V REF3 Determining whether a chip open circuit failure occurs in a multi-chip IGBT module specifically includes the following steps: The enable signal OE passes through the RC delay circuit and the logic NOT gate U 10 , thus obtaining the D flip-flop U 11 The clock signal CLK; The output signal V PG With the input reference voltage V REF3 Input high speed comparator U9 for comparison; The output signal of high-speed comparator U9 is input to D flip-flop U 11 The data input terminal; D Flip Flop 11 Output voltage signal V representing the health status of chip branch of multi-chip IGBT module dia ; If the output voltage V dia If it is low level, the multi-chip IGBT module is in a healthy state; If the output voltage V dia If the voltage is high, the multi-chip IGBT module will fail due to chip open circuit.

9. A multi-chip IGBT module chip open circuit failure monitoring system, using the multi-chip IGBT module chip open circuit failure monitoring method according to any one of claims 1 to 8, characterized in that: The system includes a health sensitive parameter determination module, a measurement module, a failure threshold determination module and a diagnosis module. The health sensitive parameter determination module is used to determine the health sensitive parameter for monitoring the open circuit failure of the multi-chip IGBT module chip. The measurement module is used to measure the health sensitive parameter value of the multi-chip IGBT module and convert it into an analog voltage signal V PG The failure threshold determination module is used to determine the analog voltage signal V that determines the occurrence of chip open circuit failure in the multi-chip IGBT module. PG The failure threshold V REF3 The diagnostic module is based on the measured analog voltage signal V PG and failure threshold V REF3 Determine whether a multi-chip IGBT module has a chip open circuit failure.

10. The multi-chip IGBT module chip open circuit failure monitoring system according to claim 9, characterized in that: The measurement module adopts a measurement circuit, which includes a signal processing subcircuit, a logic subcircuit and a signal conversion subcircuit; The signal processing subcircuit includes a resistor divider composed of voltage-dividing resistors R1 and R2, a common-mode adder composed of a high-speed operational amplifier U1, resistors R3, R4, R5, R6 and a capacitor C1, a window comparator composed of high-speed comparators U2 and U3, digital isolators U4 and U5, an input reference voltage V REF1 、V REF2 , DC voltage E C The voltage divider resistors R1 and R2 are connected in series and coupled between the gate G and the auxiliary emitter AE of the multi-chip IGBT module. The midpoint of the voltage divider resistors R1 and R2 is connected in series and coupled to the in-phase input terminal of the high-speed operational amplifier U1 through the resistor R4. The DC voltage E C The resistor R5 is coupled to the non-inverting terminal of the high-speed operational amplifier U1, the resistor R3 is coupled between the inverting input terminal of the high-speed operational amplifier U1 and the reference ground, the resistor R6 and the capacitor C1 are connected in parallel and coupled between the inverting input terminal and the output terminal of the high-speed operational amplifier U1, and the output terminal of the high-speed operational amplifier U1 is respectively coupled to the non-inverting input terminal of the high-speed comparator U2 and the inverting input terminal of the high-speed comparator U3, and the input reference voltage V REF1 、V REF2 The outputs of the high-speed comparator U2 and the high-speed comparator U3 are respectively coupled to the inverting input terminal of the high-speed comparator U2 and the non-inverting input terminal of the high-speed comparator U3, and the outputs of the high-speed comparator U2 and the high-speed comparator U3 are respectively coupled to the input terminals of the digital isolators U4 and U5; The logic subcircuit includes an RC delay circuit composed of a resistor R7 and a capacitor C2 and two logic AND gates U6 and U7; the resistor R7 and the capacitor C2 are connected in series and coupled between the output end of the digital isolator U4 and the digital reference ground, the input end of the logic AND gate U6 is respectively coupled to the midpoint of the RC delay circuit and the output end of the digital isolator U4, and the input end of the logic AND gate U7 is respectively coupled to the output end of the digital isolator U4 and the output end of the digital isolator U5; The signal conversion subcircuit includes a three-state buffer U8 and an RC integration circuit composed of a resistor R8 and a capacitor C3; the enable end of the three-state buffer U8 is coupled to the output end of the logic AND gate U6, the signal input end of the three-state buffer U8 is coupled to the output end of the logic AND gate U7, the resistor R8 and the capacitor C3 are connected in series and coupled between the output end of the three-state buffer U8 and the digital reference ground, and the output voltage at the midpoint of the series connection between the resistor R8 and the capacitor C3 is V representing the gate voltage pre-charge time. PG .

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