Differentiated Testing Method, System, Electronic Device and Storage Medium for Wafer

Abstract

The present invention provides a differential testing method, system, electronic device and storage medium for wafers. Among them, the method includes: based on the testing requirements of wafers in the same batch and the coordinate information of the die to be tested, allocating the coordinate information of each die to be tested to at least one die set; setting electrical schemes for each die set to form at least one test set; combining at least one die set and its corresponding at least one test set to generate at least one test scheme set; obtaining the wafers of the same batch of wafers, determining the test content of each wafer based on at least one test scheme set; and performing differential testing on the wafers of the same batch based on the test content. In this way, differential testing can be performed on the wafers of each batch and / or the dies of each wafer, meeting the customized test scheme requirements of the FAB, shortening the time for wafer-level electrical testing of wafers, and thus improving the wafer shipment efficiency of the FAB.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer-level electrical testing, and in particular, to a differential testing method, system, electronic device, and storage medium for wafers. Background Art

[0002] In the field of wafer testing, during the R & D stage of wafer products, a set of test schemes is generally used to perform wafer electrical testing on wafers, and the electrical parameters of specific test structures on the wafers are tested. Currently, during the process of testing wafers by existing wafer-level electrical testing equipment, only the same set of test schemes can be selected for the wafers to be tested. In order to test the electrical parameters of wafers more comprehensively, a large number of test schemes need to be defined in the set of test schemes to cover as much as possible. However, if the current scheme is adopted, there are no differential testing conditions, and only the test schemes of a single set of test schemes can be supported. The changeability and expandability of the test schemes are relatively low, and the needs of some FAB manufacturers for wafer differential testing cannot be met. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a differential testing method, system, electronic device, and storage medium for wafers, so as to define a set of test schemes (super test spec) specified for each wafer in each lot, enable differential wafer-level electrical testing, meet the requirements of the customized set of test schemes of FAB (wafer fab, Fabrication), shorten the time for testing wafers in wafer-level electrical testing, and thus improve the wafer shipment efficiency of FAB (wafer fab).

[0004] In a first aspect, an embodiment of the present invention provides a differential testing method for wafers. The method includes: based on the test requirements of wafers in the same lot and the coordinate information of the die to be tested, allocating the coordinate information of each die to be tested to at least one die set; setting electrical schemes for each die set to form at least one test set; generating at least one set of test schemes based on the combination of at least one die set and its corresponding at least one test set; obtaining the wafers of the wafers in the same lot, and determining the test content of each wafer based on at least one set of test schemes; and performing differential testing on the wafers in the same lot based on the test content.

[0005] In an alternative embodiment of the present application, based on the test requirements of wafers in the same batch and the coordinate information of the die to be tested, the coordinate information of each die to be tested is assigned to at least one die set; an electrical scheme is set for each die set to form at least one test set, including: defining at least one die set and the test coordinate points of the die to be tested according to the test requirements of wafers in the same batch; wherein, at least one die set contains the same or different test coordinate points; setting at least one test object for each die set; generating at least one test set according to the combination of at least one test object, and setting at least one electrical scheme for the test object.

[0006] In an alternative embodiment of the present application, the above combination based on at least one die set and its corresponding at least one test set includes: classifying and merging at least one test set, and matching each test set with the die set and the coordinate information required for testing to obtain at least one test scheme set, and each test scheme set contains completely identical / partially identical / completely different test sets, test objects and die sets.

[0007] In an alternative embodiment of the present application, the above combination based on at least one die set and its corresponding at least one test set further includes: when matching each test set with the die set, verifying whether all the test objects in the test set are located in at least one test object of the die set; if there is a test object not located in at least one test object of the die set, an error prompt is given.

[0008] In an alternative embodiment of the present application, the above obtaining the wafers of the same batch of wafers and determining the test content of each wafer based on at least one test scheme set includes: selecting the wafers to be tested in the same batch of wafers and obtaining at least one test scheme set; configuring the test scheme set according to the test requirements of the wafers to be tested to determine the test content of each wafer.

[0009] In an alternative embodiment of the present application, the above configuring the test scheme set according to the test requirements of the wafers to be tested includes: loading the test scheme set and checking whether the test content defined by the test scheme set is accurate; if the test content defined by the test scheme set is accurate, determining the test scheme set of each wafer to be tested; if the test content defined by the test scheme set is inaccurate, re-determining the defined content of the test scheme set.

[0010] In an alternative embodiment of the present application, the above differential testing of the wafers in the same batch based on the test content includes: obtaining the wafers to be tested in the same batch of wafers and the test scheme set; traversing the wafers to be tested, and obtaining the required test scheme set according to the information of the currently tested wafer; performing electrical testing on the currently tested wafer according to the test scheme set.

[0011] In a second aspect, an embodiment of the present invention further provides a differential testing system for wafers, the system comprising: a test plan definition module, configured to allocate the coordinate information of each die to be tested to at least one die set based on the test requirements of wafers in the same batch and the coordinate information of the dies to be tested; set an electrical plan for each die set to form a test set; generate at least one test plan set based on the combination of at least one die set and its corresponding at least one test set; a wafer definition module, configured to obtain the wafers of the wafers in the same batch and determine the test content of each wafer based on at least one test plan set; a wafer differential testing module, configured to perform differential testing on the wafers in the same batch based on the test content.

[0012] In an alternative embodiment of the present application, the above-mentioned test plan definition module includes a die set definition unit, an electrical plan definition unit, and a test plan definition unit; the die set definition unit is configured to define a die set and the test coordinate points of the dies to be tested according to the test requirements of wafers in the same batch; wherein, at least one die set includes at least one same or different test coordinate point; set at least one test object for each die set; the electrical plan definition unit is configured to generate at least one test set by combining at least one test object and set at least one electrical plan for the test object; the test plan definition unit is configured to generate at least one test plan set based on the combination of at least one die set and its corresponding at least one test set.

[0013] In an alternative embodiment of the present application, the above-mentioned wafer definition module includes a test wafer determination unit and a test plan determination unit; the test wafer determination unit is configured to obtain the wafers of the wafers in the same batch, determine the wafers to be tested and set a unique identifier; the test plan determination unit is configured to obtain at least one test plan set, bind the unique identifier to the required test plan set, and determine the test content of the wafers to be tested.

[0014] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising a processor and a memory, the memory storing computer-executable instructions that can be executed by the processor, and the processor executing the computer-executable instructions to implement the above-mentioned differential testing method for wafers.

[0015] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, the computer-readable storage medium storing computer-executable instructions, and when the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the above-mentioned differential testing method for wafers.

[0016] The embodiments of the present invention bring the following beneficial effects:

[0017] An embodiment of the present invention provides a method, system, electronic device, and storage medium for differential testing of wafers. Based on the test requirements of wafers in the same batch and the coordinate information of the dies to be tested, the coordinate information of each die to be tested is assigned to at least one die set; an electrical scheme is set for each die set to form at least one test set; based on at least one die set and its corresponding at least one test set, combinations are made to generate at least one test scheme set; wafers of the same batch are obtained, and the test content of each wafer is determined based on at least one test scheme set; differential testing of the wafers in the same batch is performed based on the test content. In this way, differential testing at the wafer level and die level can be achieved. In the prior art, only the same test can be performed on wafers in the same batch, and differential testing of different wafers in the same batch and different dies in one wafer cannot be achieved. According to the test requirements (such as multiple electrical test schemes), this technical solution sets multiple die sets containing die coordinate information, and matches at least one test set to the die set. By freely combining the die sets, multiple sets of test scheme sets are formed. Since the die set only contains partial coordinate points, differential testing of different dies on one wafer is achieved by setting multiple die sets corresponding to test sets. At the same time, multiple sets of test scheme sets are set for different wafers to choose from, enabling differential wafer-level electrical testing of multiple wafers in the same batch, meeting the customized test scheme requirements of the FAB (wafer fab), shortening the time for wafer-level electrical testing of wafers, and thus improving the wafer shipping efficiency of the FAB (wafer fab).

[0018] Other features and advantages of the present disclosure will be set forth in the following description, or may be learned by inference from the description, or may be clearly known by implementing the above technologies of the present disclosure.

[0019] To make the above objects, features, and advantages of the present disclosure more comprehensible, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, provides a detailed description as follows. Description of the Drawings

[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1 It is a flowchart of a method for differential testing of wafers provided by an embodiment of the present invention.

[0022] Figure 2Flowchart of another differential testing method for wafers provided by an embodiment of the present invention;

[0023] Figure 3 Schematic diagram of the composition relationship of a super test spec provided by an embodiment of the present invention;

[0024] Figure 4 Schematic diagram of the implementation process of a wafer definition module for each lot provided by an embodiment of the present invention;

[0025] Figure 5 Schematic diagram of differential testing of wafers provided by an embodiment of the present invention;

[0026] Figure 6 Schematic diagram of a differential testing method provided by an embodiment of the present invention;

[0027] Figure 7 Schematic diagram of a die list editing interface provided by an embodiment of the present invention;

[0028] Figure 8 Schematic diagram of a die spec editing interface provided by an embodiment of the present invention;

[0029] Figure 9 Schematic diagram of a test spec editing interface provided by an embodiment of the present invention;

[0030] Figure 10 Schematic diagram of a super test spec editing interface provided by an embodiment of the present invention;

[0031] Figure 11 Schematic diagram of a wafer configuration interface provided by an embodiment of the present invention;

[0032] Figure 12 Schematic diagram of the structure of a differential testing system for wafers provided by an embodiment of the present invention;

[0033] Figure 13 Schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0035] Currently, existing wafer testing solutions generally determine the testing time and electrical parameters of wafers in each lot based on the category and quantity. However, the current wafer-level electrical testing software does not have the function of differential testing. During software testing, only a single testing solution is supported. The variability and scalability of existing testing solutions are relatively low, and they cannot meet the needs of wafer differential testing in some FABs (wafer fabs).

[0036] Based on this, a differential testing method, system, electronic device, and storage medium for wafers provided by an embodiment of the present invention specifically provide a differential testing method for wafer-level electrical testing of super test spec. Aiming at the problem of a single testing solution selected for wafers in each lot during existing wafer-level electrical testing, it can meet the requirements of different FABs to define different testing solution sets for different wafers in each lot, improve the range of electrical testing parameters in a single lot, and meet the needs of differential testing.

[0037] To facilitate the understanding of this embodiment, first, a differential testing method for wafers disclosed by an embodiment of the present invention will be introduced in detail.

[0038] Embodiment 1:

[0039] An embodiment of the present invention provides a differential testing method for wafers. The differential testing solution for wafers provided in this embodiment includes the following modules: a testing solution definition module, a wafer definition module for each lot (which can be abbreviated as the wafer definition module), and a wafer differential testing module.

[0040] Based on the above description, refer to Figure 1 the flowchart of a differential testing method for wafers shown in the figure. The differential testing method for wafers includes the following steps:

[0041] Step S102, based on the testing requirements of wafers in the same lot and the coordinate information of the die to be tested, allocate the coordinate information of each die to be tested to at least one die set; set an electrical plan for each die set to form at least one testing set.

[0042] In this embodiment, the testing solution definition module can set the die set and the coordinate information of the die to be tested based on the testing requirements, and can also set an electrical plan for each die set to form multiple testing sets; the testing requirements can be multiple electrical testing solutions. For example, if multiple tests need to be performed on different dies on the same wafer, multiple die sets can be set for multiple tests, and the coordinate information that needs to be tested for the same content is placed in the same die set, so as to realize the setting of differential testing content for the same wafer.

[0043] Among them, the coordinate information of each of the above dies belongs to at least one die set, that is, the same coordinate information may exist in multiple die sets. At least one die included in multiple die sets may be the same, that is, the same die is subjected to different tests.

[0044] In some embodiments, at least one die set and the test coordinate points of the dies to be tested can be defined according to the test requirements of wafers in the same batch; among them, at least one die set includes multiple identical or different test coordinate points; at least one test object is set for each die set; at least one test set is generated by combining at least one test object, and at least one electrical scheme is set for the test object.

[0045] Exemplarily, the test object here can be a module. For each die set, multiple modules to be tested and corresponding coordinates are set, and then a test set is set according to the test requirements. The test set is formed by setting an electrical scheme for each selected module. Each die set can include multiple test sets according to the test requirements.

[0046] The test scheme definition module in this embodiment can also set an electrical scheme for each die under multiple die sets. Specifically, different electrical schemes can be defined for the modules to be tested under each die.

[0047] Among them, in this embodiment, at least one die set and the test coordinate points of the dies to be tested can be defined first according to the test requirements of wafers in the same batch, and then at least one test object is set for the die set and an electrical scheme is set based on the test object, so as to form a test set associated with the die set.

[0048] Step S104, combine at least one die set and its corresponding at least one test set to generate at least one test scheme set.

[0049] The test scheme definition module in this embodiment can also combine at least one die set and its corresponding at least one test set to generate at least one test scheme set.

[0050] In some embodiments, at least one test set under the same or different die coordinates can be classified and merged, and a die set and the coordinate information required for testing are matched for each test set to obtain at least one test scheme set. Each test scheme set includes test sets, die sets, and test objects that are completely the same, partially the same, or completely different.

[0051] The test plan definition module in this embodiment can classify and merge single or multiple test sets under the same or different die coordinates, so as to obtain multiple test plan sets. Among them, a test plan set in this embodiment can include at least one of the above complete or partial test plans. Because there may be coordinate information of the same or different dies when defining the die set, when setting the test set for the module (module) defined based on each die set, one or more test sets under the same or different die coordinates will be generated.

[0052] Step S106: Obtain wafers of the same batch of wafers, and determine the test content of each wafer based on at least one test plan set; perform differential testing on the wafers of the same batch based on the test content.

[0053] The wafer definition module in this embodiment can obtain the wafer information of each batch, and determine the super test spec (test plan set) of each wafer based on the above test plan set, so as to define the specified test content of each wafer in each batch.

[0054] The wafer differential testing module in this embodiment can perform differential testing on the wafers of each batch and / or the dies of each wafer based on the test content of each wafer, so as to perform differential wafer-level electrical testing, meet the customized test plan requirements of the FAB, shorten the time for wafer-level electrical testing of wafers, and thus improve the wafer shipping efficiency of the FAB.

[0055] An embodiment of the present invention provides a differential testing method for wafers. Based on the testing requirements of wafers in the same batch and the coordinate information of the die to be tested, the coordinate information of each die to be tested is assigned to at least one die set; an electrical scheme is set for each die set to form at least one test set; based on at least one die set and its corresponding at least one test set, combinations are made to generate at least one test scheme set; wafers of the same batch are obtained, and the testing content of each wafer is determined based on at least one test scheme set; differential testing is performed on the wafers of the same batch based on the testing content. In this way, differential testing at the wafer level and die level can be achieved. The prior art can only perform the same test on wafers in the same batch, and cannot achieve differential testing of different wafers in the same batch and differential testing of different dies on one wafer. This technical solution sets multiple die sets containing die coordinate information according to the testing requirements (such as multiple electrical testing schemes), and matches at least one test set to the die set. Multiple sets of test scheme sets are formed by freely combining the die sets. Because each die set only contains partial coordinate points, differential testing of different dies on one wafer is achieved by setting multiple die sets corresponding to test sets. At the same time, multiple sets of test scheme sets are set for different wafers to choose from, so that multiple wafers in the same batch can perform differential wafer-level electrical testing, meeting the customized testing scheme requirements of the FAB, shortening the time for wafer-level electrical testing of wafers, and thus improving the wafer shipping efficiency of the FAB.

[0056] Embodiment 2:

[0057] This embodiment provides another differential testing method for wafers, which is implemented on the basis of the above embodiment. Among them, the above method can be used for electrical testing of wafers.

[0058] ‌Electrical testing is a process of detecting the electrical performance of electronic components, PCB (Printed Circuit Board‌) boards, wafers, etc. In the field of semiconductor manufacturing, electrical testing is also an important link in the wafer manufacturing process. Various devices on the wafer will undergo electrical testing to check for defects and measure parameters to ensure that the wafer meets the predetermined electrical performance requirements before packaging and dicing.

[0059] The above method provided in this embodiment can be used for electrical testing of wafers. It should be noted here that the above method provided in this embodiment can not only be used for electrical testing of wafers, but also for other tests of wafers. This embodiment does not make any limitations in this regard.

[0060] Based on the above description, refer to Figure 2 the flowchart of another differential testing method for wafers shown in the figure. This differential testing method for wafers includes the following steps:

[0061] Step S202: Based on the test requirements of wafers in the same batch and the coordinate information of the bare dies to be tested, allocate the coordinate information of each bare die to be tested to at least one set of bare dies; set electrical schemes for each set of bare dies to form at least one test set.

[0062] Step S204: Classify and merge at least one test set, and match each test set with the set of bare dies and the coordinate information to be tested, to obtain at least one set of test schemes, where each set of test schemes includes test sets, test objects, and sets of bare dies that are exactly the same / partially the same / entirely different.

[0063] In some embodiments, when matching each test set with the set of bare dies, verify whether all the test objects in the test set are located in at least one of the test objects of the set of bare dies; if there are test objects not located in at least one of the test objects of the set of bare dies, an error message will be prompted.

[0064] Because when generating test sets, generally, the test sets are edited based on the modules existing in the set of bare dies, but it does not exclude adding modules that were not previously defined. Then, during the process of generating the set of test schemes, it will match the modules in the test set and the selected set of bare dies. If there are undefined modules, an alarm will be issued. At the same time, the user can update the previously defined modules (such as adding undefined modules). If no operation is performed, the test content of the undefined modules will be ignored during testing.

[0065] Reference can be made to Figure 3 the schematic diagram showing the composition relationship of a super test spec as shown. First, define the position coordinate points of the bare dies (dies) to be tested on the wafer, and define at least one test name (diename) for each coordinate for each die, that is, classify the bare dies to be tested to form multiple sets of bare dies.

[0066] Secondly, set test schemes for each set of bare dies. Specifically, define the position coordinate points of the modules (modules) to be tested for each set of bare dies, and define a test name (modulename) for each module coordinate point to form a die spec; based on the set module name, select the required module name to set electrical schemes to form multiple test sets, and name a single test set as a test spec.

[0067] Finally, according to the electrical test plan attributes and different test requirements, single and multiple test specs under the same or different die coordinates can be classified and merged to form multiple test plan sets under different dies or the same die, which are defined as super test specs. Each super test spec can contain exactly the same, partially the same, or completely different test specs (test sets), die specs (sets of test objects), and die lists (lists of die sets). The electrical test plans of the different super test specs defined above are saved to a file.

[0068] Step S206: Obtain wafers of the same batch of wafers, determine the test content of each wafer based on at least one test plan set; perform differential testing on the wafers of the same batch based on the test content.

[0069] In some embodiments, wafers to be tested in the same batch of wafers can be selected, and at least one test plan set can be obtained; the test plan set can be configured according to the test requirements of the wafers to be tested to determine the test content of each wafer.

[0070] In this embodiment, for the wafers to be tested in a batch of wafers, at least one test plan set can be obtained first, and then a suitable test plan set can be configured according to the test requirements of the wafers to be tested, so as to determine the test content of the wafers.

[0071] In some embodiments, the test plan set can be loaded to check whether the test content defined by the test plan set is accurate; if the test content defined by the test plan set is accurate, determine the test plan set for each wafer to be tested; if the test content defined by the test plan set is inaccurate, re-determine the defined content of the test plan set.

[0072] See Figure 4 As shown in the schematic implementation flow diagram of a wafer definition module for each lot, first, select 1 - 25 wafers to be tested in each lot on the wafer configuration interface. Secondly, load the file storing the electrical test plan to obtain different super test spec sets, check whether the content defined by the super test spec sets is correct, and then select different super test spec electrical test plans for different wafers in the electrical test plan configuration interface according to the wafer test requirements.

[0073] In some embodiments, wafers to be tested in the same batch of wafers and the test plan set can be obtained; traverse the wafers to be tested, obtain the required test plan set according to the information of the currently tested wafer; perform electrical testing on the currently tested wafer according to the test plan set.

[0074] After obtaining the wafers to be tested and the set of test schemes in a batch of wafers, the present embodiment can perform differential testing on the wafers to be tested. Among them, the wafers to be tested can be traversed, and the corresponding set of test schemes can be obtained according to the information of each wafer to be tested, and electrical testing can be performed on each wafer to be tested according to the set of test schemes.

[0075] See Figure 5 As shown in the schematic diagram of the differential testing of a kind of wafer, different super test spec differential testing modules can obtain the number and ID of the wafers to be tested from the wafer definition module of each lot, obtain the ID (subscript) of the wafer to be tested, obtain the specified super test spec according to the wafer ID, parse all the electrical testing schemes defined in the super test spec, loop to test each electrical testing scheme on the wafer, and store the test data results in real time.

[0076] In the field of wafer-level electrical testing, since the number of electrical testing schemes provided by different FABs is large and the testing time required for a single testing scheme is long, in a specific scenario, when a certain electrical testing scheme is newly added by the FAB, it is necessary to perform this electrical scheme testing only on the specified single or multiple wafers in each lot, but the existing methods can only perform this electrical scheme testing on all wafers in each lot, which cannot meet the differential testing requirements and affect the analysis efficiency of wafer electrical parameters.

[0077] The above method provided by the embodiment of the present invention specifically provides a differential testing method for electrical testing, which can define the test schemes specified for each wafer in each lot, can perform differential wafer-level electrical testing, meet the customized test scheme requirements of the FAB, shorten the time for testing wafers at the wafer-level electrical testing, and thus improve the wafer shipping efficiency of the FAB.

[0078] Embodiment 3:

[0079] The present embodiment provides a specific implementation manner of a differential testing method for wafers. This implementation manner is implemented on the basis of the above embodiment and can be seen in Figure 6 The schematic diagram of a differential testing method.

[0080] As Figure 6 shown, in order to meet the need to select different sets of electrical testing schemes for different wafers during the wafer-level electrical testing of the same lot (the same batch) of wafers by using the supporting test machine software internally and by customers, the present embodiment can provide a differential testing method for wafer-level electrical testing based on super test spec.

[0081] If a customer or internally adds one or more electrical test schemes, first, in the Super Test Spec definition module, according to the requirements of the test scheme, define the die name and test coordinate points in the die list editing interface. The interface after definition can be seen in Figure 7 A schematic diagram of a die list editing interface as shown.

[0082] Secondly, in the die spec editing interface, define diename1-6 respectively, define each module name and coordinate points. The interface after defining diename1 can be seen in Figure 8 A schematic diagram of a die spec editing interface as shown.

[0083] Then, in the test spec interface, define the electrical test schemes that need to be tested in each module. The editing interface after defining test1 (electrical test scheme 1, abbreviated as t1) can be seen in Figure 9 A schematic diagram of a test spec editing interface as shown. As Figure 9 shown, the first column is the name of the module name, xx is the specific content of the electrical test scheme that must be filled in, and the blank spaces can be filled or not.

[0084] Finally, in the super test spec interface, according to the specific requirements of the electrical test scheme, summarize and merge the above testspec and save it as different super test specs. The editing interface after defining super test spec1 can be seen in Figure 10 A schematic diagram of a super test spec editing interface as shown, where Select Die is selectable in Figure 7 Define different coordinate points with the name of diename1 (can be all selected, not selected, partially selected). Among them, Figure 10 The SelectedDies in is the multiple dies that are selected.

[0085] Summarize and define different electrical test scheme attributes as different super test specs and save them as specific files.

[0086] In each card lot wafer definition module, first load the file containing the super test spec, and then select the wafers to be inspected in each card lot in the wafer configuration interface. The wafer configuration interface can be seen in Figure 11 A schematic diagram of a wafer configuration interface as shown. As Figure 11As shown, by moving the wafer subscript defined by the left border to the right border, the wafer subscript defined in the right can correspond to the actual wafer subscript in each lot per card, and all wafers in each lot per card can be tested. Among them, Figure 11 the Selected Wafers in Figure 11 are multiple selected wafers, and the Slot in

[0087] is the position of the wafer. Finally, after selecting the required wafers to be tested and before entering the electrical test plan configuration interface, the test plan file is automatically loaded to obtain all defined different super test specs (such as defining 4 different super test specs). When opening the electrical test plan configuration interface, the same test plan is defined for all wafers by default (the supertest spec defined first by default). In this configuration interface, according to the test requirements, the specified Super Test Spec is manually selected for the wafers to be tested in each lot per card for subsequent testing.

[0088] Before performing the wafer test, the content of the super test spec plan selected for each wafer is loaded, and the wafers selected in each lot per card are tested according to the test processes of different super test spec differential test modules to obtain the differential electrical test parameter result data.

[0089] In summary, this embodiment can configure different wafers in each lot per card, select different super test specs, and can perform differential testing, so that the range of electrical test parameters covers a relatively wide range, meets the customized test plan requirements of the FAB, shortens the time for testing wafers in wafer-level electrical testing, and thus improves the wafer shipment efficiency of the FAB.

[0090] Embodiment 4:

[0091] Corresponding to the above method embodiment, an embodiment of the present invention provides a differential test system for wafers. Refer to Figure 12 the structural schematic diagram of a differential test system for wafers shown. This differential test system for wafers includes:

[0092] A test plan definition module 1201, configured to allocate the coordinate information of each die to be tested to at least one die set based on the test requirements of wafers in the same batch and the coordinate information of the dies to be tested; set an electrical plan for each die set to form a test set; combine at least one die set and its corresponding at least one test set to generate at least one test plan set;

[0093] The wafer definition module 1202 is configured to obtain wafers of the same batch, and determine the test content of each wafer based on at least one set of test schemes;

[0094] The wafer differential testing module 1203 is configured to perform differential testing on wafers of the same batch based on the test content.

[0095] An embodiment of the present invention provides a wafer differential testing system. Based on the test requirements of wafers of the same batch and the coordinate information of the dies to be tested, the coordinate information of each die to be tested is assigned to at least one die set; an electrical scheme is set for each die set to form at least one test set; based on at least one die set and its corresponding at least one test set, combinations are made to generate at least one set of test schemes; wafers of the same batch are obtained, and the test content of each wafer is determined based on at least one set of test schemes; differential testing is performed on wafers of the same batch based on the test content. In this way, differential testing at the wafer level and die level can be achieved. In the prior art, only the same testing can be performed on wafers of the same batch, and it is impossible to perform differential testing on different wafers in the same batch and different dies in one wafer. This technical solution sets multiple die sets containing die coordinate information according to the test requirements (such as multiple electrical testing schemes), and matches at least one test set for each die set. Multiple sets of test schemes are formed by freely combining the die sets. Since each die set only contains partial coordinate points, differential testing of different dies in one wafer can be achieved by setting multiple die sets corresponding to test sets. At the same time, multiple sets of test schemes can be selected by different wafers, enabling differential wafer-level electrical testing of multiple wafers in the same batch, meeting the customized test scheme requirements of the FAB, shortening the time for wafer-level electrical testing of wafers, and thus improving the wafer shipping efficiency of the FAB.

[0096] The above test scheme definition module includes a die set definition unit, an electrical scheme definition unit, and a test scheme definition unit;

[0097] The die set definition unit is configured to define die sets and the test coordinate points of the dies to be tested according to the test requirements of wafers of the same batch; wherein, at least one die set contains at least one identical or different test coordinate point; at least one test object is set for each die set;

[0098] The electrical scheme definition unit is configured to generate at least one test set by combining according to at least one test object, and set at least one electrical scheme for the test object;

[0099] The test scheme definition unit is configured to generate at least one set of test schemes by combining based on at least one die set and its corresponding at least one test set.

[0100] The test scheme definition module in this embodiment includes a die set definition unit, an electrical scheme definition unit, and a test scheme definition unit. The die set definition unit is used to define a die set and the test coordinate points of the dies to be tested. The electrical scheme definition unit is used to define an electrical scheme. The test scheme definition unit is used to generate at least one test scheme set.

[0101] The above-mentioned wafer definition module includes a test wafer determination unit and a test scheme determination unit. The test wafer determination unit is used to obtain wafers of the same batch, determine the wafers to be tested, and set a unique identifier. The test scheme determination unit is used to obtain at least one test scheme set, bind the unique identifier to the required test scheme set, and determine the test content of the wafers to be tested.

[0102] The wafer definition module in this embodiment includes a test wafer determination unit and a test scheme determination unit. The test wafer determination unit is used to determine the wafers to be tested and set a unique identifier. The test scheme determination unit is used to bind the unique identifier to the required test scheme set, so as to determine the test content of the wafers to be tested.

[0103] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described wafer differential testing system can refer to the corresponding process in the embodiment of the foregoing wafer differential testing method, which will not be elaborated here.

[0104] Embodiment Five:

[0105] The embodiment of the present invention also provides an electronic device for running the above-mentioned wafer differential testing method; see Figure 13 the structural schematic diagram of an electronic device shown. The electronic device includes a memory 100 and a processor 101. Among them, the memory 100 is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor 101 to implement the above-mentioned wafer differential testing method.

[0106] Furthermore, Figure 13 the electronic device shown also includes a bus 102 and a communication interface 103. The processor 101, the communication interface 103, and the memory 100 are connected through the bus 102.

[0107] Among them, the memory 100 may include high-speed random access memory (RAM), and may also include non-volatile memory, such as at least one disk memory. The communication connection between this system network element and at least one other network element is realized through at least one communication interface 103 (which can be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. can be used. The bus 102 can be an ISA bus, a PCI bus, an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 13 only a bidirectional arrow is used in

[0108] The processor 101 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of the processor 101 or the instructions in the form of software. The above-mentioned processor 101 can be a general-purpose processor, including a central processing unit (CPU for short), a network processor (NP for short), etc.; it can also be a digital signal processor (DSP for short), an application specific integrated circuit (ASIC for short), a field programmable gate array (FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present invention can be directly embodied as being executed and completed by the hardware decoding processor, or executed and completed by the combination of the hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the art such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, register, etc. This storage medium is located in the memory 100, and the processor 101 reads the information in the memory 100 and combines its hardware to complete the steps of the method in the foregoing embodiments.

[0109] An embodiment of the present invention also provides a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the above-mentioned differential testing method for wafers. For specific implementation, reference can be made to the method embodiment, which will not be elaborated here.

[0110] The computer program product of the differential testing method, system, electronic device and storage medium for wafers provided by the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods in the foregoing method embodiments. For specific implementation, reference can be made to the method embodiments, which will not be elaborated here.

[0111] Those skilled in the art can clearly understand that for the convenience and brevity of description, the above-described system and / or the specific working process of the system can refer to the corresponding process in the foregoing method embodiments, which will not be elaborated here.

[0112] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0113] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or a part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program code.

[0114] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the system or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0115] Finally, it should be noted that the above embodiments are only specific embodiments of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit it. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that any person skilled in the art within the technical scope disclosed by the present invention can still modify the technical solutions recorded in the foregoing embodiments, or can easily conceive of changes, or make equivalent replacements for some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A differential testing method for wafers, characterized in that, The method includes: Based on the test requirements of wafers in the same batch and the coordinate information of the die to be tested, allocate the coordinate information of each die to be tested to at least one die set; set electrical schemes for each of the die sets to form at least one test set; Based on the combination of the at least one die set and its corresponding at least one test set, generate at least one test plan set; Obtain the wafers of the same batch of wafers, determine the test content of each wafer based on the at least one test plan set; perform differential testing on the same batch of wafers based on the test content; Setting electrical schemes for each of the die sets to form at least one test set includes: setting at least one test object for each of the die sets; generating at least one test set according to the combination of the at least one test object, and setting at least one electrical scheme for the test object; The combination based on the at least one die set and its corresponding at least one test set includes: classifying and merging at least one test set, and matching each test set with a die set and the coordinate information required for testing to obtain at least one test plan set, and each test plan set includes exactly the same / partially the same / completely different test sets, test objects and die sets.

2. The method according to claim 1, wherein The allocation of the coordinate information of each die to be tested to at least one die set based on the test requirements of wafers in the same batch and the coordinate information of the die to be tested includes: Define at least one die set and the test coordinate points of the die to be tested according to the test requirements of wafers in the same batch; wherein, the at least one die set includes the same or different test coordinate points.

3. The method according to claim 1, characterized in that, The combination based on the at least one die set and its corresponding at least one test set further includes: When matching each test set with a die set, check whether all the test objects in the test set are located in at least one of the test objects of the die set; If there are test objects not located in at least one of the test objects of the die set, an error message will be prompted.

4. The method according to claim 1, characterized in that, The obtaining of the wafers of the same batch of wafers and determining the test content of each wafer based on the at least one test plan set includes: Select the wafers to be tested among the wafers of the same batch, and obtain at least one test plan set; Configure the test plan set according to the test requirements of the wafers to be tested, and determine the test content of each wafer.

5. The method according to claim 4, wherein The configuration of the test plan set according to the test requirements of the wafers to be tested includes: Load the test plan set and check whether the test content defined by the test plan set is accurate; If the test content defined by the test plan set is accurate, determine the test plan set for each of the wafers to be tested; if the test content defined by the test plan set is inaccurate, re-determine the defined content of the test plan set.

6. The method according to claim 4, wherein The differential testing of the same batch of wafers based on the test content includes: Obtain the wafers to be tested and the test plan set among the wafers of the same batch; Traverse the wafers to be tested, and obtain the required test plan set according to the information of the current wafer to be tested; Perform electrical testing on the current wafer to be tested according to the test plan set.

7. A differential testing system for wafers, characterized in that, The system includes: A test plan definition module, which is used to allocate the coordinate information of each die to be tested to at least one die set based on the test requirements of wafers in the same batch and the coordinate information of the dies to be tested; set electrical schemes for each of the die sets to form test sets; combine the at least one die set and its corresponding at least one test set to generate at least one test plan set; A wafer definition module, which is used to obtain the wafers of the wafers in the same batch and determine the test content of each wafer based on the at least one test plan set; A wafer differential test module, which is used to perform differential tests on the wafers in the same batch based on the test content; The test plan definition module is used to set at least one test object for each of the die sets; combine the at least one test object to generate at least one test set, and set at least one electrical scheme for the test object; The test plan definition module is used to classify and merge at least one test set, and match each test set with the die set and the coordinate information required for testing to obtain at least one test plan set, and each test plan set includes completely identical / partially identical / completely different test sets, test objects and die sets; 8. The system according to claim 7, wherein The test plan definition module includes a die set definition unit, an electrical scheme definition unit, and a test plan definition unit; The die set definition unit is used to define die sets and the test coordinate points of the dies to be tested according to the test requirements of wafers in the same batch; wherein, the at least one die set includes at least one identical or different test coordinate point; set at least one test object for each of the die sets; The electrical scheme definition unit is used to combine the at least one test object to generate at least one test set, and set at least one electrical scheme for the test object; The test plan definition unit is used to combine the at least one die set and its corresponding at least one test set to generate at least one test plan set; 9. The system according to claim 7, wherein The wafer definition module includes a test wafer determination unit and a test plan determination unit; The test wafer determination unit is used to obtain the wafers of the wafers in the same batch, determine the wafers to be tested and set a unique identifier; The test plan determination unit is used to obtain at least one test plan set, bind the unique identifier to the required test plan set, and determine the test content of the wafers to be tested; 10. An electronic device, characterized in that, It includes a processor and a memory, and the memory stores computer-executable instructions that can be executed by the processor. The processor executes the computer-executable instructions to implement the differential test method for wafers according to any one of claims 1 to 6.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are called and executed by the processor, the computer-executable instructions cause the processor to implement the differential test method for wafers according to any one of claims 1 to 6.

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