A low-power MCU power management unit implemented using asynchronous circuits

Abstract

The application relates to the field of chip design, in particular to a low-power MCU power management unit realized by using an asynchronous circuit. The application realizes isolated unit control, stabilized power supply control, HSI clock control and VCORE domain reset control asynchronously through a flip-flop and a series of delay chains. Compared with a PMU realized based on a state machine, the application is a full-asynchronous design, does not need a clock during work, reduces the dynamic power consumption of the PMU, and saves the power consumption required for maintaining clock operation in a low-power mode. Compared with a PMU realized based on a state machine which needs to wait for the clock to be stable before starting work, the application starts work as soon as the wake-up flag is valid, effectively shortening the wake-up response time of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip design, in particular to a low-power MCU power management unit implemented by using an asynchronous circuit. BACKGROUND

[0002] With the continuous development of Internet of Things technology, MCU plays an increasingly important role in it. An important indicator for measuring a MCU is power consumption. Reducing the power consumption of MCU not only prolongs the working time of Internet of Things system in battery-powered environment, but also reduces the working temperature of MCU chip to prolong the service life of the chip. The main low-power processing method at present is to divide the chip into multiple power domains, and then turn off the clock and power supply inside the MCU as much as possible when the CPU is not working. This is usually achieved by a power management unit (PMU) cooperating with clock, reset, isolation unit, power switch, etc. to control the low power consumption of MCU. In the existing scheme, the PMU is usually implemented based on a state machine, which completes circuit control by jumping to different states. This implementation method usually has two disadvantages. First, the state machine is a sequential circuit that needs a clock when working. The PMU implemented based on the state machine will generate a large amount of dynamic power consumption when working, and even in low power consumption mode, it cannot turn off all clock sources, otherwise the PMU will not be able to perform wake-up operation. In addition, even if the asynchronous wake-up circuit is used to turn off the clock source in low power consumption mode, the PMU needs to wait for the clock to recover before it can start working, thus increasing the recovery time when the chip wakes up. SUMMARY

[0003] The present application provides an asynchronous circuit implemented power management unit to effectively reduce power consumption and area cost, and shorten the response time of waking up from low power consumption mode, aiming at the deficiencies of the existing MCU power management unit implementation technology.

[0004] The present application provides the following technical solutions:

[0005] The present application provides a low-power MCU power management unit (PMU) implemented by using an asynchronous circuit, which includes an LDO, an HSI, an ISO, a VCORE domain, and an HSION register. The output signal of the VCORE domain is output to other modules after passing through the ISO.

[0006] The PMU includes an isolation control module, a power-on control module, and a delay wake-up module.

[0007] The isolation control module outputs Iso_on to the ISO as an enable signal of the ISO.

[0008] The isolation control module is configured to:

[0009] Iso_on is set to an effective state when Por_rstn_dly is a power-on reset state or Iso_clamp is an effective state; wherein, Por_rstn_dly is Por_rstn released through a delay, Por_rstn is a power-on reset signal; Iso_clamp is a signal obtained after Standby_en is delayed through a delay chain, and Standby_en is a low-power mode switching enable signal;

[0010] Iso_on is set to an invalid state after being delayed through a delay chain when the first condition changes from an unsatisfied state to a satisfied state, and the content of the first condition is that Por_rstn_dly is a reset release state and Standby_rstn is an invalid state; wherein, Standby_rstn is a VCORE domain reset signal, and the VCORE domain is reset when Standby_rstn is effective;

[0011] Ldo_on is output by the power-on control module to LDO as an enable signal of LDO;

[0012] The power-on control module is configured to:

[0013] Ldo_on is set to an effective state when Por_rstn_dly is a power-on reset state or a wake-up condition is satisfied; wherein, the wake-up condition includes that a wake-up flag signal Stdby_wkup_src is an effective state, and Ldo_on_dly is Ldo_on delayed through a delay chain;

[0014] Ldo_on is set to an invalid state when Iso_on_dly changes from invalid to effective; wherein, Iso_on_dly is Iso_on delayed through a delay chain;

[0015] The delay wake-up module outputs Standby_rstn;

[0016] The delay wake-up module is configured to:

[0017] Standby_rstn is set to an invalid state when Por_rstn_dly is a power-on reset state;

[0018] Standby_rstn is set to an effective state when a wake-up condition changes from unsatisfied to satisfied, and Standby_rstn is set to an invalid state when a delay preset wake-up time is reached.

[0019] The core circuit of the present application only uses a plurality of delay chains to complete all timing control, is not dependent on a clock, reduces dynamic power consumption of a PMU, and has a simpler PMU circuit structure compared with a state machine.

[0020] Further, when the enable signals sent by the LDO and the HSION register to the HSI are all valid, the HSI is turned on, otherwise the HSI is turned off; the enable signal sent by the LDO to the HSI is valid after the output voltage reaches a threshold value and lasts for a preset time;

[0021] The external wiring of the PMU is configured as:

[0022] When the Por_rstn_dly is a power-on reset state or the Standby_rstn is a valid state, the VCORE domain is reset, and the HSION register is reset, so that the enable signal sent by the HSION register to the HSI is valid.

[0023] The present application indirectly controls the HSI clock source enable by controlling the LDO enable and the Standby_rstn, and realizes that the HSI can be controlled by hardware and the control of the HSI by software is not affected.

[0024] Further, the delay wake-up module uses the clock signal Hsi_clk generated by the HSI to count time when the delay preset wake-up time.

[0025] The present application uses the clock signal Hsi_clk to count time, thereby ensuring that the VCORE domain reset is released after the HSI clock is stable.

[0026] Further, the wake-up condition further includes that the Ldo_on_dly is an invalid state.

[0027] The present application shields the wake-up flag signal before the power-off process is completed (the Ldo_on_dly has not become an invalid state), so as to avoid that the circuit is woken up by mistake.

[0028] Further, the isolation control module includes a DFF flip-flop ISO_ON and a delay chain.

[0029] The data input end D of the ISO_ON is always 1, and the positive output end Q is connected to Iso_on.

[0030] The Standby_en is delayed by using the delay chain to obtain Iso_clamp, and the Iso_clamp and the inverted Por_rstn_dly are subjected to logical or operation and then connected to the high-level valid reset input end of the ISO_ON.

[0031] Por_rstn_dly and Standby_rstn are logically ANDed, and the result is delayed by a delay chain and then input to the rising edge of ISO_ON to trigger the clock input end;

[0032] wherein Iso_on and Standby_rstn are low-level effective, Standby_en is high-level effective, Por_rstn_dly is low-level in power-on reset state and high-level in reset release state; Iso_on is 0 in ISO_ON reset;

[0033] Further, the power-on control module includes a DFF flip-flop LDO_ON and a delay chain.

[0034] The data input end D of LDO_ON is always 1, and the inverting output end QN is connected to Ldo_on.

[0035] Iso_on is delayed by a delay chain and then input to the falling edge of LDO_ON to trigger the clock input end.

[0036] Ldo_on is delayed by a delay chain to obtain Ldo_on_dly, Ldo_on_dly is inverted and logically ANDed with Stdby_wkup_src to obtain Ldo_on_set, Ldo_on_set is inverted and logically ANDed with Por_rstn_dly and then input to the low-level effective reset input end of LDO_ON.

[0037] wherein Ldo_on and Stdby_wkup_src are high-level effective, Iso_on is low-level effective; Por_rstn_dly is low-level in power-on reset state and high-level in reset release state; Ldo_on is 1 in LDO_ON reset;

[0038] Further, the delay wake-up module includes a DFF flip-flop LDO_HSI_ON, a counter Standby_rstn_cnt, a comparator and a delay chain.

[0039] The data input end D of LDO_HSI_ON is always 1, the positive output end Q is connected with Ldo_hsi_on, and the inverting output end QN is connected with Standby_rstn; the result of logical AND operation between the inverted Ldo_on_dly and Stdby_wkup_src is input into the rising edge trigger input end of LDO_HSI_ON, wherein Ldo_on_dly is Ldo_on delayed by a delay chain; Ldo_hsi_on is input into the enable input end of Standby_rstn_cnt after synchronization, the clock signal Hsi_clk generated by HSI is input into the rising edge trigger clock input end of Standby_rstn_cnt, the count value Hsi_cnt generated by Standby_rstn_cnt is connected with the input end of a comparator, the output end of the comparator is connected with Hsi_stable signal, when Hsi_cnt is equal to the set threshold n, Hsi_stable is 1, otherwise Hsi_stable is 0; Hsi_stable_dly is obtained by delaying Hsi_stable by a delay chain, Ldo_hsi_on_rstn is obtained by logical AND operation between the inverted Hsi_stable_dly and Por_rstn_dly, Ldo_hsi_on_rstn is input into the low level effective reset input end of LDO_HSI_ON flip-flop, and Ldo_hsi_on_rstn is input into the low level effective reset input end of Standby_rstn_cnt;

[0040] wherein Standby_rstn is low level effective, Ldo_hsi_on, Ldo_on and Stdby_wkup_src are high level effective; the power-on reset state of Por_rstn_dly is low level, and the reset release state is high level; when LDO_HSI_ON is reset, Ldo_hsi_on is 0, and Standby_rstn is 1.

[0041] Beneficial effects: the patent application realizes isolation unit control, stable voltage power supply control, HSI clock control and VCORE domain reset control asynchronously through the flip-flop and a series of delay chains. Compared with the PMU realized based on the state machine, the patent application is a full asynchronous design, and no clock is needed during work, which reduces the dynamic power consumption of the PMU and saves the power consumption needed for maintaining the clock running in the low power consumption mode. Compared with the PMU realized based on the state machine, which needs to wait for the clock to stabilize before starting to work, the patent application starts to work as soon as the wake-up flag is valid, effectively shortening the wake-up response time of the chip. From the circuit scale, the core circuit of the patent application only uses 3 flip-flops, 1 counter and a series of delay chains to complete all the timing control, and the circuit structure is simpler than that of the PMU realized based on the state machine. The patent application can reset and release the VCORE domain when waking up, and automatically reset the internal counter after waking up, without the need for software reset. The patent application indirectly controls the HSI clock source enablement by controlling the LDO enablement and Standby_rstn, realizes that the HSI can be controlled by hardware, and does not affect the control of the HSI by software. Finally, the patent application can shield the wake-up flag signal before the power-off process ends, avoiding the circuit from being awakened by mistake. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 The structural diagram of one embodiment of the power management unit in the application;

[0043] Figure 2 The structural diagram of one embodiment of the peripheral circuit of the power management unit in the application;

[0044] Figure 3 The timing control diagram of the power management unit in the embodiment of the application; DETAILED DESCRIPTION

[0045] In order to make the purpose, features and advantages of the application more obvious and easy to understand, the technical solutions in the embodiments of the application will be described clearly and completely in conjunction with the drawings in the embodiments of the application. Obviously, the following described embodiments are only part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0046] A low-power MCU power management unit (PMU) implemented using an asynchronous circuit, the MCU comprising an LDO (linear voltage regulator), an HSI (high-speed internal oscillator), an ISO (isolation unit), a VCORE domain, an HSION register; an output signal of the VCORE domain is output to other modules after passing through the ISO; when the LDO and the HSION register both send an enable signal to the HSI, the HSI is enabled, otherwise the HSI is disabled; when an output voltage of the LDO reaches a threshold value and lasts for a preset time, the LDO sends an enable signal to the HSI;

[0047] The PMU comprises an isolation control module, a power-on control module, and a delay wake-up module.

[0048] The isolation control module outputs Iso_on to the ISO as an enable signal of the ISO.

[0049] The isolation control module is configured to:

[0050] When Por_rstn_dly is in a power-on reset state or Iso_clamp is in an effective state, Iso_on is set to an effective state; Por_rstn_dly is Por_rstn released after a delay, Por_rstn is a power-on reset signal, and Iso_clamp is a signal obtained by delaying Standby_en through a delay chain, and Standby_en is a low-power mode switching enable signal.

[0051] When a first condition changes from an unsatisfied state to a satisfied state, Iso_on is set to an invalid state after being delayed through a delay chain, and the content of the first condition is that Por_rstn_dly is in a reset release state and Standby_rstn is in an invalid state; Standby_rstn is a VCORE domain reset signal, and when Standby_rstn is effective, the VCORE domain is reset.

[0052] The power-on control module outputs Ldo_on to the LDO as an enable signal of the LDO.

[0053] The power-on control module is configured to:

[0054] When Por_rstn_dly is in a power-on reset state or a wake-up condition is satisfied, Ldo_on is set to an effective state; the wake-up condition comprises that a wake-up flag signal Stdby_wkup_src is in an effective state and Ldo_on_dly is in an invalid state, and Ldo_on_dly is Ldo_on delayed through a delay chain.

[0055] Ldo_on is set to the invalid state when Iso_on_dly changes from invalid to valid, wherein Iso_on_dly is Iso_on delayed by a delay chain;

[0056] The standby_rstn is output by the delay wake-up module;

[0057] The delay wake-up module is configured to:

[0058] The standby_rstn is set to the invalid state when the Por_rstn_dly is in the power-on reset state;

[0059] The standby_rstn is set to the valid state when the wake-up condition changes from not satisfied to satisfied, and the standby_rstn is set to the invalid state when the delay preset wake-up time is reached;

[0060] The external wiring of the PMU is configured to:

[0061] The VCORE domain is reset and the HSION register is reset when the Por_rstn_dly is in the power-on reset state or the standby_rstn is in the valid state, so that the enable signal sent by the HSION register to the HSI is set to valid.

[0062] More specific embodiments will be described below:

[0063] The PMU is located in the 3.3V digital always-on power domain of the MCU, which is powered by the chip power pin and remains powered when entering the low-power mode.

[0064] The VCORE domain is located in the 1.1V digital power-off domain, which contains the MCU core, bus and various 1.1V digital peripherals, and is powered off when the chip enters the low-power mode.

[0065] The circuit architecture of the PMU is as shown in Figure 1 The PMU is composed of 3 DFF flip-flops (ISO_ON, LDO_ON, LDO_HSI_ON), 1 counter (Standby_rstn_cnt), 1 digital comparator (COMP), 5 delay chains and a number of logic gates and synchronizers. The PMU completes asynchronous power-on and power-off timing control through 5 delay chains without clock. The counter counts with the clock signal Hsi_clk to release the VCORE domain reset after the HSI clock is stable.

[0066] The PMU controls the ISO enable signal Iso_on and the LDO enable signal Ldo_on to be 0 when the chip enters the low power mode, controls Ldo_on to be 1 when the chip exits the low power mode, controls the VCORE domain reset signal Standby_rstn to be 0 and then to be 1 after a period of time, and finally controls Iso_on to be 1 to release the isolation of the VCORE domain.

[0067] The Iso_on is a low-level effective ISO enable signal, when Iso_on is 0, all the output signals of the VCORE domain are isolated, and when Iso_on is 1, the isolation of the VCORE domain is released.

[0068] The Ldo_on is a high-level effective LDO enable signal, when Ldo_on is 1, the LDO is enabled to restore the power supply of the VCORE domain, and when Ldo_on is 0, the LDO is disabled to power off the VCORE domain.

[0069] The Standby_rstn is a low-level effective VCORE domain reset signal, when Standby_rstn is 0, the VCORE domain is reset, and when Standby_rstn is 1, the VCORE domain reset is released.

[0070] The circuit connection relationship of the PMU is as follows Figure 1As shown, Por_rstn_dly and Standby_rstn are delayed by a set of delay chains to get Iso_release_in, which is delayed by a set of delay chains to get Iso_release and connected to the rising edge triggered clock input of ISO_ON flip-flop. Standby_en is delayed by a set of delay chains to get Iso_clamp, which and the inverted Por_rstn_dly or get Iso_on_rst, which is connected to the high active reset input of ISO_ON flip-flop. The data input D of ISO_ON flip-flop is always 1, and the positive output Q is connected to Iso_on. Iso_on is delayed by a set of delay chains to get Iso_on_dly and input to the falling edge triggered clock input of LDO_ON flip-flop. The data input D of LDO_ON is always 1, and the inverted output QN is connected to Ldo_on to control the enable of 1.1V LDO. Ldo_on is delayed by a set of delay chains to get Ldo_on_dly, which is inverted and and the wake-up flag signal Stdby_wkup_src to get Ldo_on_set. Ldo_on_set is inverted and and Por_rstn_dly to get Ldo_on_rstn, which is the low active reset input signal of LDO_ON flip-flop. Ldo_on_set is also connected to the rising edge triggered clock input of LDO_HSI_ON flip-flop, and the data input D of LDO_HSI_ON is always 1. The positive output Q of LDO_HSI_ON is connected to Ldo_Hsi_on, which is synchronized to HSI clock by two stages of synchronizers and used as the enable signal of Standby_rstn_cnt counter; the inverted output QN of LDO_HSI_ON is connected to Standby_rstn, which is 0 to reset the VCORE domain. The rising edge triggered clock input of Standby_rstn_cnt counter is connected to Hsi_clk, and it starts counting up when the enable signal EN of Standby_rstn_cnt counter is 1. The count value Hsi_cnt output by Standby_rstn_cnt is connected to the input of comparator, and the output of comparator is connected to Hsi_stable. When Hsi_cnt is equal to the set threshold n, Hsi_stable is 1, otherwise Hsi_stable is 0.Hsi_stable_dly is obtained after Hsi_stable is delayed by a set of delay chains, Hsi_stable_dly is inverted and connected with Por_rstn_dly and Standby_rstn to obtain Ldo_hsi_on_rstn, Ldo_hsi_on_rstn is input to the low-level effective reset input end of the LDO_HSI_ON flip-flop, and Ldo_hsi_on_rstn is input to the low-level effective reset input end of Standby_rstn_cnt.

[0071] The peripheral circuit of the PMU is as shown in Figure 2 Por_rstn_dly and Standby_rstn are connected to the low-level effective reset input end of the HSION register and the VCORE domain after being connected, the output of the HSION register is Hsi_on, and the reset value is 1, that is, the effective state. The HSION register can be configured by software. Ldo_on is connected to the enable end of the voltage stabilizing power supply LDO, and when the output voltage of the LDO reaches the threshold value 10us, the LDO sends an enable signal VCORE_OK_HV to the HSI, which is 1, that is, the effective state. VCORE_OK_HV and Hsi_on are connected with each other to obtain En_hsi and input to the enable end of the HSI clock source. When En_hsi is 1, the HSI starts to work and outputs the clock Hsi_clk, otherwise the clock output is prohibited. When the Standby_en signal output by the VCORE domain is 1, it indicates that the PMU is enabled to enter the low-power mode. The output signal of the VCORE domain is output to other modules after passing through the ISO isolation unit, and the isolation unit is effective when Iso_on is low. The APB bus output by the VCORE domain is connected to the HSION register after passing through the ISO, and is used to configure the HSION register.

[0072] As shown in Figure 3 The control flow of the PMU in the embodiment is as follows:

[0073] 1) Por_rstn_dly is the Por_rstn released after counting delay by Hsi_clk. Por_rstn is a power-on reset signal. When Por_rstn_dly is in the power-on reset state, it is set to low level by default and resets all the flip-flops and counters of the PMU, wherein Iso_on and Hsi_cnt are reset to 0, Ldo_on and Standby_rstn are reset to 1, and the LDO output is enabled and the VCORE domain is isolated.

[0074] 2) After the output voltage of the LDO reaches the threshold value 10us, VCORE_OK_HV is set to 1, and the HSI oscillator is enabled to generate the clock.

[0075] Por_rstn_dly and Standby_rstn are logically ANDed to form Iso_release_in. Por_rstn_dly is high to release the reset state, and Iso_release_in is set to 1.

[0076] 3) Iso_release_in is delayed by a delay chain to generate Iso_release. The rising edge of Iso_release triggers Iso_on to be set to 1, and ISO is disabled after being enabled.

[0077] 4) When entering the low-power mode, the low-power mode switching enable signal Standby_en is set to 1, and Iso_clamp is set to 1 after being delayed by a delay chain. The high level of Iso_clamp triggers Iso_on to be set to 0, and ISO enables Standby_en to be clamped to 0.

[0078] At the same time, since the PMU does not depend on the clock signal, HSI is closed by configuring the HSION register through the APB bus before Standby_en is sent by the VCORE domain.

[0079] 5) Iso_on is delayed by a delay chain to set Iso_on_dly to 0. The falling edge of Iso_on_dly triggers LDO_ON to output Ldo_on to 0, and LDO is turned off, completing the entire power-off process.

[0080] 6) When exiting the low-power mode, the input wake-up flag signal Stdby_wkup_src is set to 1. Ldo_on_dly is delayed by a delay chain to generate Ldo_on, which is set to 0 when the wake-up condition is met. When Ldo_on_dly is 0 and Stdby_wkup_src is 1, Ldo_on_set is set to 1.

[0081] 7) After Ldo_on_set is set to 1, the LDO_ON trigger is reset, Ldo_on is set to 1, and LDO is turned on. After the LDO output is valid, VCORE_OK_HV is set to 1.

[0082] At the same time, the rising edge of Ldo_on_set triggers Ldo_Hsi_on to be set to 1, enabling the counter to count Hsi_clk. The rising edge of Ldo_on_set triggers the LDO_HSI_ON inverting output end Standby_rstn to be set to 0, resetting the VCORE domain register and the HSION register, so that Hsi_on is set to 1, and the HSI oscillator generates a clock at this time.

[0083] 8) When Hsi_cnt reaches the comparator threshold, Hsi_stable is set to 1, and the LDO_HSI_ON flip-flop and counter are reset.

[0084] 9) The LDO_HSI_ON flip-flop reset sets Ldo_Hsi_on to 0 to stop the counting enable, and sets Standby_rstn to 1 to release the VCORE domain reset.

[0085] 10) Iso_release_in changes with Standby_rstn, and when Standby_rstn is released, Iso_release_in generates a rising edge.

[0086] 11) After the Iso_release_in rising edge is delayed, Iso_release generates a rising edge, which triggers Iso_on to 1, and completes the entire low-power wake-up process.

[0087] The above only describes the preferred embodiments of the present application, and it should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should be considered as the protection scope of the present application.

Claims

1. A low-power MCU power management unit, abbreviated as PMU, implemented using asynchronous circuitry, wherein the MCU includes an LDO, HSI, ISO, VCORE domain, and HSION register; the output signal of the VCORE domain is output after passing through ISO. Its features are, The PMU includes an isolation control module, a power-on control module, and a delayed wake-up module; Among them, the isolation control module outputs Iso_on to the ISO as the ISO's enable signal; The isolation control module is configured as follows: When Por_rstn_dly is in the power-on reset state or Iso_clamp is in the active state, Iso_on is set to the active state; where Por_rstn_dly is Por_rstn released after a delay, and Por_rstn is the power-on reset signal; Iso_clamp is the signal obtained after Standby_en is delayed by a delay chain, and Standby_en is the low-power mode switching enable signal; When the first condition changes from an unsatisfied state to a satisfied state, after a delay chain, Iso_on is set to an invalid state. The content of the first condition is that Por_rstn_dly is in a reset release state and Standby_rstn is in an invalid state; where Standby_rstn is the VCORE field reset signal. When Standby_rstn is valid, the VCORE field is reset. Among them, the power-on control module outputs Ldo_on to the LDO as the LDO enable signal; The power-on control module is configured as follows: When Por_rstn_dly is in power-on reset state or the wake-up condition is met, Ldo_on is set to the active state; where the wake-up condition includes the wake-up flag signal Stdby_wkup_src being active, and Ldo_on_dly being Ldo_on after the delay chain. When Iso_on_dly changes from invalid to valid, Ldo_on is set to invalid; where Iso_on_dly is the Iso_on after the delay chain. The delayed wake-up module outputs Standby_rstn; The delayed wake-up module is configured as follows: When Por_rstn_dly is in power-on reset state, Standby_rstn is set to invalid state; When the wake-up condition changes from not being met to being met, Standby_rstn is set to an active state; when the preset wake-up time is delayed, Standby_rstn is set to an inactive state. The isolation control module includes a DFF trigger ISO_ON and a delay chain; The data input terminal D of ISO_ON is always 1, and the positive output terminal Q is connected to Iso_on; The power-on control module includes a DFF trigger LDO_ON and a delay chain; The data input terminal D of LDO_ON is always 1, and the inverting output terminal QN is connected to LDO_ON; The delayed wake-up module includes a DFF trigger LDO_HSI_ON, a counter Standby_rstn_cnt, a comparator, and a delay chain. The data input terminal D of LDO_HSI_ON is always 1, the positive output terminal Q outputs the signal Ldo_hsi_on, and the inverting output terminal QN is connected to Standby_rstn.

2. A low-power MCU power management unit (PMU) implemented using asynchronous circuitry as described in claim 1, characterized in that: HSI is enabled when both the LDO and HSION registers send valid enable signals to HSI; otherwise, HSI is disabled. The LDO sends a valid enable signal to HSI after the output voltage reaches the threshold and remains so for a preset time. The external wiring of the PMU is configured as follows: When Por_rstn_dly is in power-on reset state or Standby_rstn is in active state, the VCORE field is reset and the HSION register is reset, so that the enable signal sent by the HSION register to HSI is enabled.

3. A low-power MCU power management unit (PMU) implemented using asynchronous circuitry as described in claim 1, characterized in that: The delayed wake-up module uses the clock signal Hsi_clk generated by HSI to keep track of the time when the preset wake-up time is delayed.

4. A low-power MCU power management unit (PMU) implemented using asynchronous circuits according to claim 1, wherein the wake-up condition further includes Ldo_on_dly being in an invalid state.

5. A low-power MCU power management unit (PMU) implemented using asynchronous circuitry as described in claim 1, characterized in that, in the isolation control module: Delay Standby_en using a delay chain to obtain Iso_clamp. Perform a logical OR operation between Iso_clamp and the inverted Por_rstn_dly, and then connect it to the high-level active reset input of ISO_ON. After Por_rstn_dly and Standby_rstn perform a logical AND operation, the result is delayed by a delay chain and then connected to the rising edge trigger clock input of ISO_ON. Iso_on and Standby_rstn are active low, Standby_en is active high, Por_rstn_dly is low during power-on reset and high during reset release; Iso_on is set to 0 when ISO_ON is reset.

6. A low-power MCU power management unit (PMU) implemented using asynchronous circuitry according to claim 1, characterized in that: In the power-on control module: After delaying Iso_on using a delay chain, it is connected to the falling edge trigger clock input of LDO_ON; After delaying Ldo_on using a delay chain, we get Ldo_on_dly. After inverting Ldo_on_dly, we perform a logical AND operation with Stdby_wkup_src to get Ldo_on_set. After inverting Ldo_on_set, we perform a logical AND operation with Por_rstn_dly and then connect it to the low-level active reset input of LDO_ON. in, Ldo_on and Stdby_wkup_src are active high, while Iso_on is active low; Por_rstn_dly is low on power-on reset and high on reset release; LDO_ON is set to 1 during LDO_ON reset.

7. A low-power MCU power management unit (PMU) implemented using asynchronous circuitry as described in claim 1, characterized in that, in the delayed wake-up module: The result of a logical AND operation between the inverted Ldo_on_dly and Stdby_wkup_src is connected to the rising edge trigger input of LDO_HSI_ON, where Ldo_on_dly is the delayed Ldo_on after the delay chain. Ldo_hsi_on, after synchronization, is input to the enable input of Standby_rstn_cnt. The clock signal Hsi_clk generated by HSI is connected to the rising edge trigger clock input of Standby_rstn_cnt. The count value Hsi_cnt generated by Standby_rstn_cnt is connected to the input of a comparator, and the output of the comparator is connected to Hsi_st. The signal is called Able. When Hsi_cnt equals the set threshold n, Hsi_stable is set to 1; otherwise, Hsi_stable is set to 0. After delaying Hsi_stable using a delay chain, Hsi_stable_dly is obtained. After inverting Hsi_stable_dly, a logical AND operation is performed with Por_rstn_dly to obtain Ldo_hsi_on_rstn. Ldo_hsi_on_rstn is input to the low-level active reset input of the LDO_HSI_ON flip-flop, and Ldo_hsi_on_rstn is input to the low-level active reset input of Standby_rstn_cnt. Standby_rstn is active low, while Ldo_hsi_on, Ldo_on, and Stdby_wkup_src are active high. Por_rstn_dly is low during power-on reset and high during reset release. When LDO_HSI_ON is reset, Ldo_hsi_on is set to 0 and Standby_rstn is set to 1.

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