Driving Method, Driving Circuit and Display Panel of a Display Panel

Abstract

The present application relates to a driving method, a driving circuit and a display panel of a display panel. The method includes: obtaining a data voltage of a current frame; determining, according to the polarity and the gray scale value of the data voltage, that the data voltage is a first data voltage or a second data voltage; wherein, a feed-through voltage generated when the first data voltage is written into a pixel unit is greater than a feed-through voltage generated when the second data voltage is written into the pixel unit; in a case where the data voltage is the first data voltage, writing the first data voltage into the pixel unit by using a first timing signal; and, in a case where the data voltage is the second data voltage, writing the second data voltage into the pixel unit by using a second timing signal; wherein, the first timing signal is delayed by a preset time relative to the second timing signal. By means of the present application, the technical problem in the prior art that the correction solution cannot well cover the entire gray scale range, resulting in local afterimage phenomena still occurring during non-specific gray scale changes, is solved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a driving method, a driving circuit, and a display panel for a display panel. Background Art

[0002] The pixel unit of an LCD display panel is controlled by a thin film transistor (TFT). When the gate voltage (Vgh / Vgl) of the TFT switches, its parasitic capacitance (Cgs), liquid crystal capacitance (Clc), and storage capacitance (Cst) form a coupling loop, generating a feedthrough voltage (Vkb). The amplitude of the feedthrough voltage is directly related to the capacitance values of the parasitic capacitance, liquid crystal capacitance, and storage capacitance. At the same time, the capacitance value of the liquid crystal capacitance is regulated by the gray scale, and the change in the gray scale causes the capacitance value of the liquid crystal capacitance to also change.

[0003] Therefore, when switching between different gray scales, the difference in the feedthrough voltage causes the effective voltage between the pixel electrode and the common electrode (Vcom) to not be fully reset, forming a cross-frame DC voltage bias. This bias continuously acts on the liquid crystal molecules, changing their alignment state, resulting in a residual image being "imprinted" on the screen, that is, the phenomenon of ghosting occurs.

[0004] In the prior art, the gray scale reference voltage (Gamma voltage) of a specific gray scale (such as gray scale 0) is usually corrected to suppress the ghosting phenomenon. However, such a correction scheme only targets a specific gray scale and cannot cover the entire gray scale range well, resulting in local ghosting phenomena still occurring when non-specific gray scales change. Summary of the Invention

[0005] This application provides a driving method, a driving circuit, and a display panel for a display panel to solve the technical problem that the correction scheme in the prior art cannot cover the entire gray scale range well, resulting in local ghosting phenomena still occurring when non-specific gray scales change.

[0006] In a first aspect, this application provides a driving method for a display panel, and the method includes:

[0007] Obtain the data voltage of the current frame;

[0008] Determine whether the data voltage is a first data voltage or a second data voltage according to the polarity and gray scale value of the data voltage; wherein, the feedthrough voltage generated when the first data voltage is written into the pixel unit is greater than the feedthrough voltage generated when the second data voltage is written into the pixel unit;

[0009] When the data voltage is the first data voltage, write the first data voltage into the pixel unit using a first timing signal; and when the data voltage is the second data voltage, write the second data voltage into the pixel unit using a second timing signal; wherein, the first timing signal is delayed by a preset time relative to the second timing signal.

[0010] In a feasible embodiment of the present application, determining that the data voltage is the first data voltage or the second data voltage according to the polarity and gray-scale value of the data voltage includes:

[0011] Determine the polarity of the data voltage and determine the gray-scale interval to which the gray-scale value of the data voltage belongs; wherein, the polarity of the data voltage is positive or negative, the gray-scale interval is the first gray-scale interval or the second gray-scale interval, and the gray-scale values in the first gray-scale interval are all smaller than the gray-scale values in the second gray-scale interval;

[0012] When the polarity and gray-scale value of the data voltage satisfy a first judgment condition, determine that the data voltage is the first data voltage; wherein, the first judgment condition is that the polarity of the data voltage is positive and the gray-scale value of the data voltage belongs to the first gray-scale interval, or the polarity of the data voltage is negative and the gray-scale value of the data voltage belongs to the second gray-scale interval;

[0013] When the polarity and gray-scale value of the data voltage satisfy a second judgment condition, determine that the data voltage is the second data voltage; wherein, the second judgment condition is that the polarity of the data voltage is positive and the gray-scale value of the data voltage does not belong to the first gray-scale interval, or the polarity of the data voltage is negative and the gray-scale value of the data voltage does not belong to the second gray-scale interval.

[0014] In a feasible embodiment of the present application, determining the polarity of the data voltage includes:

[0015] Obtain a common voltage;

[0016] Compare the data voltage with the common voltage;

[0017] When the data voltage is greater than the common voltage, determine that the polarity of the data voltage is positive;

[0018] When the data voltage is less than the common voltage, determine that the polarity of the data voltage is negative.

[0019] In a feasible embodiment of the present application, determining the gray-scale interval to which the gray-scale value of the data voltage belongs includes:

[0020] Obtain a grayscale mapping table; wherein, the grayscale mapping table includes N sequentially increasing grayscale values, and N is an integer greater than 0;

[0021] Determine a first boundary grayscale value and a second boundary grayscale value according to the grayscale mapping table; wherein, the first boundary grayscale value is less than the second boundary grayscale value;

[0022] When the grayscale value of the data voltage is less than the first boundary grayscale value and greater than 0, determine that the grayscale value of the data voltage belongs to the first grayscale interval;

[0023] When the grayscale value of the data voltage is less than the maximum grayscale value in the grayscale mapping table and greater than the second boundary grayscale value, determine that the grayscale value of the data voltage belongs to the second grayscale interval.

[0024] In a feasible embodiment of the present application, determining the first boundary grayscale value and the second boundary grayscale value according to the grayscale mapping table includes:

[0025] Determine the nth grayscale value in the grayscale mapping table as the first boundary grayscale value; wherein, n = F(N / 4), and F() is a floor function;

[0026] Determine the mth grayscale value in the grayscale mapping table as the second boundary grayscale value; wherein, m = H(3N / 4), and H() is a ceiling function.

[0027] In a second aspect, the present application provides a driving circuit for a display panel. The circuit includes a source driving module, a comparison module, and a timing control module. One end of the source driving module is connected to one end of the comparison module, and the other end of the comparison module is connected to one end of the timing control module, wherein:

[0028] The source driving module is configured to output a data voltage of the current frame to the comparison module;

[0029] The comparison module is configured to determine whether the data voltage is a first data voltage or a second data voltage according to the polarity and grayscale value of the data voltage, and output a timing control signal to the timing control module according to the data voltage; wherein, the feed-through voltage generated when the first data voltage is written into the pixel unit is greater than the feed-through voltage generated when the second data voltage is written into the pixel unit;

[0030] The timing control module is configured to generate a first timing signal or a second timing signal, and write the first data voltage into the pixel unit using the first timing signal and write the second data voltage into the pixel unit using the second timing signal according to the timing control signal; wherein, the first timing signal is delayed by a preset time relative to the second timing signal.

[0031] In a feasible embodiment of the present application, the comparison module is configured to:

[0032] When the polarity of the data voltage and the gray-scale value satisfy a first judgment condition, determine the data voltage as the first data voltage; wherein, the first judgment condition is that the polarity of the data voltage is positive and the gray-scale value of the data voltage belongs to the first gray-scale interval, or the polarity of the data voltage is negative and the gray-scale value of the data voltage belongs to the second gray-scale interval, and the gray-scale values in the first gray-scale interval are all smaller than the gray-scale values in the second gray-scale interval;

[0033] When the polarity of the data voltage and the gray-scale value satisfy a second judgment condition, determine the data voltage as the second data voltage; wherein, the second judgment condition is that the polarity of the data voltage is positive and the gray-scale value of the data voltage does not belong to the first gray-scale interval, or the polarity of the data voltage is negative and the gray-scale value of the data voltage does not belong to the second gray-scale interval.

[0034] In a feasible embodiment of the present application, the comparison module includes a comparison circuit, and the comparison circuit includes a first switch unit, a second switch unit, a first comparator, a second comparator, a third comparator, and an exclusive-OR gate, wherein:

[0035] The non-inverting input terminal of the first comparator is connected to the data voltage output terminal of the source driver module, the inverting input terminal of the first comparator is connected to the common electrode, and the output terminal of the first comparator is respectively connected to the first input terminal of the exclusive-OR gate, the control terminal of the first switch unit, and the control terminal of the second switch unit; wherein, the data voltage output terminal of the source driver module is used to output the data voltage, and the common electrode is used to output the common voltage;

[0036] The inverting input terminal of the second comparator is connected to the first terminal of the first switch unit, the non-inverting input terminal of the second comparator is connected to the gamma voltage output terminal of the source driver module, the output terminal of the second comparator is connected to the second input terminal of the exclusive-OR gate, and the second terminal of the first switch unit is connected to the data voltage output terminal of the source driver module; wherein, the gamma voltage output terminal of the source driver module is used to output the standard gamma voltage;

[0037] The inverting input terminal of the third comparator is connected to the first terminal of the second switch unit, the non-inverting input terminal of the third comparator is connected to the gamma voltage output terminal of the source driver module, the output terminal of the third comparator is connected to the second input terminal of the exclusive-OR gate, and the second terminal of the second switch unit is connected to the data voltage output terminal of the source driver module;

[0038] The output terminal of the exclusive - OR gate is connected to the timing control module.

[0039] In a feasible embodiment of the present application, the first switching unit includes an NMOS transistor. The gate of the NMOS transistor serves as the control terminal of the first switching unit and is connected to the output terminal of the first comparator. The drain of the NMOS transistor serves as the first terminal of the first switching unit and is connected to the inverting input terminal of the second comparator. The source of the NMOS transistor serves as the second terminal of the first switching unit and is connected to the data voltage output terminal of the source driver module.

[0040] The second switching unit includes a PMOS transistor. The gate of the PMOS transistor serves as the control terminal of the second switching unit and is connected to the output terminal of the first comparator. The drain of the PMOS transistor serves as the first terminal of the second switching unit and is connected to the inverting input terminal of the third comparator. The source of the PMOS transistor serves as the second terminal of the second switching unit and is connected to the data voltage output terminal of the source driver module.

[0041] In a third aspect, the present application provides a display panel, and the display panel includes a driving circuit of the display panel as described in any one of the embodiments of the second aspect above.

[0042] The above - mentioned technical solutions provided by the embodiments of the present application have the following advantages compared with the prior art:

[0043] It can be understood that the effective voltage of the pixel unit is actually composed of two parts: the charging voltage (the voltage actually acting on the pixel unit) and the feed - through voltage. The difference in the feed - through voltage at different gray levels leads to a difference in the effective voltage. When the effective voltage is not consistent with the target gray - scale voltage, the ghosting phenomenon occurs.

[0044] In the technical solution provided by the present application, the data voltage of the current frame is distinguished. According to the polarity and gray - scale value of the data voltage, it is determined whether the data voltage is a first data voltage or a second data voltage, so as to judge whether an excessive feed - through voltage will be generated when the data voltage is written into the pixel unit. When the data voltage is the first data voltage, it is written through the first timing signal, reducing the charging time of the first data voltage to the pixel unit, thereby reducing the charging voltage and compensating for the excessive feed - through voltage. When the data voltage is the second data voltage, it is written through the second timing signal, making the charging time of the second data voltage more standard and the charging voltage not decreasing.

[0045] It can be seen that, through the technical solution provided by the present application, the charging voltage is changed by changing the charging time, so that the charging voltage and the feed-through voltage form complementary cancellation at different gray levels, and finally the effective voltages at each gray level tend to be as consistent as possible, solving the technical problem that the correction solution in the prior art cannot cover the full gray level range well, resulting in local afterimage phenomena still occurring when non-specific gray levels change. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application and, together with the specification, are used to explain the principles of the present application.

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0048] One or more embodiments are illustrated by way of example in the pictures in the corresponding accompanying drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, unless otherwise stated, and the drawings in the figures do not constitute a scale limitation.

[0049] Figure 1 It is a schematic flowchart of a driving method for a display panel provided by an embodiment of the present application;

[0050] Figure 2 It is a schematic diagram of the correspondence between timing signals and data voltages in a driving method for a display panel provided by an embodiment of the present application;

[0051] Figure 3 It is a schematic structural diagram of a driving circuit for a display panel provided by an embodiment of the present application;

[0052] Figure 4 It is a schematic structural diagram of a comparison circuit in a driving circuit for a display panel provided by an embodiment of the present application;

[0053] Figure 5 It is a schematic structural diagram of a display panel provided by an embodiment of the present application.

[0054] Description of the reference numerals in the drawings:

[0055] 1. Source driving module; 2. Comparison module; 3. Timing control module; 4. Comparison circuit; 41. First switch unit; 42. Second switch unit; U1. First comparator; U2. Second comparator; U3. Third comparator; U4. Exclusive-OR gate; Q1. NMOS transistor; Q2. PMOS transistor. Detailed implementation manners

[0056] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0057] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or letters in different examples. This repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0058] To solve the technical problem that the correction solution of the prior art cannot cover the full gray scale range well, resulting in local ghosting phenomenon still occurring when there is a non-specific gray scale change, the present application provides a driving method, a driving circuit and a display panel of a display panel, which can eliminate the ghosting phenomenon under the full gray scale.

[0059] To more clearly illustrate the technical solution provided by the present application, the generation principle of the ghosting phenomenon is first explained in detail.

[0060] Figure 1 is a schematic flowchart of a driving method of a display panel provided by an embodiment of the present application. Referring to Figure 1 , a driving method of a display panel provided by an embodiment of the present application includes the following steps:

[0061] S1: Obtain the data voltage of the current frame;

[0062] Specifically, the data voltage is generated by a driving chip (Driver IC) of the display panel. The driving chip generates a corresponding data voltage according to the digital signal transmitted by a timing controller (TCON), so as to control the pixel unit to perform display.

[0063] When the display panel needs to display a frame of picture, obtain the data voltage corresponding to the current frame from the driving chip.

[0064] S2: Determine whether the data voltage is a first data voltage or a second data voltage according to the polarity and gray scale value of the data voltage; wherein, the feed-through voltage generated when the first data voltage is written into the pixel unit is greater than the feed-through voltage generated when the second data voltage is written into the pixel unit;

[0065] Specifically, after obtaining the data voltage of the current frame, the data voltage is classified according to the polarity and gray-scale value of the data voltage, and the data voltage is identified as the first data voltage or the second data voltage. The feed-through voltage generated when the first data voltage is written into the pixel unit is greater than the feed-through voltage generated when the second data voltage is written into the pixel unit.

[0066] In a feasible embodiment of the present application, determining that the data voltage is the first data voltage or the second data voltage according to the polarity and gray-scale value of the data voltage includes:

[0067] Determine the polarity of the data voltage and determine the gray-scale interval to which the gray-scale value of the data voltage belongs; wherein, the polarity of the data voltage is positive or negative, the gray-scale interval is the first gray-scale interval or the second gray-scale interval, and the gray-scale values in the first gray-scale interval are all smaller than the gray-scale values in the second gray-scale interval;

[0068] When the polarity and gray-scale value of the data voltage satisfy the first judgment condition, determine that the data voltage is the first data voltage; wherein, the first judgment condition is that the polarity of the data voltage is positive and the gray-scale value of the data voltage belongs to the first gray-scale interval, or the polarity of the data voltage is negative and the gray-scale value of the data voltage belongs to the second gray-scale interval;

[0069] When the polarity and gray-scale value of the data voltage satisfy the second judgment condition, determine that the data voltage is the second data voltage; wherein, the second judgment condition is that the polarity of the data voltage is positive and the gray-scale value of the data voltage does not belong to the first gray-scale interval, or the polarity of the data voltage is negative and the gray-scale value of the data voltage does not belong to the second gray-scale interval.

[0070] Specifically, since the gray-scale value of the data voltage will specifically affect the value of the feed-through voltage generated when the data voltage acts on the pixel unit, and the influence of the gray-scale value of the data voltage on data voltages of different polarities is different, the data voltage is determined as the first data voltage or the second data voltage according to the polarity and gray-scale value of the data voltage, so as to determine whether the data voltage will generate a large feed-through voltage on the pixel unit.

[0071] The polarity of the data voltage is positive or negative, the gray-scale value of the data voltage belongs to the first gray-scale interval or the second gray-scale interval, and the gray-scale values in the first gray-scale interval are all smaller than the gray-scale values in the second gray-scale interval.

[0072] When the polarity of the data voltage is positive and the gray-scale value of the data voltage belongs to the first gray-scale interval, or the polarity of the data voltage is negative and the gray-scale value of the data voltage belongs to the second gray-scale interval, it is determined that a large feed-through voltage will be generated when the data voltage acts on the pixel unit, and at this time, the data voltage is determined as the first data voltage.

[0073] When the polarity of the data voltage is positive and the gray scale value of the data voltage does not belong to the first gray scale interval, or when the polarity of the data voltage is negative and the gray scale value of the data voltage does not belong to the second gray scale interval, it is determined that a large feed-through voltage will not be generated when the data voltage acts on the pixel unit. At this time, the data voltage is determined to be the second data voltage.

[0074] In a feasible embodiment of the present application, the polarity of the data voltage is determined based on the numerical relationship between the data voltage and the common voltage.

[0075] In this embodiment, the common voltage is obtained from the common electrode, and the common voltage is compared with the data voltage. When the data voltage is greater than the common voltage, the polarity of the data voltage is determined to be positive, and when the data voltage is less than the common voltage, the polarity of the data voltage is determined to be negative.

[0076] As a specific example, when the driving chip generates a data voltage, the driving chip synchronously obtains the common voltage, and compares the common voltage with the data voltage through a comparator set in the driving chip, so as to determine the polarity of the data voltage.

[0077] In a feasible embodiment of the present application, the gray scale interval to which the gray scale value of the data voltage belongs is determined based on the relationship between the data voltage and the first boundary gray scale value and the second boundary gray scale value.

[0078] In this embodiment, a gray scale mapping table is obtained; wherein, the gray scale mapping table includes N sequentially increasing gray scale values, and N is an integer greater than 0; the first boundary gray scale value and the second boundary gray scale value are determined according to the gray scale mapping table; wherein, the first boundary gray scale value is less than the second boundary gray scale value; when the gray scale value of the data voltage is less than the first boundary gray scale value and greater than 0, it is determined that the gray scale value of the data voltage belongs to the first gray scale interval; when the gray scale value of the data voltage is less than the maximum gray scale value in the gray scale mapping table and greater than the second boundary gray scale value, it is determined that the gray scale value of the data voltage belongs to the second gray scale interval.

[0079] Specifically, the gray scale mapping table includes N sequentially increasing gray scale values, and each gray scale value corresponds to a specific gamma voltage. The first boundary gray scale value and the second boundary gray scale value are determined based on the gray scale mapping table, so as to determine the gray scale interval where the gray scale value of the data voltage is located based on the relationship between the gray scale value of the data voltage and the first boundary gray scale value and the second boundary gray scale value.

[0080] It can be understood that, denoting the first boundary gray scale value as gamma a, the second boundary gray scale value as gamma b, and the maximum gray scale value in the gray scale mapping table as gamma c, then the first gray scale interval is actually (0, gamma a), and the second gray scale interval is actually (gamma b, gamma c).

[0081] As a specific example, a digital signal is obtained from a timing controller, and the gray scale value of a data voltage is directly identified from the digital signal. The gray scale interval in which the gray scale value of the data voltage is located is determined based on the numerical relationship between the gray scale value of the data voltage and a first boundary gray scale value and a second boundary gray scale value.

[0082] As a specific example, the amplitudes of a first gamma voltage and a second gamma voltage are determined based on a gray scale mapping table. The first gamma voltage is the gamma voltage corresponding to the first boundary gray scale value, and the second gamma voltage is the gamma voltage corresponding to the second boundary gray scale value. The gray scale interval in which the gray scale value of the data voltage is located is determined by comparing the amplitude of the data voltage with the amplitudes of the first gamma voltage and the second gamma voltage.

[0083] In a feasible embodiment of the present application, it is necessary to accurately determine the first boundary gray scale value and the second boundary gray scale value, so as to screen out a data voltage with a relatively large feed-through voltage when acting on a pixel unit as a first data voltage. In this embodiment, determining the first boundary gray scale value and the second boundary gray scale value according to the gray scale mapping table includes:

[0084] Determine the nth gray scale value in the gray scale mapping table as the first boundary gray scale value; where n = F(N / 4), and F() is a floor function;

[0085] Determine the mth gray scale value in the gray scale mapping table as the second boundary gray scale value; where m = H(3N / 4), and H() is a ceiling function.

[0086] Specifically, for the N gray scale values in the gray scale mapping table, usually the gamma voltages corresponding to the first N / 2 gray scale values are positive polarity, and the gamma voltages corresponding to the last N / 2 gray scale values are negative polarity.

[0087] Select the nth gray scale value as the first boundary gray scale value, n = F(N / 4), and F() is a floor function, that is, for a data voltage with positive polarity, determine a data voltage with a lower gray scale value as the first data voltage; select the mth gray scale value as the second boundary gray scale value, m = H(3N / 4), and H() is a ceiling function, that is, for a data voltage with negative polarity, determine a data voltage with a higher gray scale value as the first data voltage.

[0088] In some practical examples, if there are 14 gray scale values (gm1 - gm14) in the gray scale mapping table, then the first boundary gray scale value n = F(14 / 4) = 3, and gm3 is selected as the first boundary gray scale value, and the second boundary gray scale value m = F(3×14 / 4) = 11, and gm11 is selected as the second boundary gray scale value.

[0089] It can be understood that, generally speaking, the gamma voltages corresponding to the front - segment gray - scale values (i.e., gm0 - gmN / 2) in the gray - scale mapping table are positive - polarity voltages, and the gamma voltages corresponding to the back - segment gray - scale values (i.e., gmN / 2 - gmN) in the gray - scale mapping table are positive - polarity voltages. Through the above - mentioned embodiments, the boundary is adaptively divided according to the total length of the gray - scale mapping table, which is compatible with different - resolution panel designs, avoids the adaptation problems caused by artificially preset parameters, and improves the universality of the solution.

[0090] Based on the above - mentioned various embodiments, it can be understood that the first data voltage is actually the data voltage of positive - polarity low gray - scale and the data voltage of negative - polarity high gray - scale, and the second data voltage is actually the data voltage of positive - polarity high gray - scale and the data voltage of negative - polarity low gray - scale.

[0091] S3: When the data voltage is the first data voltage, write the first data voltage into the pixel unit using the first timing signal; and when the data voltage is the second data voltage, write the second data voltage into the pixel unit using the second timing signal; wherein, the first timing signal is delayed by a preset time relative to the second timing signal.

[0092] Specifically, after determining the category of the data voltage, write the data voltage into the pixel unit through different timing signals. When the data voltage is the first data voltage, write the first data voltage into the pixel unit using the first timing signal. When the data voltage is the second data voltage, write the second data voltage into the pixel unit using the second timing signal. The first timing signal is delayed by a preset time relative to the second timing signal.

[0093] As a specific example, the first timing signal is delayed by 0.5 - 2 μs relative to the second timing signal.

[0094] Figure 2 It is a schematic diagram of the correspondence between the timing signal and the data voltage in a driving method of a display panel provided by an embodiment of the present application. Referring to Figure 2 , when the data voltage is the first data voltage, that is, when the data voltage is the data voltage of positive - polarity low gray - scale (V0+) or negative - polarity high gray - scale (V255 -), under the control of the first timing signal, the charging time of the first data voltage to the pixel unit is significantly insufficient, which makes the charging voltage of the pixel unit smaller.

[0095] When the data voltage is the second data voltage, that is, when the data voltage is the data voltage of positive - polarity high gray - scale (V255+) or negative - polarity low gray - scale (V0 -), or when the data voltage is the data voltage of positive - polarity middle gray - scale (V64+) or negative - line middle gray - scale (V64 -), under the control of the second timing signal, the charging time of the second data voltage to the pixel unit is sufficient, which makes the charging voltage of the pixel unit normal.

[0096] Since the effective voltage of the pixel unit depends on the charging voltage and the feed-through voltage, when the data voltage is the first data voltage and the feed-through voltage is large, the large feed-through voltage can be compensated by reducing the charging voltage. When the data voltage is the second data voltage and the feed-through voltage is small, no compensation is required.

[0097] In this way, the effective voltages of the first data voltage and the second data voltage when writing to the pixel unit tend to be the same. Regardless of the gray level of the data voltage in the current frame, the feed-through voltage changed due to the gray level will be compensated by the charging voltage that changes synchronously, making the effective voltages of the pixel units under each gray level basically the same, thereby avoiding the generation of the ghosting phenomenon.

[0098] Through the technical solution provided by this application, the charging time is changed to change the charging voltage, so that the charging voltage and the feed-through voltage form complementary cancellation under different gray levels, and finally the effective voltages under each gray level tend to be the same as much as possible, solving the technical problem that the correction scheme of the prior art cannot cover the full gray level range well, resulting in local ghosting phenomena still occurring when the non-specific gray level changes.

[0099] Figure 3 The following is a schematic structural diagram of a driving circuit of a display panel provided by an embodiment of this application. An embodiment of this application also provides a driving circuit of a display panel. Referring to Figure 3 Figure, the device includes a source driving module 1, a comparison module 2, and a timing control module 3. One end of the source driving module 1 is connected to one end of the comparison module 2, and the other end of the comparison module 2 is connected to one end of the timing control module 3, where:

[0100] The source driving module 1 is used to output the data voltage of the current frame to the comparison module 2.

[0101] The comparison module 2 is used to determine whether the data voltage is the first data voltage or the second data voltage according to the polarity and gray level value of the data voltage, and output a timing control signal to the timing control module 3 according to the data voltage; among them, the feed-through voltage generated when the first data voltage is written to the pixel unit is greater than the feed-through voltage generated when the second data voltage is written to the pixel unit.

[0102] The timing control module 3 is used to generate a first timing signal or a second timing signal, and write the first data voltage to the pixel unit using the first timing signal and write the second data voltage to the pixel unit using the second timing signal according to the timing control signal; among them, the first timing signal is delayed by a preset time relative to the second timing signal.

[0103] Specifically, the source driving module 1 generates a data voltage based on a digital signal and outputs the data voltage value to the comparison module 2. As a specific example, the source driving module 1 may specifically be a driving chip (Drive IC) in the display panel.

[0104] The comparison module 2 classifies the data voltage to determine whether the data voltage is the first data voltage or the second data voltage, and simultaneously outputs a corresponding timing control signal to the timing control module 3 according to the category of the data voltage. In a feasible embodiment of the present application, when the comparison module 2 determines that the data voltage is the first data voltage, it outputs a first timing control signal to the timing control module 3, and when the comparison module 2 determines that the data voltage is the second data voltage, it outputs a second timing control signal to the timing control module 3.

[0105] Two timing signals are generated in the timing control module 3, namely the first timing signal or the second timing signal, and the first timing signal is delayed by a preset time relative to the second timing signal. The timing control module 3 selects the first timing signal or the second timing signal based on the received timing control signal, so as to write the first data voltage into the pixel unit using the first timing signal and write the second data voltage into the pixel unit using the second timing signal. As a specific example, the timing control module 3 may specifically be a timing controller (TCON) in the display panel.

[0106] In a feasible embodiment of the present application, the timing control module 3 determines whether to select the first timing signal or the second timing signal through the timing control signal. When the timing control module 3 receives the first timing control signal, it writes the data voltage into the pixel unit through the first timing signal, and when the timing control module 3 receives the second timing control signal, it writes the data voltage into the pixel unit through the second timing signal.

[0107] Based on the above embodiments, the driving circuit provided by the embodiments of the present application is significantly different from the prior art. The driving circuit provided by the embodiments of the present application additionally sets a comparison module to achieve accurate classification of the data voltage and determine the data voltage as the first data voltage and the second data voltage.

[0108] At the same time, the driving circuit provided by the embodiments of the present application additionally sets a timing signal in the timing control module, and jointly uses the first timing signal and the second timing signal to achieve the writing control of the data voltage, thereby completing the compensation of the effective voltage at different gray levels. Figure 4 FIG. is a schematic structural diagram of a comparison circuit 4 in a driving circuit of a display panel provided by an embodiment of the present application. Refer to Figure 4 In a feasible embodiment of the present application, the comparison module 2 includes a comparison circuit 4, and the comparison circuit 4 includes a first switch unit 41, a second switch unit 42, a first comparator U1, a second comparator U2, a third comparator U3, and an exclusive-OR gate U4, where:

[0109] The non-inverting input terminal of the first comparator U1 is connected to the data voltage output terminal of the source driver module 1, the inverting input terminal of the first comparator U1 is connected to the common electrode, and the output terminal of the first comparator U1 is respectively connected to the first input terminal of the exclusive-OR gate U4, the control terminal of the first switch unit 41, and the control terminal of the second switch unit 42; wherein, the data voltage output terminal of the source driver module 1 is used to output a data voltage, and the common electrode is used to output a common voltage;

[0110] The inverting input terminal of the second comparator U2 is connected to the first terminal of the first switch unit 41, the non-inverting input terminal of the second comparator U2 is connected to the gamma voltage output terminal of the source driver module 1, the output terminal of the second comparator U2 is connected to the second input terminal of the exclusive-OR gate U4, and the second terminal of the first switch unit 41 is connected to the data voltage output terminal of the source driver module 1; wherein, the gamma voltage output terminal of the source driver module 1 is used to output a standard gamma voltage;

[0111] The inverting input terminal of the third comparator U3 is connected to the first terminal of the second switch unit 42, the non-inverting input terminal of the third comparator U3 is connected to the gamma voltage output terminal of the source driver module 1, the output terminal of the third comparator U3 is connected to the second input terminal of the exclusive-OR gate U4, and the second terminal of the second switch unit 42 is connected to the data voltage output terminal of the source driver module 1;

[0112] The output terminal of the exclusive-OR gate U4 is connected to the timing control module 3.

[0113] Specifically, the non-inverting input terminal of the first comparator U1 is connected to the data voltage output terminal of the source driver module 1, and the inverting input terminal of the first comparator U1 is connected to the common electrode. The first comparator U1 receives the data voltage through the non-inverting input terminal, receives the common voltage through the inverting input terminal, and outputs different output signals according to the numerical relationship between the data voltage and the common voltage.

[0114] It can be seen that the first comparator U1 realizes the judgment of the polarity of the data voltage. Using the common voltage as a reference point, the polarity is determined in real time through the first comparator U1, which simplifies the polarity recognition logic. Compared with the scheme that relies on digital signal analysis, this embodiment has a faster response speed, avoids misjudgment caused by signal transmission delay, and ensures the real-time performance and accuracy of polarity classification.

[0115] At the same time, the output terminal of the first comparator U1 is respectively connected to the control terminal of the first switch unit 41 and the control terminal of the second switch unit 42. The first comparator U1 changes the conduction states of the first switch unit 41 and the second switch unit 42 by outputting signals to the control terminal of the first switch unit 41 and the control terminal of the second switch unit 42, thereby controlling the working conditions of the second comparator U2 and the third comparator U3.

[0116] In a feasible embodiment of the present application, the control terminal of the first switch unit 41 is turned on when receiving a high-level signal and turned off when receiving a low-level signal.

[0117] As a specific example, the first switch unit 41 includes an NMOS transistor Q1. The gate of the NMOS transistor Q1 serves as the control terminal of the first switch unit 41 and is connected to the output terminal of the first comparator U1. The drain of the NMOS transistor Q1 serves as the first terminal of the first switch unit 41 and is connected to the inverting input terminal of the second comparator U2. The source of the NMOS transistor Q1 serves as the second terminal of the first switch unit 41 and is connected to the data voltage output terminal of the source driving module 1.

[0118] In other examples, the first switch unit 41 can also be a triode, an electric control switch, or other devices, as long as it can be turned on when receiving a high-level signal and turned off when receiving a low-level signal.

[0119] In a feasible embodiment of the present application, the control terminal of the second switch unit 42 is turned on when receiving a low-level signal and turned off when receiving a high-level signal.

[0120] As a specific example, the second switch unit 42 includes a PMOS transistor Q2. The gate of the PMOS transistor Q2 serves as the control terminal of the second switch unit 42 and is connected to the output terminal of the first comparator U1. The drain of the PMOS transistor Q2 serves as the first terminal of the second switch unit 42 and is connected to the inverting input terminal of the third comparator U3. The source of the PMOS transistor Q2 serves as the second terminal of the second switch unit 42 and is connected to the data voltage output terminal of the source driving module 1.

[0121] In other examples, the second switch unit 42 can also be a triode, an electric control switch, or other devices, as long as it can be turned on when receiving a low-level signal and turned off when receiving a high-level signal.

[0122] The inverting input terminal of the second comparator U2 is connected to the first terminal of the first switch unit 41, and the non-inverting input terminal of the second comparator U2 is connected to the gamma voltage output terminal of the source driving module 1. When the first switch unit 41 is turned on, the second comparator U2 compares the data voltage input from the inverting input terminal with the standard gamma voltage input from the non-inverting input terminal, and outputs different output signals according to the numerical relationship between the data voltage and the standard gamma voltage.

[0123] The inverting input terminal of the third comparator U3 is connected to the first end of the second switch unit 42, and the non-inverting input terminal of the third comparator U3 is connected to the gamma voltage output terminal of the source driver module 1. When the second switch unit 42 is turned on, the third comparator U3 compares the data voltage input from the inverting input terminal with the standard gamma voltage input from the non-inverting input terminal, and outputs different output signals according to the numerical relationship between the data voltage and the standard gamma voltage.

[0124] It can be seen that the second comparator U2 and the third comparator U3 realize the judgment of the gray level interval to which the gray level value of the data voltage belongs.

[0125] The exclusive-OR gate U4 outputs different timing control signals to the timing controller according to the output signals of the first comparator U1, the second comparator U2, and the third comparator U3. Through the exclusive-OR gate U4, different timing control signals can be output to the timing controller when the categories of the data voltages are different.

[0126] In the above embodiment, the positive polarity path is controlled by the first switch unit 41, the negative polarity path is controlled by the second switch unit 42, and the timing control signal is output in combination with the exclusive-OR gate U4, with low hardware complexity and low power consumption. Multiple comparators work together to achieve double verification of the gray level interval and polarity, ensuring that the compensation action is triggered only under the necessary polarity and gray level, and reducing the power consumption waste caused by invalid timing adjustment.

[0127] Refer to Figure 4 , the data voltage is marked as Data, the common voltage is marked as Vcom, the standard gamma voltage includes the first standard gamma voltage and the second standard gamma voltage, the first standard gamma voltage is marked as gmA, the second standard gamma voltage is marked as gmB, the output signal of the first comparator U1 is marked as Sel1, the output signal of the second comparator U2 is marked as Sel2, the output signal of the third comparator U3 is marked as Sel3, and the output signal of the exclusive-OR gate U4 is marked as Sel4.

[0128] For the data voltage with positive polarity and low gray level (i.e., the first data voltage), Data is greater than Vcom and Data is less than gmA. At this time, Sel1 is a high-level signal, which makes the first switch unit 41 turn on, the second switch unit 42 turn off, and Sel2 is a low-level signal. The exclusive-OR gate U4 outputs a high-level signal to the timing controller according to Sel1 and Sel2.

[0129] For the data voltage with positive polarity and high gray level (i.e., the second data voltage), Data is greater than Vcom and Data is greater than gmA. At this time, Sel1 is a high-level signal, which makes the first switch unit 41 turn on, the second switch unit 42 turn off, and Sel2 is a high-level signal. The exclusive-OR gate U4 outputs a low-level signal to the timing controller according to Sel1 and Sel2.

[0130] When the data voltage is the data voltage of the negative high gray level (i.e., the first data voltage), Data is less than Vcom and Data is greater than gmB. At this time, Sel1 is a low-level signal, enabling the second switch unit 42 to conduct and the first switch unit 41 to cut off. Sel3 is a high-level signal. The exclusive-OR gate U4 outputs a high-level signal to the timing controller according to Sel1 and Sel2.

[0131] When the data voltage is the data voltage of the negative low gray level (i.e., the second data voltage), Data is less than Vcom and Data is less than gmB. At this time, Sel1 is a low-level signal, enabling the second switch unit 42 to conduct and the first switch unit 41 to cut off. Sel3 is a low-level signal. The exclusive-OR gate U4 outputs a low-level signal to the timing controller according to Sel1 and Sel2.

[0132] It can be seen that through the above comparison circuit 4, a high-level signal is output to the timing controller when the data voltage is the first data voltage, and a low-level signal is output to the timing controller when the data voltage is the second data voltage. The output signal of the comparison circuit 4 is the timing control signal, and this timing control signal is divided into the first timing control signal and the second timing control signal based on the level.

[0133] Based on the above circuit embodiment, the recognition of the data voltage is realized by the comparison module 2 arranged between the source driving module 1 and the timing control module 3. Based on a simple hardware circuit, it is determined that the data voltage is the first data voltage or the second data voltage, so as to realize the compensation of the effective voltage based on different categories of the data voltage, and eliminate the ghosting phenomenon in a more convenient way.

[0134] Figure 5 This is a schematic structural diagram of a display panel provided by an embodiment of the present application. An embodiment of the present application also provides a display panel. Refer to Figure 5 A display panel provided by an embodiment of the present application includes a display area and a non-display area. The non-display area surrounds the display area, and the driving circuit is arranged in the non-display area.

[0135] In another embodiment, it further includes a control board and a flip chip film. The control board is connected to the non-display area of the display panel through the flip chip film. The driving circuit of the display panel is disposed on the control board and the flip chip film. The display panel includes the driving circuit as described in any one of the above circuit embodiments. It should be understood that the terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" as used herein may also include the plural forms. The terms "include", "comprise", "contain", and "have" are inclusive and thus specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the particular order described or illustrated, unless the order of performance is explicitly stated. It should also be understood that additional or alternative steps may be used.

[0136] The above are only specific embodiments of the present application, enabling those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for driving a display panel, characterized in that: The method comprises: Get the data voltage of the current frame; Determining the data voltage as a first data voltage or a second data voltage according to the polarity and grayscale value of the data voltage; wherein the feed-through voltage generated when the first data voltage is written into the pixel unit is greater than the feed-through voltage generated when the second data voltage is written into the pixel unit; When the data voltage is the first data voltage, the first data voltage is written into the pixel unit using a first timing signal; and when the data voltage is the second data voltage, the second data voltage is written into the pixel unit using a second timing signal; wherein the first timing signal is delayed by a preset time relative to the second timing signal.

2. The method according to claim 1, characterized in that Determining the data voltage as a first data voltage or a second data voltage according to the polarity and the grayscale value of the data voltage includes: Determine the polarity of the data voltage, and determine the grayscale interval to which the grayscale value of the data voltage belongs; wherein the polarity of the data voltage is positive or negative, the grayscale interval is a first grayscale interval or a second grayscale interval, and the grayscale values ​​in the first grayscale interval are all smaller than the grayscale values ​​in the second grayscale interval; In the case where the polarity and the grayscale value of the data voltage meet a first judgment condition, determining that the data voltage is the first data voltage; wherein the first judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage belongs to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage belongs to the second grayscale interval; When the polarity and grayscale value of the data voltage meet the second judgment condition, the data voltage is determined to be the second data voltage; wherein the second judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage does not belong to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage does not belong to the second grayscale interval.

3. The method according to claim 2, characterized in that Determining the polarity of the data voltage includes: Get the common voltage; comparing the data voltage with the common voltage; In a case where the data voltage is greater than the common voltage, determining that the polarity of the data voltage is positive; In a case where the data voltage is lower than the common voltage, the polarity of the data voltage is determined to be a negative polarity.

4. The method according to claim 2, characterized in that: Determining the grayscale interval to which the grayscale value of the data voltage belongs includes: Obtain a grayscale mapping table; wherein the grayscale mapping table includes N grayscale values ​​that increase in sequence, and N is an integer greater than 0; Determine a first boundary grayscale value and a second boundary grayscale value according to the grayscale mapping table; wherein the first boundary grayscale value is smaller than the second boundary grayscale value; When the grayscale value of the data voltage is less than the first boundary grayscale value and greater than 0, determining that the grayscale value of the data voltage belongs to the first grayscale interval; When the grayscale value of the data voltage is smaller than the maximum grayscale value in the grayscale mapping table and larger than the second boundary grayscale value, it is determined that the grayscale value of the data voltage belongs to the second grayscale interval.

5. The method according to claim 4, characterized in that Determining a first boundary grayscale value and a second boundary grayscale value according to the grayscale mapping table includes: Determine that the nth grayscale value in the grayscale mapping table is the first boundary grayscale value; wherein n=F(N / 4), and F() is a floor rounding function; Determine that the mth grayscale value in the grayscale mapping table is the second boundary grayscale value; wherein, m=H(3N / 4), and H() is a rounding-up function.

6. A driving circuit for a display panel, characterized in that: The circuit includes a source driving module, a comparison module and a timing control module, one end of the source driving module is connected to one end of the comparison module, and the other end of the comparison module is connected to one end of the timing control module, wherein: The source driving module is used to output the data voltage of the current frame to the comparison module; The comparison module is used to determine whether the data voltage is the first data voltage or the second data voltage according to the polarity and grayscale value of the data voltage, and output a timing control signal to the timing control module according to the data voltage; wherein the feed-through voltage generated when the first data voltage is written into the pixel unit is greater than the feed-through voltage generated when the second data voltage is written into the pixel unit; The timing control module is used to generate a first timing signal or a second timing signal, and use the first timing signal to write the first data voltage into the pixel unit according to the timing control signal, and use the second timing signal to write the second data voltage into the pixel unit; wherein the first timing signal is delayed by a preset time relative to the second timing signal.

7. The circuit according to claim 6, characterized in that The comparison module is used for: In the case where the polarity and the grayscale value of the data voltage meet a first judgment condition, determining that the data voltage is the first data voltage; wherein the first judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage belongs to a first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage belongs to a second grayscale interval, and the grayscale values ​​in the first grayscale interval are all smaller than the grayscale values ​​in the second grayscale interval; When the polarity and grayscale value of the data voltage meet the second judgment condition, the data voltage is determined to be the second data voltage; wherein the second judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage does not belong to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage does not belong to the second grayscale interval.

8. The circuit according to claim 6, characterized in that The comparison module includes a comparison circuit, and the comparison circuit includes a first switch unit, a second switch unit, a first comparator, a second comparator, a third comparator and an XOR gate, wherein: The positive input terminal of the first comparator is connected to the data voltage output terminal of the source driving module, the negative input terminal of the first comparator is connected to the common electrode, and the output terminal of the first comparator is respectively connected to the first input terminal of the XOR gate, the control terminal of the first switch unit and the control terminal of the second switch unit; wherein the data voltage output terminal of the source driving module is used to output the data voltage, and the common electrode is used to output the common voltage; The inverting input terminal of the second comparator is connected to the first terminal of the first switch unit, the non-inverting input terminal of the second comparator is connected to the gamma voltage output terminal of the source driving module, the output terminal of the second comparator is connected to the second input terminal of the XOR gate, and the second terminal of the first switch unit is connected to the data voltage output terminal of the source driving module; wherein the gamma voltage output terminal of the source driving module is used to output a standard gamma voltage; The inverting input terminal of the third comparator is connected to the first terminal of the second switch unit, the non-inverting input terminal of the third comparator is connected to the gamma voltage output terminal of the source driving module, the output terminal of the third comparator is connected to the second input terminal of the XOR gate, and the second terminal of the second switch unit is connected to the data voltage output terminal of the source driving module; The output end of the XOR gate is connected to the timing control module.

9. The circuit according to claim 8, characterized in that: The first switch unit includes an NMOS tube, the gate of the NMOS tube is connected to the output end of the first comparator as the control end of the first switch unit, the drain of the NMOS tube is connected to the inverting input end of the second comparator as the first end of the first switch unit, and the source of the NMOS tube is connected to the data voltage output end of the source driving module as the second end of the first switch unit; The second switch unit includes a PMOS tube, the gate of the PMOS tube serves as the control end of the second switch unit and is connected to the output end of the first comparator, the drain of the PMOS tube serves as the first end of the second switch unit and is connected to the inverting input end of the third comparator, and the source of the PMOS tube serves as the second end of the second switch unit and is connected to the data voltage output end of the source driving module.

10. A display panel, comprising a display area and a non-display area, wherein the non-display area is arranged around the display area, and a driving circuit of the display panel is arranged on the non-display area of ​​the display panel, characterized in that: The driving circuit of the display panel includes the driving circuit as described in any one of claims 6 to 9.

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