Flash memory testing method

Abstract

The invention provides a test method of a flash memory, which comprises the following steps: after all memory units of the flash memory are erased and set to be 1, voltage is applied to perform floating gate defect screening, and the voltage difference between a source region and a bit line which are applied to the memory units through the test method is far greater than the voltage difference between the source region and the bit line in a terminal user operation mode; the source region voltage is coupled to the floating gate, and then the positive potential of the memory unit after erasing is superposed, so that the floating gate defect screening obtains the voltage difference between the floating gate and the bit line which is far greater than the voltage difference between the floating gate and the bit line in a terminal user operation mode, and the abnormal floating gate and the bit line of the memory unit are broken down and interconnected; 1 writing operation is carried out on the flash memory, 1 writing of the storage units of the array where the abnormal floating gate is located fails, and therefore the storage units of the array where the abnormal floating gate is located are screened out. And floating gate defect chips are screened out in a yield test stage and are not flowed to terminal users, so that the reliability risk of causing terminal failure is reduced. The reliability of the flash memory is improved, and the user mode use failure of the flash memory terminal is avoided.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a flash memory testing method. Background Art

[0002] Flash memory is an integrated circuit storage device that is widely used in electronic products such as portable computers, mobile phones, and digital music players because it has the function of electrically erasable storage of information and the stored information will not be lost after power failure.

[0003] like Figure 1 As shown, during the process of manufacturing a split-gate flash memory, due to defects in the process environment, some storage cells will have abnormal morphology. The storage structure on the left side of the groove 030 includes a first floating gate 011 and a first word line 012, and the storage structure on the right side of the groove 030 includes a second floating gate 021 and a second word line 022. The first floating gate 011 has a normal morphology, and the position of the first floating gate 011 facing the first word line 012 has a sharp corner, and there is a gap between the first floating gate 011 and the first word line 012. A bit line is formed in the groove 030. The second floating gate 021 (inside the yellow oval) has an abnormal morphology, and the position of the second floating gate 021 facing the second word line 022 does not form the sharp corner shape that it should have. Figure 1 An excess portion also grows on the left side of the second floating gate 021 in the middle yellow oval.

[0004] Normally, such defective memory cells will be screened out and repaired by the through-crosstalk test item during the yield test, and can be shipped and used normally. Although the defective memory cell is repaired in the yield test, other rows in the storage array still share the bit line with the defective memory cell and are not completely independent. Although it is shipped as a normal sample and put on the terminal market, due to the different shapes and sizes of defects, during the continuous use of the end user, the bit line of the defective memory cell has leakage due to this defect, causing the entire column of memory cells to fail when writing "1", thus becoming a terminal failure event. Summary of the invention

[0005] The purpose of the present invention is to provide a flash memory test method, after all the storage cells of the flash memory are erased and set to "1", a voltage floating gate defect screening is performed to break down the abnormal floating gate of the storage cell and the bit line interconnection, so that when the flash memory is written "1", the storage cells in the entire column where the abnormal floating gate is located fail to write "1", thereby screening out the storage cells in the entire column where the abnormal floating gate is located. The floating gate defective chips are screened out in the yield test stage and are not distributed to the end user, thereby reducing the reliability risk of causing terminal failure. The reliability of the flash memory is improved to avoid the failure of the flash memory in the end user mode.

[0006] The present invention provides a flash memory testing method, comprising:

[0007] A flash memory is provided, the flash memory comprising a memory cell array, the memory cell array comprising a plurality of memory cells arranged in a matrix, the memory cells being split-gate flash memory cells; each of the memory cells comprising a floating gate and a bit line; the memory cells in each column share the bit line;

[0008] Erasing the storage unit of the flash memory;

[0009] Performing a floating gate defect screening on the erased memory cell to break down and interconnect the abnormal floating gate of the memory cell with the bit line; the voltage difference between the source region and the bit line applied on the memory cell by the floating gate screening is higher than the voltage difference between the source region and the bit line applied when the end user actually uses the memory cell;

[0010] A write "1" operation is performed on the flash memory, and writing "1" to the storage cells in the entire column where the abnormal floating gate is located fails, thereby screening out the storage cells in the entire column where the abnormal floating gate is located.

[0011] Furthermore, the floating gate defect screening applies a voltage difference range of 8.6V to 9.4V between the source region and the bit line of the memory cell.

[0012] Furthermore, in the floating gate defect screening, the voltage test condition applied to the memory cell also includes: the source region voltage V S Range: 8.6V~9.4V; the bit line voltage V B Range: 0V~1V; the word line voltage V W Range: 0V~2V.

[0013] Furthermore, after providing the flash memory and before erasing the flash memory, the method further includes:

[0014] First test: short circuit, open circuit and leakage test; if the first test is qualified, it will flow into the second test; if the first test is unqualified, it will be rejected.

[0015] Furthermore, the second test includes: performing static power consumption test and dynamic power consumption test; if the second test is qualified, then flowing into the erasing step; if the second test is unqualified, then being eliminated.

[0016] Furthermore, the voltage condition for writing "1" operation includes: the source region voltage V S is 8.2V, the bit line voltage V B is 2.5V, the word line voltage V W is 1.6V.

[0017] Furthermore, after erasing the flash memory and before the floating gate defect screening, it also includes: performing a read operation on the erased storage unit, and judging whether the storage bit reaches the "1" state after erasing based on the read current; if the storage bit reaches the "1" state, erasing is successful and the floating gate defect screening is performed; if the storage bit does not reach the "1" state, erasing fails and the unit is removed.

[0018] Furthermore, after performing a write "1" operation on the flash memory, it also includes: performing a read operation on the storage unit after the write "1" operation, and judging whether the storage bit maintains the "1" state after writing "1" based on the read current; if the storage bit is maintained in the "1" state, the write "1" operation is successful; if the storage bit is in the "0" state, the write "1" operation fails and is discarded.

[0019] Furthermore, a split-gate flash memory unit includes two storage structures that share a common source region and are symmetrically distributed; the storage structure includes a drain region and the source region located in a substrate, the drain region is connected to the bit line, the floating gate and the word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on the side of the floating gate close to the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

[0020] Furthermore, the abnormal floating gate includes a situation where the floating gate tip that should be there is not formed on a side of the floating gate close to the word line.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] The present invention provides a flash memory test method. After all the storage cells of the flash memory are erased and set to "1", a voltage is applied to perform floating gate defect screening. The voltage difference between the source region and the bit line applied to the storage cell by the test method is much greater than the voltage difference between the source region and the bit line in the terminal user operation mode; the source region voltage is coupled to the floating gate, and then the positive potential of the storage cell after erasure is superimposed, so that the floating gate defect screening obtains a voltage difference between the floating gate and the bit line that is much greater than the voltage difference between the floating gate and the bit line in the terminal user operation mode, so as to break down and interconnect the abnormal floating gate and the bit line of the storage cell; the flash memory is written with a "1" operation, and the storage cells in the entire column where the abnormal floating gate is located fail to write "1", thereby screening out the storage cells in the entire column where the abnormal floating gate is located. The floating gate defective chips are screened out in the yield test stage and do not flow to the terminal user, thereby reducing the reliability risk of causing terminal failure. The reliability of the flash memory is improved, and the failure of the flash memory in the terminal user mode is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of a split-gate flash memory.

[0024] Figure 2The present invention is a flowchart of a flash memory testing method according to an embodiment of the present invention.

[0025] Figure 3 FIG. 4 is a schematic diagram of a flash memory according to an embodiment of the present invention.

[0026] Figure 4 FIG. 4 is a schematic diagram showing the principle of a flash memory according to an embodiment of the present invention.

[0027] The reference numerals are as follows:

[0028] 011-first floating gate; 012-first word line; 030-groove; 021-second floating gate; 022-second word line;

[0029] 11-floating gate; 12-word line; 13-bit line; 14-source region; 15-drain region; A-memory cell; B-memory cell with abnormal floating gate. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0031] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0032] The embodiment of the present invention provides a flash memory testing method, such as Figure 2 As shown, including:

[0033] Step S1, providing a flash memory, the flash memory comprising a memory cell array, the memory cell array comprising a plurality of memory cells arranged in a matrix, the memory cells being split-gate flash memory cells; each memory cell comprising a floating gate and a bit line; the memory cells in each column share a common bit line;

[0034] Step S2, erasing the storage unit of the flash memory;

[0035] Step S3, applying voltage to the memory cell after erasure to screen for floating gate defects, so as to break down the abnormal floating gate and the bit line for interconnection; the voltage difference between the source region and the bit line applied to the memory cell during floating gate screening is higher than the voltage difference between the source region and the bit line applied when the end user actually uses the memory cell;

[0036] Step S4, performing a write "1" operation on the flash memory, and writing "1" to the memory cells in the entire column where the abnormal floating gate is located fails, thereby screening out the memory cells in the entire column where the abnormal floating gate is located.

[0037] Combine the following Figure 3 and Figure 4 The steps of the flash memory testing method according to the embodiment of the present invention are described in detail.

[0038] Step S1: Figure 3 and Figure 4 As shown, a flash memory is provided, the flash memory includes a memory cell array, the memory cell array includes a plurality of memory cells A arranged in a matrix, the memory cells are split-gate flash memory cells; each memory cell includes a floating gate 11 and a bit line 13; the memory cells in each column share the bit line 13. A plurality of split-gate flash memory cells arranged in parallel are formed on a semiconductor substrate. The material of the semiconductor substrate may be silicon, germanium, silicon germanium or silicon carbide, etc., or may be silicon on insulator (SOI) or germanium on insulator (GOI), or may be other materials, such as III and V group compounds such as gallium arsenide.

[0039] In this embodiment, a split-gate flash memory unit includes two storage structures that share a source region 14 and are symmetrically distributed. Each split-gate flash memory unit includes a drain region 15 (connected to a bit line 13) formed in a semiconductor substrate, a source region 14, and a source line (not shown) connected to the source region 14 formed on the semiconductor substrate, and the source line is located above the source region 14. A word line 12 is formed between the source region 14 and the drain region 15. Two word lines 12 of the same split-gate flash memory unit are formed on both sides of the corresponding source line. A floating gate oxide layer, a floating gate 11, and a sidewall are formed on the semiconductor substrate between the source line and the word line 12. A tunneling oxide layer is formed between the floating gate 11 and the word line 12. The floating gate 11, the word line 12, and the source line can all be made of polysilicon. A floating gate tip is formed on one side of the floating gate 11 close to the word line 12. The storage structure on the left and the storage structure on the right are symmetrically distributed and share a source line. In this embodiment, the source region 14 and the drain region 15 are both N-type doped, for example.

[0040] When programming the split-gate flash memory cell, the word line 12 serves as a control gate, a high voltage is applied to the source region 14, a voltage that can open the channel is applied to the word line 12, and a constant current is injected through the drain region 15. The source region 14 is at a high potential. Under the action of the high potential, on the one hand, hot electrons are generated in the channel, and on the other hand, the high potential is coupled to the floating gate 11, and the floating gate 11 generates a coupling voltage. Under the action of the coupling voltage, electrons are injected from the channel to the floating gate 11, thereby realizing programming. Programming is also called a write "0" operation.

[0041] Next, the first test is performed: short circuit, open circuit and leakage test; if the first test is qualified, it will flow into the second test; if the first test is unqualified, it will be rejected.

[0042] Next, the second test is performed: static power consumption and dynamic power consumption test; if the second test is qualified, the system enters the erasing step; if the second test is unqualified, the system is eliminated.

[0043] Step S2, erasing the memory cell of the flash memory; when erasing the split-gate flash memory cell, a high voltage is applied to the word line 12, and the tip of the floating gate reduces the channel voltage of the tunneling effect through the tip discharge principle, so that electrons can pass through the tunneling oxide layer from the tip of the floating gate 11 to the word line 12. After the memory cell is erased, the storage bit of the memory cell is in the "1" state; that is, all the memory cells of the flash memory are erased and set to "1".

[0044] The erased memory cell is read; during the read operation, a voltage is applied to the bit line 13, and the source voltage V S is 0V, and a start voltage is applied to the word line 12. It is determined whether the storage bit reaches the "1" state after erasing based on the read current; if the storage bit reaches the "1" state, erasing is successful and floating gate defect screening is performed; if the storage bit does not reach the "1" state, erasing fails and is removed.

[0045] Step S3, applying voltage to the floating gate defect screening of the erased memory cell to break down the abnormal floating gate and the bit line interconnection; the voltage difference between the source region and the bit line applied to the memory cell during the floating gate screening is higher than the voltage difference between the source region and the bit line applied during actual use by the end user.

[0046] In floating gate defect screening, the voltage difference between the source region and the bit line applied to the memory cell ranges from 8.6V to 9.4V; the source region voltage V S Range: 8.6V~9.4V; bit line voltage V B Range: 0V~1V; word line voltage V W Range: 0V~2V.

[0047] Step S4, performing a write "1" operation on the flash memory, and writing "1" to the memory cells in the entire column where the abnormal floating gate is located fails, thereby screening out the memory cells in the entire column where the abnormal floating gate is located. Figure 4 A memory cell B with a floating gate abnormality is shown.

[0048] The memory cell array includes a plurality of memory cells A arranged in a matrix, some of which need to be programmed and some of which do not. By applying a programming voltage to the memory cells that need to be programmed, the electrons of the corresponding memory cells enter the floating gate 11 from the substrate channel to complete the programming. After programming, the storage bit of the memory cell is in the "0" state. Programming is also called a write "0" operation, which changes the storage bit from the "1" state to the "0" state.

[0049] The write "1" operation is to maintain the storage bit of the memory cell in the "1" state after erasure. Applying voltage to several memory cells that do not need to be programmed makes the memory cells not meet the programming conditions, the voltage of the channel is not turned on, and the electrons of the corresponding memory cell will not enter the floating gate 11 from the substrate. The storage bit of the memory cell is always in the "1" state, which is called the write "1" operation.

[0050] Exemplarily, the voltage conditions for writing a "1" operation include: source voltage V S is 8.2V, the bit line voltage V B is 2.5V, the word line voltage V W is 1.6V.

[0051] The floating gate of the memory cell B is abnormal. For example, the floating gate does not form the sharp corner shape it should have when facing the word line, and the floating gate grows an extra part on the side close to the word line. When the floating gate defective (abnormal) memory cell is first used, the source voltage V S and the bit line voltage V B The voltage difference is less than the channel opening voltage, and the corresponding electrons of the memory cell will not enter the floating gate 11 from the substrate, and the storage bit of the memory cell is always in the "1" state. During continuous use, the bit line 13 where the defective memory cell is located leaks electricity, resulting in the suppression voltage, that is, the bit line voltage V B is pulled low, and accordingly, the source voltage V S and the bit line voltage V B The voltage difference increases, when the source voltage V S and the bit line voltage V B When the voltage difference is greater than the channel opening voltage, the corresponding entire column of memory cells on the bit line will have electrons entering their respective floating gates 11 from the substrate, and then the entire column of memory cells is programmed to "0", that is, the storage bits of the entire column of memory cells are changed from the "1" state to the "0" state. Therefore, the memory cell with a floating gate defect has leakage between the bit line 13 and the floating gate during use, which causes the subsequent write "1" operation to fail and cannot be used normally.

[0052] The voltage difference between the source region 14 and the bit line 13 applied to the memory cell in the floating gate defect screening of the present invention is much greater than the voltage difference between the source region 14 and the bit line 13 in the terminal user operation mode; the source region voltage V S Pulling up, accordingly, the voltage of the source region 14 coupled to the floating gate 11 increases, and the voltage of the floating gate 11 increases, thereby increasing the voltage difference between the floating gate 11 and the bit line 13. The source region voltage is coupled to the floating gate, so that the floating gate defect screening obtains a voltage difference between the floating gate 11 and the bit line 13 that is much larger than that in the end-user operation mode, so as to break down and interconnect the abnormal floating gate of the storage unit with the bit line, so that when the flash memory is written "1", the storage unit in the entire column where the abnormal floating gate is located fails to write "1", thereby screening out the storage unit in the entire column where the abnormal floating gate is located.

[0053] In summary, the present invention provides a method for testing flash memory, after all the storage cells of the flash memory are erased and set to "1", a voltage is applied to perform floating gate defect screening, and the voltage difference between the source region and the bit line applied to the storage cell by the test method is much greater than the voltage difference between the source region and the bit line in the terminal user operation mode; the source region voltage is coupled to the floating gate, and then superimposed on the positive potential of the storage cell itself after erasure, so that the floating gate defect screening obtains a voltage difference between the floating gate and the bit line that is much greater than the voltage difference between the floating gate and the bit line in the terminal user operation mode, so as to break down and interconnect the abnormal floating gate of the storage cell and the bit line, so that when the flash memory is written "1", the storage cells in the entire column where the abnormal floating gate is located fail to write "1", thereby screening out the storage cells in the entire column where the abnormal floating gate is located. The floating gate defective chips are screened out in the yield test stage and do not flow to the terminal user, thereby reducing the reliability risk of causing terminal failure. The reliability of the flash memory is improved, and the failure of the flash memory in the terminal user mode is avoided.

[0054] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0055] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A flash memory testing method, characterized in that: include: A flash memory is provided, the flash memory comprising a memory cell array, the memory cell array comprising a plurality of memory cells arranged in a matrix, the memory cells being split-gate flash memory cells; each of the memory cells comprising a floating gate and a bit line; the memory cells in each column share the bit line; Erasing the storage unit of the flash memory; Performing a floating gate defect screening on the erased memory cell to break down and interconnect the abnormal floating gate of the memory cell with the bit line; the voltage difference between the source region and the bit line applied on the memory cell by the floating gate screening is higher than the voltage difference between the source region and the bit line applied when the end user actually uses the memory cell; A write "1" operation is performed on the flash memory, and writing "1" to the storage cells in the entire column where the abnormal floating gate is located is invalid, thereby screening out the storage cells in the entire column where the abnormal floating gate is located.

2. The flash memory testing method according to claim 1, wherein: The voltage difference between the source region and the bit line applied to the memory cell by the floating gate defect screening ranges from 8.6V to 9.4V.

3. The flash memory testing method according to claim 2, wherein: In the floating gate defect screening, the voltage test conditions applied to the storage unit also include: the source region voltage V S Range: 8.6V~9.4V; the bit line voltage V B Range: 0V~1V; the word line voltage V W Range: 0V~2V.

4. The flash memory testing method according to claim 1, wherein: After providing the flash memory, and before erasing the flash memory, the method further includes: First test: short circuit, open circuit and leakage test; if the first test is qualified, it will flow into the second test; if the first test is unqualified, it will be rejected.

5. The flash memory testing method according to claim 4, wherein: The second test includes: performing static power consumption test and dynamic power consumption test; if the second test is qualified, then entering into the erasing step; if the second test is unqualified, then being eliminated.

6. The flash memory testing method according to claim 3, wherein: The voltage conditions for writing "1" operation include: the source region voltage V S is 8.2V, the bit line voltage V B is 2.5V, the word line voltage V W is 1.6V.

7. The flash memory testing method according to claim 1, wherein: After erasing the flash memory and before screening for floating gate defects, the method further includes: A read operation is performed on the erased storage unit, and it is determined whether the storage bit reaches the "1" state after erasure based on the read current; if the storage bit reaches the "1" state, erasure is successful and the floating gate defect screening is performed; if the storage bit does not reach the "1" state, erasure fails and the unit is removed.

8. The flash memory testing method according to claim 7, wherein: After performing a write "1" operation on the flash memory, it also includes: performing a read operation on the storage unit after the write "1" operation, and judging whether the storage bit maintains the "1" state after writing "1" according to the read current; if the storage bit is maintained in the "1" state, the write "1" operation is successful; if the storage bit is in the "0" state, the write "1" operation fails and is discarded.

9. The flash memory testing method according to claim 1, wherein: A split-gate flash memory unit includes two storage structures that share a source region and are symmetrically distributed; the storage structure includes a drain region and the source region located in a substrate, the drain region is connected to the bit line, the floating gate and the word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on the side of the floating gate close to the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

10. The flash memory testing method according to claim 9, characterized in that: The abnormal floating gate includes a situation where the floating gate tip that should be there is not formed on a side of the floating gate close to the word line.

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