Method for testing flash memory

Abstract

The application provides a test method of flash memory. After all the storage units of the flash memory are erased to "1", a voltage is applied for floating gate defect screening. The voltage difference between the source region and the bit line of the storage unit by the test method is much larger than the voltage difference between the source region and the bit line in the end user operation mode. The source region voltage is coupled to the floating gate, and the positive potential of the storage unit after erasing is superimposed on the floating gate, so that the floating gate defect screening obtains a voltage difference between the floating gate and the bit line much larger than that in the end user operation mode, so as to break the interconnection of the abnormal floating gate and the bit line of the storage unit. The flash memory is written "1" operation, and the storage unit of the whole column where the abnormal floating gate is located is written "1" invalid, so as to screen out the storage unit of the whole column where the abnormal floating gate is located. The floating gate defect chip is screened out in the yield test stage, and does not flow to the end user, so as to reduce the reliability risk of causing end invalidation. The reliability of the flash memory is improved, and the invalidation of the flash memory in the end user mode is avoided.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, and specifically relates to a testing method for flash memory. Background Technology

[0002] Flash memory, as an integrated circuit storage device, is widely used in electronic products such as portable computers, mobile phones, and digital music players because it has the function of electrically erasable and rewritable storage of information, and the stored information will not be lost after power is turned off.

[0003] like Figure 1 As shown, during the manufacturing process of a multi-gate flash memory, some memory cells may exhibit abnormal morphologies due to process environment defects. The memory structure on the left side of trench 030 includes a first floating gate 011 and a first word line 012, while the memory structure on the right side of trench 030 includes a second floating gate 021 and a second word line 022. The first floating gate 011 has a normal morphology, but the position of the first floating gate 011 facing the first word line 012 has a sharp angle, and there is a gap between the first floating gate 011 and the first word line 012. Bit lines are formed in trench 030. The second floating gate 021 (within the yellow ellipse) has an abnormal morphology; the position of the second floating gate 021 facing the second word line 022 does not form the expected sharp angle shape. Figure 1 An extra portion also grew out to the left of the second floating gate 021 inside the yellow ellipse.

[0004] Normally, such defective memory cells are identified and repaired during yield testing using the punch-through crosstalk test, allowing for normal shipment and use. Although this defective memory cell is repaired during yield testing, other rows in the storage array still share bit lines with it, and it is not completely independent. Even though it is shipped as a normal sample to the end-user market, due to the varying size and shape of the defect, the bit lines of this defective memory cell may leak current during continuous use by end users. This can cause the entire row of memory cells to fail during write operations of "1", thus becoming an end-user failure event. Summary of the Invention

[0005] The purpose of this invention is to provide a flash memory testing method. After erasing all memory cells of the flash memory and setting them to "1", a voltage-based floating gate defect screening process is performed to identify abnormal floating gates and bit line interconnections in the memory cells. This ensures that when a write operation to "1" is performed on the flash memory, the write operation to the entire column of memory cells containing the abnormal floating gate fails, thus filtering out the entire column of memory cells with abnormal floating gates. This method filters out chips with floating gate defects during the yield testing stage, preventing them from reaching end users and reducing the reliability risk of end-user failure. It improves the reliability of flash memory and avoids flash memory failure during end-user mode use.

[0006] This invention provides a method for testing flash memory, comprising:

[0007] A flash memory is provided, the flash memory comprising a memory cell array, the memory cell array comprising a plurality of memory cells arranged in a matrix, the memory cells being grid-type flash memory cells; each memory cell comprising a floating gate and a bit line; the memory cells in each column sharing the bit line;

[0008] The storage cells of the flash memory are erased;

[0009] After erasing, the memory cell is subjected to voltage-applied floating gate defect screening to identify abnormal floating gates of the memory cell that are interconnected with the bit lines that have broken down. The voltage difference between the source region and the bit line applied to the memory cell during the floating gate screening is higher than the voltage difference applied between the source region and the bit line during actual use by the end user.

[0010] By performing a write "1" operation on the flash memory, the write "1" operation of the entire column of memory cells containing the abnormal floating gate fails, thereby filtering out the entire column of memory cells containing the abnormal floating gate.

[0011] Furthermore, the voltage difference between the source region and the bit line applied to the memory cell during the floating gate defect screening ranges from 8.6V to 9.4V.

[0012] Furthermore, in the floating gate defect screening, the voltage test conditions applied to the memory cell also include: the source region voltage V S Range: 8.6V~9.4V; the bit line voltage V B Range: 0V~1V; the word line voltage V W Range: 0V~2V.

[0013] Furthermore, after providing the flash memory, but before erasing the flash memory, the procedure also includes:

[0014] First test: Perform short circuit, open circuit and leakage current tests; if the first test is passed, proceed to the second test; if the first test is failed, discard.

[0015] Furthermore, the second test includes: performing static power consumption and dynamic power consumption tests; if the second test is qualified, it proceeds to the erasure step; if the second test is unqualified, it is rejected.

[0016] Furthermore, the voltage condition for the write "1" operation includes: the source region voltage V S The bit line voltage V is 8.2V. B The word line voltage V is 2.5V. W It is 1.6V.

[0017] Furthermore, after erasing the flash memory and before the floating gate defect screening, the process includes: performing a read operation on the erased storage cell, and determining whether the storage bit is in a "1" state after erasure based on the read current; if the storage bit is in a "1" state, the erasure is successful and the floating gate defect screening is performed; if the storage bit is not in a "1" state, the erasure fails and the cell is discarded.

[0018] Furthermore, after performing a write "1" operation on the flash memory, the method further includes: performing a read operation on the storage cell after the write "1" operation, and determining whether the storage bit remains in the "1" state after the write "1" based on the read current; if the storage bit remains in the "1" state, the write "1" operation is successful; if the storage bit is in the "0" state, the write "1" operation fails and is discarded.

[0019] Furthermore, one of the gate-type flash memory cells includes two memory structures that share a source region and are symmetrically distributed; the memory structure includes a drain region and the source region located in the substrate, the drain region is connected to the bit line, the floating gate and word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on the side of the floating gate near the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

[0020] Furthermore, the abnormal floating gate includes a situation where the floating gate tip that should be formed is not formed on the side of the floating gate near the word line.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] This invention provides a flash memory testing method. After erasing all memory cells of the flash memory to "1", a voltage is applied for floating gate defect screening. This testing method applies a voltage difference between the source region and the bit line on the memory cell that is significantly greater than the voltage difference between the source region and the bit line in end-user operation mode. The source region voltage is coupled to the floating gate, and then superimposed with the positive potential of the memory cell after erasure, resulting in a floating gate defect screening voltage difference that is significantly greater than that between the floating gate and the bit line in end-user operation mode. This effectively breaks down the abnormal floating gate and bit line interconnection of the memory cell. A write operation to "1" is then performed on the flash memory, causing the entire column of memory cells containing the abnormal floating gate to fail, thus filtering out the entire column of memory cells containing the abnormal floating gate. Floating gate defective chips are screened out during the yield testing stage, preventing them from reaching end users and reducing the reliability risk of end-user failure. This improves the reliability of flash memory and avoids flash memory failure during end-user operation. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a gate-divided flash memory.

[0024] Figure 2This is a schematic diagram of a flash memory testing method according to an embodiment of the present invention.

[0025] Figure 3 This is a schematic diagram of a flash memory according to an embodiment of the present invention.

[0026] Figure 4 This is a schematic diagram of the flash memory principle according to an embodiment of the present invention.

[0027] The accompanying figure is labeled as follows:

[0028] 011-First floating gate; 012-First letter line; 030-Groove; 021-Second floating gate; 022-Second letter line;

[0029] 11-Floating gate; 12-Word line; 13-Bit line; 14-Source region; 15-Drain region; A-Memory cell; B-Memory cell with floating gate malfunction. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0031] For ease of description, some embodiments of this application may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that these terms, as used, may be replaced where appropriate.

[0032] This invention provides a method for testing flash memory, such as... Figure 2 As shown, it includes:

[0033] Step S1: Provide flash memory, which includes a memory cell array. The memory cell array includes a plurality of memory cells arranged in a matrix. The memory cells are grid-type flash memory cells. Each memory cell includes a floating gate and a bit line. Each column of memory cells shares a bit line.

[0034] Step S2: Erase the storage cells of the flash memory;

[0035] Step S3: Perform voltage-applied floating gate defect screening on the erased memory cell to interconnect abnormal floating gates with bit lines that have broken down; the voltage difference between the source region and the bit line applied to the memory cell during floating gate screening is higher than the voltage difference between the source region and the bit line applied during actual use by the end user.

[0036] Step S4: Perform a write "1" operation on the flash memory. The write "1" operation will fail for the entire column of memory cells containing the abnormal floating gate, thereby filtering out the entire column of memory cells containing the abnormal floating gate.

[0037] The following is combined with Figure 3 and Figure 4 The present invention describes in detail each step of the flash memory testing method according to an embodiment of the present invention.

[0038] Step S1, as follows Figure 3 and Figure 4 As shown, a flash memory is provided, comprising a memory cell array, which includes a plurality of memory cells A arranged in a matrix. Each memory cell is a grid-type flash memory cell; each memory cell includes a floating gate 11 and a bit line 13; each column of memory cells shares the bit line 13. Multiple grid-type flash memory cells are formed in parallel on a semiconductor substrate. The semiconductor substrate can be made of silicon, germanium, silicon-germanium, or silicon carbide, or it can be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or other materials such as gallium arsenide or other group III and V compounds.

[0039] In this embodiment, a gate-type flash memory cell includes two memory structures that share a source region 14 and are symmetrically distributed. Each gate-type flash memory cell includes a drain region 15 (connecting bit line 13) formed in a semiconductor substrate, a source region 14, and a source line (not shown) formed on the semiconductor substrate connecting the source region 14, with the source line located above the source region 14. A word line 12 is formed between the source region 14 and the drain region 15. Two word lines 12 of the same gate-type flash memory cell are formed on both sides of the corresponding source line. A floating gate oxide layer, a floating gate 11, and sidewalls are formed on the semiconductor substrate between the source line and the word line 12. A tunneling oxide layer is formed between the floating gate 11 and the word line 12. The floating gate 11, word line 12, and source line can all be made of polysilicon. A floating gate tip is formed on the side of the floating gate 11 closest to the word line 12. The memory structures on the left and right are symmetrically distributed and share a source line. In this embodiment, the source region 14 and the drain region 15 are, for example, both N-type doped.

[0040] During programming of this gate-type flash memory cell, word line 12 acts as a control gate. A high voltage is applied to the source region 14, a voltage that can open the channel is applied to word line 12, and a constant current is injected through the drain region 15. The source region 14 is at a high potential. Under the influence of the high potential, hot electrons are generated in the channel. On the other hand, the high potential is coupled to the floating gate 11, which generates a coupling voltage. Under the influence of the coupling voltage, electrons are injected from the channel into the floating gate 11, thereby realizing programming. Programming is also called the write "0" operation.

[0041] Next, the first test is performed: short circuit, open circuit, and leakage current test; if the first test is passed, it proceeds to the second test; if the first test is failed, it is rejected.

[0042] Next, a second test is conducted: static power consumption and dynamic power consumption tests. If the second test is passed, the device proceeds to the erase step; if the second test is failed, it is discarded.

[0043] Step S2: Erase the flash memory cell. During the erasure of the grid-type flash memory cell, a high voltage is applied to the word line 12. The floating gate tip reduces the channel voltage of the tunneling effect through the tip discharge principle, enabling electrons to pass through the tunneling oxide layer from the tip of the floating gate 11 into the word line 12. After the memory cell is erased, the memory bit of the memory cell is in the "1" state; that is, all memory cells of the flash memory are erased and set to "1".

[0044] A read operation is performed on the erased memory cell; during the read operation, a voltage is applied to bit line 13, and the source region voltage V... S The voltage is 0V, and an enable voltage is applied to word line 12. The current read determines whether the erased state reaches the "1" state. If the "1" state is reached, the erase is successful and floating gate defect screening is performed. If the "1" state is not reached, the erase fails and the device is discarded.

[0045] Step S3: Perform voltage-based floating gate defect screening on the erased memory cell to interconnect abnormal floating gates with bit lines that have broken down; the voltage difference between the source region and the bit line applied to the memory cell during floating gate screening is higher than the voltage difference applied between the source region and the bit line during actual use by the end user.

[0046] In floating gate defect screening, the voltage difference between the source region and the bit line applied to the memory cell ranges from 8.6V to 9.4V; the source region voltage V S Range: 8.6V~9.4V; Bit line voltage V B Range: 0V~1V; Word line voltage V W Range: 0V~2V.

[0047] Step S4: Perform a write "1" operation on the flash memory. The write "1" operation will fail for the entire column of memory cells containing the abnormal floating gate, thereby filtering out the entire column of memory cells containing the abnormal floating gate. Figure 4 The memory cell B with the floating gate anomaly is shown.

[0048] The memory cell array includes several memory cells A arranged in a matrix. Some memory cells need to be programmed, while others do not. By applying a programming voltage to the memory cells that need to be programmed, electrons from the corresponding memory cells enter the floating gate 11 from the substrate channel to complete the programming. After programming, the memory bit of the memory cell is in the "0" state. Programming is also called a write "0" operation, which changes the memory bit from the "1" state to the "0" state.

[0049] A write-1 operation maintains the memory bit of a memory cell in a "1" state after erasure. Applying a voltage to several memory cells that do not require programming prevents them from meeting programming conditions. The channel voltage is not turned on, and electrons in that memory cell will not enter the floating gate 11 from the substrate. The memory bit of that cell remains in a "1" state; this is called a write-1 operation.

[0050] For example, the voltage conditions for writing "1" include: source region voltage V S It is 8.2V, bit line voltage V B It is 2.5V, word line voltage V W It is 1.6V.

[0051] Memory cell B has a floating gate defect, for example, the floating gate does not form the required sharp corner shape towards the word line, or there is an excess portion of the floating gate near the word line. When a memory cell with a floating gate defect (abnormality) is first used, the source voltage V... S With bit line voltage V B If the voltage difference is less than the channel turn-on voltage, electrons in the corresponding memory cell will not enter the floating gate 11 from the substrate, and the memory bit of the memory cell will always be in a "1" state. During continuous use, the bit line 13 where the defective memory cell is located leaks current, causing the suppression voltage, i.e., the bit line voltage V, to decrease. B When pulled low, the corresponding source voltage V S With bit line voltage V B As the voltage difference increases, when the source voltage V S With bit line voltage V B When the voltage difference exceeds the channel turn-on voltage, electrons will enter their respective floating gates 11 from the substrate into the entire row of memory cells on that bit line. This causes the entire row of memory cells to be programmed to be "0", meaning all memory bits in the row change from a "1" state to a "0" state. Therefore, memory cells with floating gate defects experience leakage between bit line 13 and the floating gate during use, leading to failure of subsequent "1" writing operations and rendering them unusable.

[0052] In this invention, the voltage difference between the source region 14 and the bit line 13 applied to the memory cell during floating gate defect screening is much greater than the voltage difference between the source region 14 and the bit line 13 in the end-user operation mode; the source region voltage V S As the voltage is increased, the voltage coupled from source region 14 to floating gate 11 increases, leading to a larger voltage difference between floating gate 11 and bit line 13. The source region voltage is coupled to the floating gate, resulting in a voltage difference between floating gate 11 and bit line 13 that is much greater than that under end-user operation mode. This allows for the breakdown interconnection of abnormal floating gates and bit lines in memory cells, causing write "1" operations to fail on the entire column of memory cells containing the abnormal floating gate during flash memory operation. This effectively filters out the entire column of memory cells containing the abnormal floating gate.

[0053] In summary, this invention provides a flash memory testing method. After erasing all memory cells of the flash memory to "1", a voltage is applied for floating gate defect screening. This testing method applies a voltage difference between the source region and the bit line on the memory cell that is significantly greater than the voltage difference between the source region and the bit line in end-user operation mode. The source region voltage is coupled to the floating gate, and this is superimposed with the positive potential of the memory cell itself after erasure. This results in a floating gate defect screening method that achieves a voltage difference significantly greater than that between the floating gate and the bit line in end-user operation mode. This breaks down the abnormal floating gate and bit line interconnection of the memory cell, causing the entire column of memory cells containing the abnormal floating gate to fail when a write operation to "1" is performed on the flash memory. This effectively filters out memory cells containing the abnormal floating gate. Floating gate defective chips are screened out during the yield testing stage, preventing them from reaching end users and reducing the reliability risk of end-user failure. This improves the reliability of flash memory and avoids flash memory failure during end-user operation.

[0054] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the devices disclosed in the embodiments; relevant details can be found in the method section.

[0055] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for testing flash memory, characterized in that, include: A flash memory is provided, the flash memory comprising a memory cell array, the memory cell array comprising a plurality of memory cells arranged in a matrix, the memory cells being grid-type flash memory cells; each memory cell comprising a floating gate, word lines, and bit lines all located on a substrate; the memory cells in each column share the bit lines; The storage cells of the flash memory are erased; After erasing, the memory cell is subjected to voltage-applied floating gate defect screening to identify abnormal floating gates of the memory cell that are interconnected with the bit lines that have broken down. The voltage difference between the source region and the bit line applied to the memory cell during the floating gate defect screening is higher than the voltage difference applied between the source region and the bit line during actual use by the end user. A write-"1" operation is performed on the flash memory, causing the write-"1" operation to fail in the entire column of memory cells containing the abnormal floating gate, thereby filtering out the entire column of memory cells containing the abnormal floating gate; the write-"1" operation maintains the memory bit of the memory cell in the "1" state after erasure; a voltage is applied to several memory cells that do not need to be programmed, so that the memory cells do not meet the programming conditions, the channel voltage is not turned on, and the electrons of the corresponding memory cells will not enter the floating gate from the substrate, so the memory bit of the memory cells remains in the "1" state.

2. The flash memory testing method as described in claim 1, characterized in that, The voltage difference between the source region and the bit line applied to the memory cell during the floating gate defect screening ranges from 8.6V to 9.4V.

3. The flash memory testing method as described in claim 2, characterized in that, In the floating gate defect screening, the voltage test conditions applied to the memory cell also include: the source region voltage V S Range: 8.6V~9.4V; the bit line voltage V B Range: 0V~1V; the word line voltage V W Range: 0V~2V.

4. The flash memory testing method as described in claim 1, characterized in that, After providing the flash memory, and before erasing the flash memory, the procedure further includes: First test: short circuit, open circuit and leakage current tests are performed; if the first test is passed, it proceeds to the second test; if the first test is failed, it is rejected.

5. The flash memory testing method as described in claim 4, characterized in that, The second test includes: performing static power consumption and dynamic power consumption tests; if the second test is qualified, it proceeds to the erasure step; if the second test is unqualified, it is rejected.

6. The flash memory testing method as described in claim 3, characterized in that, The voltage conditions for the write "1" operation include: the source region voltage V S The bit line voltage V is 8.2V. B The word line voltage V is 2.5V. W It is 1.6V.

7. The flash memory testing method as described in claim 1, characterized in that, After erasing the flash memory and before the floating gate defect screening, the process further includes: A read operation is performed on the erased storage cell. The current reading determines whether the storage bit is "1" after erasure. If the storage bit is "1", the erasure is successful and the floating gate defect screening is performed. If the storage bit is not "1", the erasure of the storage cell fails and the storage cell is discarded.

8. The flash memory testing method as described in claim 7, characterized in that, After performing a write "1" operation on the flash memory, the method further includes: performing a read operation on the storage cell after the write "1" operation, and determining whether the storage bit remains in the "1" state after the write "1" operation based on the read current; if the storage bit remains in the "1" state, the write "1" operation is successful; if the storage bit is in the "0" state, the write "1" operation fails and is discarded.

9. The flash memory testing method as described in claim 1, characterized in that, A gate-type flash memory cell includes two memory structures that share a source region and are symmetrically distributed; the memory structure includes a drain region and a source region located in a substrate, the drain region being connected to the bit line, a floating gate and a word line being formed on the substrate between the source region and the drain region, a floating gate tip being formed on the side of the floating gate near the word line, and a tunneling oxide layer being formed between the floating gate and the word line.

10. The flash memory testing method as described in claim 9, characterized in that, The abnormal floating grid includes a situation where the floating grid tip that should be formed is not formed on the side of the floating grid near the word line.

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