Manufacturing method of semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device, which comprises the following steps of: after defining a first slot of an area for forming a sacrificial oxide layer by patterning a hard mask layer and before forming the sacrificial oxide layer by thermal oxidation, or after removing the sacrificial oxide layer to form a second slot and before forming a gate oxide layer by thermal oxidation; under the masking of a patterned hard mask layer, ions used for improving the oxidation rate of the substrate are obliquely injected into a part of the substrate below the bottom of a corresponding slot and around the side wall, and then the patterned hard mask layer is etched back to widen the corresponding slot until a part of the substrate area which is easy to form a beak in the thermal oxidation process is exposed. According to the method, the gate oxide layer is formed by the thermal oxidation, and then the corresponding oxide layer is formed by the thermal oxidation, so that the time for forming the oxide layer with the required thickness is shorter, the beak of the formed oxide layer is smaller, the beak problem of the gate oxide layer is finally improved, the height expectation of the gate oxide layer can be ensured, and the expectation of forming a smaller beak can be considered.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] With the continuous miniaturization of semiconductor components and the requirements of specific application scenarios, current product designs often need to apply high-voltage devices. High-voltage devices are devices that can withstand higher voltages while ensuring that the gate is not broken down under high-voltage operation. Generally, the thickness of the gate oxide layer of high-voltage devices is much thicker than that of traditional medium-voltage devices and low-voltage devices. For example, the gate oxide layer thickness of a 1.1V low-voltage device is The gate oxide thickness of high voltage devices needs to reach above.

[0003] Please refer to Figure 1 At present, in order to reduce the height difference between the gate oxide layers of the high-voltage device and the medium-voltage device or the low-voltage device, the process of forming the gate oxide layer of the high-voltage device is generally as follows: first, a thermal oxidation process is used to consume the silicon on the surface of the substrate 100 in the gate oxide layer region of the high-voltage device to be formed, thereby forming a sacrificial oxide layer 101, and then the sacrificial oxide layer 101 is removed to form a deeper groove (not shown); then, a thermal oxidation process is used to consume the substrate in the gate oxide layer region of the high-voltage device to be formed again, thereby forming the gate oxide layer of the high-voltage device (not shown).

[0004] In the above process, when the sacrificial oxide layer 102 is formed, on the one hand, because the thermal oxidation temperature is high and the time is long, a bird's beak is easily formed on the substrate 100 (i.e., the active area of ​​the high-voltage device) at the top corner of the sacrificial oxide layer 102, and the longer the thermal oxidation time, the larger the bird's beak formed, so a shorter thermal oxidation time is required to reduce the formation of the bird's beak; on the other hand, considering reducing the height difference between the gate oxide layer of the high-voltage device and the medium-voltage device or the low-voltage device, a longer thermal oxidation time is required to form a thicker and deeper sacrificial oxide layer 102, so as to form a deeper groove 100a in this area after the sacrificial oxide layer 102 is subsequently etched away, thereby meeting the thickness and height requirements of the gate oxide layer for forming the high-voltage device.

[0005] Therefore, in the manufacturing process of the gate oxide layer of the high-voltage device, there are two conflicting expectations: the expectation of achieving a smaller height difference between the gate oxide layers (requiring a long thermal oxidation time) and the expectation of smaller bird's beak formation (short thermal oxidation time), which need to be taken into account.

[0006] In addition, the bird's beak size of the sacrificial oxide layer 102 will affect the morphology and bird's beak size of the gate oxide layer formed subsequently. Summary of the invention

[0007] The object of the present invention is to provide a method for manufacturing a semiconductor device, which can ensure that the height expectation between gate oxide layers is achieved and also take into account the expectation of forming a smaller bird's beak.

[0008] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0009] Providing a substrate having a patterned hard mask layer formed on the surface thereof, wherein the patterned hard mask layer has a first groove exposing a sacrificial oxide layer to be formed on the substrate;

[0010] Under the mask of the patterned hard mask layer, thermally oxidizing a portion of the substrate at the first groove to form a sacrificial oxide layer;

[0011] Under the mask of the patterned hard mask layer, wet-etching to remove the sacrificial oxide layer and form a second groove in the substrate;

[0012] Under the masking of the patterned hard mask layer, thermally oxidizing a portion of the substrate at the second groove to form a gate oxide layer;

[0013] Wherein, the manufacturing method further comprises:

[0014] After forming the first groove and before thermally oxidizing a portion of the substrate at the first groove to form a sacrificial oxide layer, under the mask of the patterned hard mask layer, ions for increasing the substrate oxidation rate are obliquely implanted into a portion of the thickness of the substrate at the first groove; the patterned hard mask layer is etched back to widen the first groove to expose a portion of the substrate area where the bird's beak of the sacrificial oxide layer is easily formed; and / or,

[0015] After forming the second groove and before thermally oxidizing a portion of the substrate at the second groove to form a gate oxide layer, ions used to increase the substrate oxidation rate are obliquely implanted into a portion of the thickness of the substrate around the second groove under the mask of the patterned hard mask layer; and the patterned hard mask layer is back-etched to widen the second groove to expose a portion of the substrate area where the gate oxide layer bird's beak is easily formed.

[0016] Optionally, a device isolation structure for defining a device active region is further formed in the substrate; and the step of forming the patterned hard mask layer on the substrate comprises:

[0017] sequentially covering the substrate and the device isolation structure with a pad oxide layer and a hard mask layer;

[0018] The hard mask layer is dry-etched, and the pad oxide layer is further wet-etched to form the patterned hard mask layer.

[0019] Optionally, the patterned hard mask layer is etched back using a wet etching process; and / or, after etching back the patterned hard mask layer, the pad oxide layer is also etched back using a wet etching process to shrink the pad oxide layer relative to the patterned hard mask layer.

[0020] Optionally, the hard mask layer includes silicon nitride, the pad oxide layer includes silicon oxide, a phosphoric acid solution is used when etching back the patterned hard mask layer, and an HF acid solution, an SPM solution or an SC1 solution is used when etching back the pad oxide layer.

[0021] Optionally, the ions for increasing the oxidation rate of the substrate include at least one of oxygen ions, amorphization ions and halogen ions.

[0022] Optionally, the amorphization ions include at least one of silicon ions, germanium ions, and argon ions.

[0023] Optionally, the ions for increasing the substrate oxidation rate include amorphization ions, and the amorphization ions are heavier than intrinsic atoms in the substrate.

[0024] Optionally, after forming the first groove and before etching back the patterned hard mask layer to widen the first groove, the line width of the first groove is 20nm to 150nm smaller than the required line width of the sacrificial oxide layer; or, after forming the second groove and before etching back the patterned hard mask layer to widen the second groove, the line width of the second groove is 20nm to 150nm smaller than the required line width of the gate oxide layer.

[0025] Optionally, after the ions are obliquely implanted, an ion implantation region is formed in the partial thickness of the substrate at the first groove; wherein the ion implantation region is narrow at the top and wide at the bottom, and the bottom edge of the ion implantation region is located outside the side wall of the first groove; and / or, the ion doping concentration in the ion implantation region located at the bottom of the edge of the patterned hard mask layer increases vertically downward from the surface of the substrate.

[0026] Optionally, the thermal oxidation time for forming the sacrificial oxide layer or the gate oxide layer is 2 hours to 10 hours.

[0027] Optionally, the injection angle of the inclined injection is 20° to 45°.

[0028] Compared with the prior art, the technical solution of the present invention is to first, under the mask of the patterned hard mask layer, obliquely inject ions for increasing the substrate oxidation rate into the substrate below the bottom of the corresponding groove and around the sidewalls after defining the first groove in the area where the sacrificial oxide layer is formed by a patterned hard mask layer and before thermal oxidation forms the sacrificial oxide layer, or after removing the sacrificial oxide layer to form the second groove and before thermal oxidation forms the gate oxide layer, and then back-etch the patterned hard mask layer to widen the corresponding groove to expose a portion of the substrate area that is prone to forming a bird's beak during the thermal oxidation process, so that in the process of thermal oxidation to form the corresponding oxide layer (i.e., the sacrificial oxide layer or the gate oxide layer), the substrate oxidation rate in the area near the corresponding groove including the area that is prone to forming a bird's beak is faster, thereby taking less time to form an oxide layer of the required thickness, and the bird's beak of the formed oxide layer is smaller, which ultimately improves the bird's beak problem of the gate oxide layer, and can ensure that the height expectation of the gate oxide layer is achieved (i.e., the height difference expectation between the gate oxide layers in different device areas is met), while taking into account the expectation of forming a smaller bird's beak.

[0029] In addition, when the ions used to increase the substrate oxidation rate include amorphizing ions, the substrate below the region prone to bird's beak is differentiated by ion implantation into a non-amorphized region near the top of the substrate and the amorphized region below it, and the two regions have different oxidation rates. Thus, compared with the prior art, when the amorphized region below the bird's beak region and the non-amorphized region of the region prone to bird's beak are oxidized simultaneously in the present invention, the oxidation degrees of the two regions are closer. Because the region below the region prone to bird's beak is amorphized, the time for the entire oxidation process of forming the gate oxide is reduced, and the formation time of the bird's beak is reduced, and the oxidation degrees of the two regions are further closer, so the expected small bird's beak or bird's beak-free gate oxide morphology in the present invention can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0031] Figure 1 The present invention is a schematic diagram of a flow chart of forming a sacrificial oxide layer in the process of manufacturing a high-voltage gate oxide layer of a high-voltage device in the prior art.

[0032] Figure 2 It is a schematic flow chart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

[0033] Figure 3 yes Figure 2 A schematic diagram of a device cross-sectional structure in a method for manufacturing a semiconductor device is shown.

[0034] Figure 4 It is a schematic flow chart of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

[0035] Figure 5 yes Figure 4 A schematic diagram of a device cross-sectional structure in a method for manufacturing a semiconductor device is shown.

[0036] Figure 6 It is a schematic flow chart of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0037] Figure 7 It is a schematic diagram of the cross-sectional structure of a device in a method for manufacturing a semiconductor device according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0038] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0040] First embodiment

[0041] Please refer to Figure 2 , this embodiment provides a method for manufacturing a semiconductor device, which includes the following steps:

[0042] S11, providing a substrate having a patterned hard mask layer formed on the surface thereof, wherein the patterned hard mask layer has a first groove exposing a sacrificial oxide layer to be formed on the substrate;

[0043] S12, under the mask of the patterned hard mask layer, obliquely implanting ions for increasing the oxidation rate of the substrate into a portion of the thickness of the substrate at the first groove;

[0044] S13, etching back the patterned hard mask layer to widen the first groove to expose a portion of the substrate area where a bird's beak of a sacrificial oxide layer is easily formed;

[0045] S14, under the mask of the patterned hard mask layer, thermally oxidizing a portion of the substrate at the first groove to form a sacrificial oxide layer;

[0046] S15, under the mask of the patterned hard mask layer, wet-etching to remove the sacrificial oxide layer, and forming a second groove in the substrate;

[0047] S16, under the mask of the patterned hard mask layer, thermally oxidize a portion of the substrate at the second groove to form a gate oxide layer.

[0048] In step S11, please refer to Figure 3 In (A), the provided substrate 200 may be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC) or silicon on insulator (SOI), etc., and a device isolation structure 201 is further formed in the substrate 200, and a patterned hard mask layer 203 is formed on the surface of the substrate 200. As an example, the process includes:

[0049] (1) Please refer to Figure 3 In (A), a shallow trench isolation process is used to form a shallow trench isolation structure (STI) filled in the shallow trench and used as a device isolation structure 201. The device isolation structure 201 can define an active area (not shown) of a high-voltage device in the substrate 200. The process of the shallow trench isolation process may include: first, etching the substrate 200 to form a shallow trench (not shown) by photolithography and etching processes; then, forming a linear oxide layer (not shown) on the inner surface of the shallow trench by thermal oxidation, atomic layer deposition or plasma enhanced chemical vapor deposition; thereafter, depositing an insulating dielectric material by a chemical vapor deposition process to fill the shallow trench, and further removing excess insulating dielectric material by chemical mechanical polishing or wet etching processes, thereby forming the desired shallow trench isolation structure. In other embodiments of the present invention, a local field oxygen isolation process may also be used to form the device isolation structure 201, which will not be described in detail herein.

[0050] (2) Please refer to Figure 3In (A), a pad oxide layer 202 may be covered on the surface of the substrate 200 and the device isolation structure 201 by any suitable process such as a thermal oxidation process or a chemical vapor deposition process, and a hard mask layer may be further deposited on the surface of the pad oxide layer 202 by any suitable process such as a chemical vapor deposition process. The pad oxide layer 202 may include silicon oxide, and the hard mask layer may include one or more layers of silicon oxynitride and silicon nitride. The hard mask layer is used as a downward transfer layer of the photoresist pattern in the subsequent process, and on the other hand, it is used as a barrier layer to block the diffusion of oxygen atoms when a sacrificial oxide layer or a gate oxide layer is formed by thermal oxidation in the subsequent process. At the same time, it can also be used as a shielding layer for subsequent ion implantation to cooperate with the tilted implantation to form the required area for ion implantation in the substrate. The pad oxide layer 202 is used to relieve the stress between the hard mask layer and the substrate 200.

[0051] (3) Please refer to Figure 3 In (A) and (B), a patterned photoresist layer 300 is formed on the hard mask layer through a series of photolithography processes such as photoresist coating, exposure, and development. The patterned photoresist layer 300 is then used as a mask to etch the hard mask layer using a dry etching process to form a patterned hard mask layer 203. The patterned hard mask layer 203 has a first groove 204 for exposing a portion of the area 200a where a sacrificial oxide layer is to be formed, and masks other areas. The patterned photoresist layer 300 is then removed. Under the mask of the patterned hard mask layer 203, any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, and H2O) or SC1 (a mixture of NH4OH, H2O2, and H2O) is used to wet-remove the pad oxide layer 202 on the bottom of the first groove 204 to expose the surface of the substrate 200.

[0052] In this step S11, in order to make the area of ​​the bird's mouth of the sacrificial oxide layer formed in the prior art also become a part of the sacrificial oxide layer of the present invention, the line width W1 of the first slot 204 is smaller than the line width W0 of the area 200a to be formed with the sacrificial oxide layer. For example, W0-W1=d. The specific size of d can be determined according to the lateral extension distance of the bird's mouth of the sacrificial oxide layer when the sacrificial oxide layer is formed by thermal oxidation in the historical production data, for example, d is greater than or equal to the lateral extension distance of the bird's mouth of the sacrificial oxide layer. The specific size of d can also be adjusted according to the required thickness of the sacrificial oxide layer to be formed and the thermal oxidation time. The greater the required thickness of the sacrificial oxide layer to be formed and the longer the thermal oxidation time, the greater the value of d. The width of the first slot 204 is smaller than the width of the sacrificial oxide layer that is actually needed. This is to utilize the smaller opening to form a shield for ion implantation, so that the ion implantation region 205 formed in the subsequent step S12 can form a distribution characteristic of ion doping concentration difference in the bottom area of ​​the edge area of ​​the hardening mask layer 203 beside the first slot 204 (on the side other than the device isolation structure 201), where the ion doping concentration is low near the surface of the substrate 200 (i.e., the top surface of the substrate) in the vertical direction and the ion doping concentration is high away from the surface of the substrate 200 (i.e., as shown in FIG. Figure 3 B), so that after the subsequent oxidation process, although the area below the bottom of the edge area of ​​the hardened mask layer 203 near the surface of the substrate 200 is more accessible to oxygen, it is less likely to form an oxidized structure (or the formation rate is slower) relative to the area far from the surface of the substrate 200, thereby reducing the bird's beak structure formed near the surface of the substrate 200 compared to the prior art.

[0053] Please refer to Figure 3 (B) in step S12, under the mask of the patterned hard mask layer 203, ions for improving the oxidation rate of the substrate are injected into the substrate 200 around the bottom and sidewall of the first groove 204 at an inclination angle θ, forming an ion implantation area 205 in a trapezoidal shape with a narrow top and a wide bottom. The inclination angle θ needs to be set according to the above d, and the ion implantation depth h in this step needs to be slightly less than or equal to the thickness h0 of the sacrificial oxide layer to be formed (i.e., the thickness of the region 200a), so as to prevent the problem that the ion implantation is too shallow and the bird's beak of the sacrificial oxide layer to be formed subsequently cannot be improved, and the problem that the second groove to be formed subsequently is too deep due to the ion implantation being too deep.

[0054] As an example, the ion implantation depth in step S12 is greater than 50% of h0.

[0055] As an example, the ions used to increase the substrate oxidation rate in step S12 include at least one of oxygen ions, amorphizing ions and halogen ions. The implantation of oxygen ions can increase the oxygen content in the substrate 200, thereby increasing the oxidation rate of the substrate at the subsequent first groove 204 during oxidation. The amorphizing ions, for example, include at least one of silicon ions, germanium ions or argon ions. For example, when the intrinsic material of the substrate 200 is single crystal silicon, the implantation of amorphizing ions can form the single crystal silicon in the region of the substrate 200 implanted with the amorphizing ions into amorphous silicon (i.e., the ion implantation region 205 is an amorphous region), thereby increasing the oxidation rate of the substrate at the subsequent first groove 204 during thermal oxidation. Halogen ions include, for example, at least one of chloride ions (Cl), fluorine ions (F) and bromide ions (Br). The injection of halogen ions can act as a catalyst, weakening the Si-O bond energy in the ion injection area 205. Therefore, when a sacrificial oxide layer is subsequently formed by thermal oxidation at the first groove 204, the SO bond energy of SiO2 in the formed upper sacrificial oxide layer is weaker, making it easier for oxygen to diffuse in, thereby increasing the oxidation rate during substrate oxidation.

[0056] As an example, when the ions used to increase the substrate oxidation rate in step S12 include amorphizing ions, the substrate region below the region prone to producing a bird's beak includes a non-amorphized region near the top of the substrate and an amorphized region below the non-amorphized region after the ion tilted injection. The oxidation rates of the two regions in the subsequent step S16 are different. Compared with the prior art, when the amorphized region below the above-mentioned bird's beak region and the non-amorphized region of the region prone to producing a bird's beak are oxidized at the same time in step S16 of this embodiment, the oxidation degrees of the two regions are closer. Because the region below the region prone to forming a bird's beak is amorphized, the time of the entire oxidation process of forming the gate oxide layer is reduced, and the formation time of the bird's beak is reduced, so that the oxidation degrees of the two regions are further close. Therefore, the expected small bird's beak or gate oxide morphology without a bird's beak can be obtained, achieving the effect of improving the bird's beak problem relative to the prior art.

[0057] Preferably, the ions used to increase the oxidation rate of the substrate in step S12 include amorphizing ions, and the amorphizing ions are heavier than the intrinsic atoms in the substrate. Thus, by implementing amorphizing implantation through heavier ions, the ion implantation region 205 can have a better and relatively stable morphology, and the gate oxide layer formed in step S16 can have higher quality and predictability.

[0058] Please refer to Figure 3(C) in step S13, a phosphoric acid solution is used as an etching solution to wet-etch the patterned hard mask layer 203 to pull back the patterned hard mask layer 203 to a suitable degree, and further any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, H2O) or SC1 (a mixture of NH4OH, H2O2, H2O) is used to pull back the pad oxide layer 202 exposed by the patterned hard mask layer 203, so that the opening of the first groove 204 is widened to expose the surface of the part of the substrate area where the bird's beak of the sacrificial oxide layer is easily formed. Therefore, the back-etching thickness d1 of the patterned hard mask layer 203 (i.e., the widening degree 2*d1 of the first groove 204) depends on the required thickness of the sacrificial oxide layer, the size of the area where the bird's beak is easily formed, the thermal oxidation time, and the requirements of the device performance on the bird's beak.

[0059] In this step, the purpose of widening the opening of the first groove 204 is, on the one hand, to prevent the stress caused by the compression of the sacrificial oxide layer and the patterned hard mask layer 203 formed during the subsequent thermal oxidation to form the sacrificial oxide layer, which may cause the patterned hard mask layer 203 on the surface of the substrate 200 to peel off or crack. The peeling or cracking of the patterned hard mask layer 203 may easily lead to the formation of a larger bird's beak during the subsequent thermal oxidation to form a gate oxide layer; on the other hand, it is to make the substrate area where the bird's beak is easy to form (especially the corner area above the top of the ion implantation area 205 where ions for improving the substrate oxidation efficiency are not implanted) more exposed to the environment of the subsequent thermal oxidation to form the gate oxide layer, so that the substrate in this area will also be oxidized during the process of thermal oxidation to form the gate oxide layer, and it is ensured that the bird's beak formed is small or even non-existent.

[0060] Please refer to Figure 3 In (D), in step S14, the substrate 200 in the widened first slot 204 can be thermally oxidized by any suitable process such as a high-temperature furnace tube oxidation process. In the thermal oxidation process, since the surface of the substrate 200 of the first slot 204 is exposed, the oxygen molecules directly contact and react with the substrate 200 at the bottom of the first slot 204 and consume the substrate 200 downward to form a sacrificial oxide layer 206 of the required thickness. Since the ion implantation area 205 is below the bottom of the first slot 204, its oxidation rate becomes relatively faster, so the thermal oxidation time required to form a sacrificial oxide layer 206 of the same thickness as the prior art becomes shorter, and the area that is originally prone to forming a bird's beak can be directly contacted with oxygen and oxidized, and finally become a part of the sacrificial oxide layer 206, thereby achieving the effect of reducing or even eliminating the formation of the bird's beak when the sacrificial oxide layer 206 is formed by thermal oxidation. In addition, the depth and morphology of the ion implantation area 205 can limit the morphology of the sacrificial oxide layer 206 during the thermal oxidation process, so that the sacrificial oxide layer 206 is better than the prior art.

[0061] Please refer to Figure 3 In (E), in step S15, any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, and H2O) or SC1 (a mixture of NH4OH, H2O2, and H2O) can be selected to wet-etch and remove the sacrificial oxide layer 206. After removing the sacrificial oxide layer 206, a second groove 207 is formed in the area where the sacrificial oxide layer 206 was originally located. The second groove 207 allows the top of the substrate 200 in this area to be lowered to a required height.

[0062] Optionally, in this process, the etching selectivity ratio between the device isolation structure 201 and the sacrificial oxide layer 206 is not high, and the etching solution will also etch the top and side walls of the device isolation structure 201 exposed by the patterned hard mask layer 203, so that the top of the device isolation structure 201 drops to the bottom surface of the original sacrificial oxide layer 206 or is lower than the bottom surface of the original sacrificial oxide layer 206 (at this time, a step is formed with the top surface of the substrate at the bottom of the second groove 207), thereby expanding the process window for forming the gate oxide layer, and meeting the requirements of the minimum spacing from the gate to the source contact plug of the high-voltage device, etc., which is conducive to the subsequent self-aligned formation of the gate oxide layer and avoids affecting the reliability of the device.

[0063] Please refer to Figure 3 (F) in step S16, according to the thickness requirement of the gate oxide layer required by the device (e.g., high-voltage transistor), a corresponding thermal oxidation process recipe is set, and the surface of the substrate 200 exposed by the second groove 207 is thermally oxidized according to the process recipe, thereby self-aligningly growing the required gate oxide layer 208. As an example, the thickness h1 of the gate oxide layer 208 is greater than h0, so as to restore the flatness of the process top surface jointly constituted by the second groove 207 and the substrate 200 around it. It should be understood that, since the sacrificial oxide layer 206 formed in the aforementioned step S14 has a better morphology and a smaller bird's beak, the morphology of the second groove 207 is better and the bird's beak area is smaller, so the gate oxide layer 208 formed in this step has a better morphology and a smaller bird's beak, thereby achieving the effect of improving the bird's beak problem relative to the prior art.

[0064] In summary, in the method for manufacturing a semiconductor device of the present embodiment, after defining an opening smaller than the area to be formed with the first groove of the patterned hard mask layer and before forming the sacrificial oxide layer by thermal oxidation, ions for increasing the oxidation rate of the substrate are first injected obliquely into the substrate at the bottom of the first groove. These ions are not only injected into the main area where the sacrificial oxide layer is formed, but also injected into the substrate below the partial area where the bird's beak is easily formed (i.e., the substrate area away from the substrate surface), and the patterned hard mask layer is etched back to widen the first groove to expose the partial surface of the area where the bird's beak is easily formed (i.e., expanded to the width of the sacrificial oxide layer to be formed). Therefore, when the sacrificial oxide layer is formed by thermal oxidation, the effect of the ion implantation area can be utilized to shorten the thermal oxidation time, and the bird's beak of the sacrificial oxide layer can be reduced or even eliminated, thereby achieving the desired effect of ensuring that the height difference between the gate oxide layers of different device areas meets the expectation and forming a smaller bird's beak.

[0065] Second embodiment

[0066] Please refer to Figure 4 , this embodiment provides a method for manufacturing a semiconductor device, which includes the following steps:

[0067] S21, providing a substrate having a patterned hard mask layer formed on the surface thereof, wherein the patterned hard mask layer has a first groove exposing a sacrificial oxide layer to be formed on the substrate;

[0068] S22, under the mask of the patterned hard mask layer, thermally oxidizing a portion of the substrate at the first groove to form a sacrificial oxide layer;

[0069] S23, under the mask of the patterned hard mask layer, wet-etching to remove the sacrificial oxide layer, and forming a second groove in the substrate;

[0070] S24, under the mask of the patterned hard mask layer, obliquely implanting ions for increasing the oxidation rate of the substrate into a portion of the thickness of the substrate at the second groove;

[0071] S25, etching back the patterned hard mask layer to widen the second groove to expose a portion of the substrate region where a gate oxide layer bird's beak is easily formed;

[0072] S26, under the mask of the patterned hard mask layer, thermally oxidize a portion of the substrate at the second groove to form a gate oxide layer.

[0073] In step S21, please refer to Figure 5In (A), first, the provided substrate 200 can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC) or silicon on insulator (SOI), etc., and further adopts any suitable process such as shallow trench isolation process to form a device isolation structure 201 in the substrate 200 to define an active area (not shown) of a high-voltage device, etc.; then, a pad oxide layer 202 and a hard mask layer are sequentially covered on the surface of the substrate 200 and the device isolation structure 201, and a photoresist 301 is coated for photolithography; then, the photoresist 301 after photolithography is used as a mask to etch The hard mask layer is formed into a patterned hard mask layer 203; then the photoresist 301 is removed, and the patterned hard mask layer 203 is used as a mask, and any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, H2O) or SC1 (a mixture of NH4OH, H2O2, H2O) is used to wet-remove the pad oxide layer 202 exposed by the patterned hard mask layer 203 to expose the surface of the substrate 200, thereby forming a first groove 204 that defines an area where a sacrificial oxide layer is to be formed (the area may be slightly smaller than the area 200b where a gate oxide layer is to be formed). This step S21 is basically the same as step S11 of the first embodiment, and will not be described in detail here. Among them, the pad oxide layer 202 may include silicon oxide, and the hard mask layer may include one or more layers of silicon oxynitride and silicon nitride. The hard mask layer is used as a downward transfer layer of the photoresist pattern in the subsequent process, and as a barrier layer to block the diffusion of oxygen atoms when a sacrificial oxide layer or a gate oxide layer is formed by thermal oxidation in the subsequent process. At the same time, it can also be used as a shielding layer for ion implantation to form a desired area for ion implantation in the substrate in coordination with the tilted implantation. The pad oxide layer 202 is used to relieve the stress between the hard mask layer and the substrate 200.

[0074] In this step S21, the line width W4 of the first slot 204 is smaller than the line width W3 of the region 200b where the gate oxide layer is to be formed. For example, W3-W4=d0. The specific size of d0 can be determined based on the lateral extension distance of the bird's beak of the gate oxide layer when the gate oxide layer is formed by thermal oxidation in historical production data, for example, d0 is greater than or equal to the lateral extension distance of the bird's beak of the gate oxide layer. The specific size of d0 can also be adjusted based on the required thickness of the gate oxide layer to be formed and the thermal oxidation time. The greater the required thickness of the gate oxide layer to be formed and the longer the thermal oxidation time, the greater the value of d0. The width W4 of the first slot 204 is smaller than the width of the sacrificial oxide layer that is actually needed. This is to utilize the smaller opening to form a shield for ion implantation, so that the ion implantation region 205 formed in the subsequent step S24 can form a characteristic of a differential distribution of ion doping concentrations in which the ion doping concentration is low near the surface of the substrate 200 (i.e., the top surface of the substrate) and the ion doping concentration is high away from the surface of the substrate 200 in the vertical direction in the region at the bottom of the edge region of the hardening mask layer 203 next to the first slot 204 (i.e., the side not including the device isolation structure 201) (i.e., the side not including the device isolation structure 201). Figure 3 B), so that after the subsequent oxidation process, although the area below the bottom of the edge area of ​​the hardened mask layer 203 near the surface of the substrate 200 is more accessible to oxygen, it is less likely to form an oxidized structure (or the formation rate is slower) relative to the area far from the surface of the substrate 200, thereby reducing the bird's beak structure formed near the surface of the substrate 200 compared to the prior art.

[0075] Please refer to Figure 5 In (B), in step S22, the substrate 200 in the first slot 204 may be thermally oxidized by any suitable process such as a high-temperature furnace tube oxidation process. In the thermal oxidation process, since the surface of the substrate 200 in the first slot 204 is exposed, oxygen molecules directly contact and react with the substrate 200 at the bottom of the first slot 204 and consume the substrate 200 downward to form a sacrificial oxide layer 206 of a desired thickness. In this process, since the thermal oxidation process time is relatively long, the sacrificial oxide layer 206 may have a corresponding bird's beak (not marked).

[0076] This step S22 is basically the same as step S14 of the first embodiment, and will not be described in detail here. However, since steps S24 to S25 need to be performed after step S23 and before step S26, the time for thermal oxidation to form a gate oxide layer can be shortened and the formation rate of the gate oxide layer can be increased. Therefore, the thermal oxidation process time of the sacrificial oxide layer 206 formed in this step S22 can be shorter than that in the prior art, and the thickness of the formed sacrificial oxide layer 206 can be less than that of the sacrificial oxide layer 206 formed in the prior art, so that the bird's beak of the sacrificial oxide layer 206 formed in this step will also be reduced relative to the prior art.

[0077] Please refer to Figure 5 In (C), in step S23, any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, H2O) or SC1 (a mixture of NH4OH, H2O2, H2O) can be selected to wet etch and remove the sacrificial oxide layer 206. After removing the sacrificial oxide layer 206, a second groove 207 is formed in the area where the sacrificial oxide layer 206 and its bird's beak are originally located. The second groove 207 makes the top of the substrate 200 in this area lowered to the required height. This step S23 is basically the same as step S15 of the first embodiment, and will not be described in detail here.

[0078] Optionally, in this process, the etching selectivity ratio between the device isolation structure 201 and the sacrificial oxide layer 206 is not high, and the etching solution will also etch the top and side walls of the device isolation structure 201 exposed by the patterned hard mask layer 203, so that the top of the device isolation structure 201 drops to the bottom surface of the original sacrificial oxide layer 206 or is lower than the bottom surface of the original sacrificial oxide layer 206 (at this time, a step is formed with the top surface of the substrate at the bottom of the second groove 207), thereby expanding the process window for forming the gate oxide layer, and meeting the requirements of the minimum spacing from the gate to the source contact plug of the high-voltage device, etc., which is conducive to the subsequent self-aligned formation of the gate oxide layer and avoids affecting the reliability of the device.

[0079] Please refer to Figure 5 (D) in step S24, under the mask of the patterned hard mask layer 203, ions used to increase the oxidation rate of the substrate are injected into the substrate 200 around the bottom and sidewall of the second groove 207 at a corresponding tilt angle (not shown), forming an ion implantation area 205 with a shape of narrow top and wide bottom. The tilt angle needs to be set according to the above-mentioned d0, and the ion implantation depth h in this step needs to be slightly less than or equal to the thickness h2 of the gate oxide layer to be formed (i.e., the thickness of the region 200b), so as to prevent the problem that the ion implantation is too shallow and the bird's beak of the gate oxide layer to be formed subsequently cannot be improved, and the problem that the gate oxide layer to be formed subsequently is too thick due to the ion implantation being too deep. This step S24 is basically the same as step S12 of the first embodiment, and will not be described in detail here.

[0080] As an example, the ion implantation depth in step S24 is greater than 50% of h2.

[0081] As an example, the ions used to increase the substrate oxidation rate in step S24 include at least one of oxygen ions, amorphization ions, and halogen ions. Among them, the implantation of oxygen ions can increase the oxygen content in the substrate 200, thereby increasing the oxidation rate of the substrate at the second groove 207 during oxidation; the amorphization ions include, for example, at least one of silicon ions, germanium ions, or argon ions, and the implantation of amorphization ions can form the single crystal silicon in the substrate 200 near the second groove 207 into amorphous silicon (i.e., the ion implantation area 205 is an amorphous area), thereby increasing the oxidation rate of the substrate at the second groove 207 during thermal oxidation; the halogen ions include, for example, at least one of chloride ions (Cl), fluorine ions (F), and bromide ions (Br), and the implantation of halogen ions can act as a catalyst, which has the effect of weakening the Si-O bond energy in the ion implantation area 205. Therefore, when the gate oxide layer is formed by thermal oxidation at the second groove 207, the SO bond energy of SiO2 in the upper gate oxide layer that has been formed is weaker, making it easier for oxygen to diffuse into, thereby increasing the oxidation rate of the substrate during oxidation.

[0082] Preferably, the ions used to increase the oxidation rate of the substrate in step S24 include amorphizing ions, and the amorphizing ions are heavier than the intrinsic atoms in the substrate. Thus, by implementing amorphizing implantation through heavier ions, the ion implantation region 205 can have a better and relatively stable morphology, and the gate oxide layer formed in step S26 can have higher quality and predictability.

[0083] Please refer to Figure 5 (E) in step S25, a phosphoric acid solution is used as an etching solution to wet-etch the patterned hard mask layer 203 to pull back the patterned hard mask layer 203 to a suitable degree, and further any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, H2O) or SC1 (a mixture of NH4OH, H2O2, H2O) is used to pull back the pad oxide layer 202 exposed by the patterned hard mask layer 203, so that the opening of the second groove 207 is widened to expose a portion of the substrate surface area that is easy to form a bird's beak when the gate oxide layer is formed by thermal oxidation. Therefore, the back-etching thickness d2 of the patterned hard mask layer 203 (i.e., the widening degree 2*d2 of the second groove 207) depends on the required gate oxide layer thickness h2, the thermal oxidation time and the requirements of the device performance on the bird's beak. This step S25 is basically the same as step S13 of the first embodiment, and will not be described in detail here.

[0084] In this step, the purpose of widening the opening of the second groove 207 is, on the one hand, to prevent the stress caused by the gate oxide layer and the patterned hard mask layer 203 formed when the gate oxide layer is thermally oxidized to form a gate oxide layer in the subsequent step S26 from peeling off or cracking, which may easily lead to the formation of a larger bird's beak; on the other hand, it is to make the substrate area where the bird's beak is easily formed (especially the corner area above the top of the ion implantation area 205 where ions for improving the substrate oxidation efficiency are not implanted) more exposed to the environment of thermal oxidation to form the gate oxide layer, so that the substrate in this area will also be oxidized in the process of thermal oxidation to form the gate oxide layer, and ensure that the bird's beak formed is small or even non-existent.

[0085] In addition, when etching back the pad oxide layer 202 in step S25, the top of the exposed device isolation structure 201 is also etched to round the top corner of the active area connected to the device isolation structure 201 to facilitate the subsequent growth of the gate oxide layer.

[0086] Please refer to Figure 5 In (F), in step S26, according to the thickness requirement of the gate oxide layer required by the device (such as a high-voltage transistor), a corresponding thermal oxidation process recipe (gate oxide recipe) is set. According to the process recipe, the substrate 200 exposed around the widened second slot 207 is thermally oxidized by any suitable process such as a high-temperature furnace tube oxidation process, and then the required gate oxide layer 208 is self-alignedly grown. As an example, the thickness h2 of the gate oxide layer 208 is sufficient to restore the flatness of the process top surface jointly constituted by the second slot 207 and the substrate 200 around it. In the thermal oxidation process, since the ion implantation area 205 is below the bottom of the second slot 207, its oxidation rate becomes relatively faster, so the thermal oxidation time required to form the gate oxide layer 208 of the same thickness as the prior art becomes shorter, and the area that is originally prone to forming a bird's beak can be directly contacted with oxygen and oxidized, and finally becomes a part of the gate oxide layer 208, thereby achieving the effect of reducing or even eliminating the formation of the bird's beak when the gate oxide layer 208 is formed by thermal oxidation. In addition, the depth and morphology of the ion implantation region 205 and the morphology of the second groove 207 can limit the morphology and thickness of the gate oxide layer 208 during the thermal oxidation process.

[0087] As an example, when the ions used to increase the substrate oxidation rate in step S24 include amorphizing ions, because the substrate region below the bird's beak region that is prone to be formed includes a non-amorphized region near the top of the substrate and an amorphized region below the non-amorphized region after the ion tilted implantation, the oxidation rates of the two regions are different, and then compared with the prior art, when the amorphized region below the bird's beak region and the non-amorphized region of the bird's beak region that is prone to be formed are oxidized at the same time in the present invention, the oxidation degrees of the two regions are closer. Because the region below the bird's beak region that is prone to be formed is amorphized, the time of the entire oxidation process of forming the gate oxide layer is reduced, and the formation time of the bird's beak is reduced, and the oxidation degrees of the two regions are further close, so the expected small bird's beak or bird's beak-free gate oxide morphology in the present invention can be obtained. Therefore, the morphology of the gate oxide layer 208 is better than that of the prior art, and the effect of improving the bird's beak problem is achieved compared with the prior art. And due to the existence of the ion implantation region 205, under the requirement of forming a gate oxide layer of the same thickness, the thermal oxidation time set in this step S26 can be shorter than that in step S16 of the first embodiment.

[0088] To sum up, in the manufacturing method of the semiconductor device of the present embodiment, after removing the sacrificial oxide layer to form the second groove and before thermally oxidizing to form the gate oxide layer, ions for increasing the oxidation rate of the substrate are first obliquely injected into the bottom of the second groove and the surrounding part of the substrate, and these ions are not only injected into the main area where the gate oxide layer is formed, but also injected into the part of the substrate below the part where the bird's beak is easily formed, and the patterned hard mask layer is etched back to widen the second groove to expose the part of the surface of the part where the bird's beak is easily formed. Therefore, when the gate oxide layer is formed by thermal oxidation, the effect of the ion implantation area can be utilized to shorten the thermal oxidation time, and the bird's beak of the gate oxide layer can be reduced or even eliminated, thereby achieving the desired effect of ensuring that the height difference between the gate oxide layers in different device areas meets the expectation and taking into account the formation of a smaller bird's beak.

[0089] Third embodiment

[0090] Please refer to Figure 7 This embodiment provides a method for manufacturing a semiconductor device, which includes the following steps:

[0091] S31, providing a substrate having a patterned hard mask layer formed on the surface thereof, wherein the patterned hard mask layer has a first groove exposing a sacrificial oxide layer to be formed on the substrate;

[0092] S32, under the mask of the patterned hard mask layer, obliquely implanting ions for increasing the oxidation rate of the substrate into a portion of the thickness of the substrate at the first groove;

[0093] S33, etching back the patterned hard mask layer to widen the first groove to expose a portion of the substrate region where a bird's beak of a sacrificial oxide layer is easily formed;

[0094] S34, under the mask of the patterned hard mask layer, thermally oxidizing a portion of the substrate at the first groove to form a sacrificial oxide layer;

[0095] S35, under the mask of the patterned hard mask layer, wet-etching to remove the sacrificial oxide layer, and forming a second groove in the substrate;

[0096] S36, under the mask of the patterned hard mask layer, obliquely implanting ions for increasing the oxidation rate of the substrate into a portion of the thickness of the substrate at the second groove;

[0097] S37, etching back the patterned hard mask layer to widen the second groove to expose a portion of the substrate region where a bird's beak of a sacrificial oxide layer is easily formed;

[0098] S38, under the mask of the patterned hard mask layer, thermally oxidize a portion of the substrate at the second groove to form a gate oxide layer.

[0099] In step S31, please refer to Figure 7 In (A), first, the provided substrate 200 can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC) or silicon on insulator (SOI), etc., and further adopts any suitable process such as shallow trench isolation process to form a device isolation structure 201 in the substrate 200 to define an active area (not shown) of a high-voltage device, etc.; then, a pad oxide layer 202 and a hard mask layer are sequentially covered on the surface of the substrate 200 and the device isolation structure 201, and a photoresist 301 is coated for photolithography; then, the hard mask layer is etched using the photoresist 301 after photolithography as a mask to form a patterned hard mask layer 203; then, the hard mask layer 203 is removed. Remove the photoresist 301, and use the patterned hard mask layer 203 as a mask, use any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, H2O) or SC1 (a mixture of NH4OH, H2O2, H2O), wet remove the pad oxide layer 202 exposed by the patterned hard mask layer 203 to expose the surface of the substrate 200, and then form a first groove 204 that defines the area where the sacrificial oxide layer is to be formed. The area defined by the first groove 204 can be slightly smaller than the area 200a of the sacrificial oxide layer that is actually required to be formed, and the area 200a is further smaller than the area 200b where the gate oxide layer is to be formed. This step S31 is basically the same as step S11 of the first embodiment, and will not be described in detail here.

[0100] Please refer to Figure 7In (B), in step S32, under the mask of the patterned hard mask layer 203, ions for increasing the substrate oxidation rate are injected into the substrate 200 at an inclination angle θ around the bottom and sidewall of the first groove 204 to form an ion implantation region 205a in a trapezoidal shape with a narrow top and a wide bottom. This step S32 is substantially the same as step S12 of the first embodiment, and will not be described in detail here.

[0101] As an example, the ions used to increase the substrate oxidation rate in step S32 include at least one of oxygen ions, amorphizing ions and halogen ions. Among them, the implantation of oxygen ions can increase the oxygen content in the substrate 200, thereby increasing the oxidation rate of the substrate at the first slot 204 during subsequent oxidation; the amorphizing ions include, for example, at least one of silicon ions, germanium ions or argon ions, etc. The implantation of amorphizing ions can form the single crystal silicon in the substrate 200 into amorphous silicon (i.e., the ion implantation area 205 is an amorphous area), thereby increasing the oxidation rate of the substrate at the first slot 204 during subsequent thermal oxidation; the halogen ions include, for example, at least one of chloride ions (Cl), fluorine ions (F) and bromide ions (Br), and the implantation of halogen ions can act as a catalyst, which has the effect of weakening the Si-O bond energy in the ion implantation area 205a, so that when a sacrificial oxide layer is formed by thermal oxidation at the first slot 204, the SO bond energy of the SiO2 of the formed upper sacrificial oxide layer is weaker, making it easier for oxygen to diffuse into, thereby increasing the oxidation rate of the substrate during oxidation.

[0102] Preferably, the ions used to increase the oxidation rate of the substrate in step S32 include amorphizing ions, and the amorphizing ions are heavier than the intrinsic atoms in the substrate. Thus, by implementing amorphizing implantation through heavier ions, the ion implantation region 205a can have a better and relatively stable morphology, and the gate oxide layer formed in step S38 can have higher quality and predictability.

[0103] Please refer to Figure 7(C) in step S33, a phosphoric acid solution is used as an etching solution to wet-etch the patterned hard mask layer 203 to pull back the patterned hard mask layer 203 to a suitable degree, and further any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, H2O) or SC1 (a mixture of NH4OH, H2O2, H2O) is used to pull back the pad oxide layer 202 exposed by the patterned hard mask layer 203, so that the opening of the first slot 204 is widened to expose the substrate surface area that is easy to form a bird's beak when the sacrificial oxide layer is formed by thermal oxidation. Therefore, the back-etching thickness d1 of the patterned hard mask layer 203 (i.e., the widening degree 2*d1 of the first slot 204) depends on the required thickness of the sacrificial oxide layer, the thermal oxidation time, and the requirements of the device performance on the bird's beak. This step S33 is basically the same as step S13 of the first embodiment, and will not be described in detail here.

[0104] In this step, the purpose of widening the opening of the first groove 204 is, on the one hand, to prevent the stress caused by the compression of the sacrificial oxide layer formed by the subsequent thermal oxidation to form the sacrificial oxide layer and the patterned hard mask layer 203, which may cause the patterned hard mask layer 203 on the surface of the substrate 200 to peel off or crack. The peeling or cracking of the patterned hard mask layer 203 may easily lead to the formation of a larger bird's beak when the gate oxide layer is formed by the subsequent thermal oxidation; on the other hand, it is to make the substrate area where the bird's beak is easy to form (especially the corner area above the top of the ion implantation area 205a where ions for improving the substrate oxidation efficiency are not implanted) more exposed to the environment of the subsequent thermal oxidation to form the gate oxide layer, so that the substrate in this area will also be oxidized in the process of thermal oxidation to form the gate oxide layer, and it is ensured that the bird's beak formed is small or even non-existent.

[0105] Please refer to Figure 7In (D), in step S34, the substrate 200 in the widened first slot 204 can be thermally oxidized by any suitable process such as a high-temperature furnace tube oxidation process. In the thermal oxidation process, since the surface of the substrate 200 in the first slot 204 is exposed, oxygen molecules directly contact and react with the substrate 200 at the bottom of the first slot 204 and consume the substrate 200 downward to form a sacrificial oxide layer 206 of a desired thickness. Since the ion implantation area 205a is located below the bottom of the first groove 204, its oxidation rate is relatively faster, so the thermal oxidation time required for forming the sacrificial oxide layer 206 of the same thickness as that in the prior art is shortened, and the ion implantation area 205a can form a difference in ion doping concentration distribution in the region at the bottom of the edge region of the hardening mask layer 203 next to the first groove 204 (on the side of the non-device isolation structure 201), with low ion doping concentration close to the surface of the substrate 200 (i.e., the top surface of the substrate) and high ion doping concentration away from the surface of the substrate 200 in the longitudinal direction. After the oxidation process in step S34, although it is easier to approach oxygen at the bottom of the edge region of the hardening mask layer 203 close to the surface of the substrate 200, it is less likely to form an oxidation structure (or the formation rate is slower) relative to the region far from the surface of the substrate 200. Therefore, compared with the prior art, the bird's beak structure formed by the sacrificial oxide layer 206 close to the surface of the substrate 200 is reduced, thereby achieving the effect of reducing or even eliminating the formation of the bird's beak when the sacrificial oxide layer 206 is formed by thermal oxidation. In addition, the depth and morphology of the ion implantation region 205a can limit the morphology of the sacrificial oxide layer 206 during the thermal oxidation process, thereby making the sacrificial oxide layer 206 better than the prior art. This step S34 is substantially the same as step S14 of the first embodiment and will not be described in detail here.

[0106] As an example, when the ions used to increase the substrate oxidation rate in step S32 include amorphizing ions, that is, because the substrate region below the region prone to bird's beak includes a non-amorphized region near the top of the substrate and an amorphized region below, the two regions have different oxidation rates, and then relative to the prior art, in step S34 of this embodiment, when the amorphized region below the bird's beak region and the non-amorphized region of the region prone to bird's beak are oxidized at the same time, the oxidation degrees of the two regions are closer. Because the region below the region prone to bird's beak is amorphized, the time of the entire oxidation process of forming the sacrificial oxide layer 206 is reduced, and the formation time of the bird's beak is reduced, and the oxidation degrees of the two regions are further close, so the expected small bird's beak or bird's beak-free sacrificial oxide layer 206 morphology in the present invention can be obtained.

[0107] Please refer to Figure 7(E) in step S35, any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, H2O) or SC1 (a mixture of NH4OH, H2O2, H2O) can be selected to wet etch and remove the sacrificial oxide layer 206. After removing the sacrificial oxide layer 206, a second groove 207 is formed in the area where the sacrificial oxide layer 206 was originally located. The second groove 207 lowers the top of the substrate 200 in this area to the required height. This step S35 is basically the same as step S15 of the first embodiment and will not be described in detail here. Optionally, in this process, the etching selectivity ratio between the device isolation structure 201 and the sacrificial oxide layer 206 is not high, so the etching solution will also etch the top and side walls of the device isolation structure 201 exposed by the patterned hard mask layer 203.

[0108] Please refer to Figure 7 In step (E), in step S36, under the mask of the patterned hard mask layer 203, ions for increasing the oxidation rate of the substrate are tiltedly implanted into the substrate 200 around the bottom and sidewall of the second groove 207 at a corresponding tilt angle (not shown) to form an ion implantation area 205b. The ions for increasing the oxidation rate of the substrate in this step include at least one of oxygen ions, amorphization ions and halogen ions. This step S36 is basically the same as step S24 of the second embodiment, and will not be described in detail here.

[0109] Preferably, the ions used to increase the oxidation rate of the substrate in step S36 include amorphizing ions, and the amorphizing ions are heavier than the intrinsic atoms in the substrate. Thus, by implementing amorphizing injection through heavier ions, the ion injection region 205b can have a better and relatively stable morphology, and the gate oxide layer formed in step S38 can have higher quality and predictability.

[0110] Please refer to Figure 7 (F) in step S37, a phosphoric acid solution is used as an etching solution to wet-etch the patterned hard mask layer 203 to pull back the patterned hard mask layer 203 to a suitable degree, and further any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, H2O) or SC1 (a mixture of NH4OH, H2O2, H2O) is used to pull back the pad oxide layer 202 exposed by the patterned hard mask layer 203, so that the opening of the second groove 207 is widened to expose a portion of the substrate surface area that is easy to form a bird's beak when the gate oxide layer is formed by thermal oxidation. Therefore, the back-etching thickness d2 of the patterned hard mask layer 203 (i.e., the widening degree 2*d2 of the second groove 207) depends on the required thickness of the gate oxide layer, the thermal oxidation time, and the requirements of the device performance on the bird's beak. This step S37 is basically the same as step S25 of the second embodiment, and will not be described in detail here.

[0111] In this step, the purpose of widening the opening of the second groove 207 is, on the one hand, to prevent the stress caused by the gate oxide layer and the patterned hard mask layer 203 formed during the subsequent thermal oxidation to form the gate oxide layer from peeling off or cracking, which may easily lead to the formation of a larger bird's beak; on the other hand, it is to make the substrate area where the bird's beak is easily formed (especially the corner area above the top of the ion implantation area 205b where ions for improving the substrate oxidation efficiency are not implanted) more exposed to the environment of thermal oxidation to form the gate oxide layer, so that the substrate in this area will also be oxidized during the process of thermal oxidation to form the gate oxide layer, and to ensure that the formed bird's beak is small or even non-existent.

[0112] As an example, when the ions used to increase the substrate oxidation rate in step S36 include amorphizing ions, that is, because the substrate region below the region prone to bird's beak includes a non-amorphized region near the top of the substrate and an amorphized region below, the two regions have different oxidation rates, and then relative to the prior art, in step S38 of this embodiment, when the amorphized region below the bird's beak region and the non-amorphized region of the region prone to bird's beak are oxidized simultaneously, the oxidation degrees of the two regions are closer. Because the region below the region prone to bird's beak is amorphized, the time of the entire oxidation process of forming the gate oxide layer is reduced, and the formation time of the bird's beak is reduced, and the oxidation degrees of the two regions are further closer, so the expected small bird's beak or bird's beak-free gate oxide morphology in the present invention can be obtained.

[0113] In addition, when etching back the pad oxide layer 202 in step S37 , the top of the exposed device isolation structure 201 is also etched to round the top corner of the active area near the device isolation structure 201 to facilitate the subsequent growth of the gate oxide layer.

[0114] Please refer to Figure 7 In (G), in step S38, a corresponding thermal oxidation process recipe is set according to the thickness requirement of the gate oxide layer required by the device (e.g., a high-voltage transistor), and the surface of the substrate 200 exposed by the second groove 207 is thermally oxidized according to the process recipe, thereby self-aligningly growing the required gate oxide layer 208.

[0115] As an example, the thickness h1 of the gate oxide layer 208 is greater than h0 to restore the flatness of the process top surface formed by the second groove 207 and the surrounding substrate 200. It should be understood that, since the sacrificial oxide layer 206 formed in the above step has a better morphology and a smaller bird's beak, the morphology of the second groove 207 is better and the bird's beak area is smaller. After forming the second groove 207, the ion implantation area 205b is further formed and the patterned mask layer 203 is etched back to widen the second groove 207. Therefore, the gate oxide layer 208 formed in this step has a better morphology and a smaller bird's beak, thereby achieving the effect of improving the bird's beak problem relative to the prior art. This step S38 is basically the same as step S16 of the first embodiment, and will not be described in detail here. And due to the existence of the ion implantation area 205b, under the requirement of forming a gate oxide layer of the same thickness, the thermal oxidation time set in this step S38 can be shorter than that in step S16 of the first embodiment.

[0116] Among them, the ion implantation area 205b can form an ion doping concentration difference distribution characteristic in the bottom area of ​​the edge area of ​​the hardening mask layer 203 next to the second groove 207 (on the side of the non-device isolation structure 201), with low ion doping concentration close to the surface of the substrate 200 (i.e., the top surface of the substrate) and high ion doping concentration away from the surface of the substrate 200 in the vertical direction. After the oxidation process in step S38, below the bottom of the edge area of ​​the hardening mask layer 203, although it is easier to approach oxygen near the surface of the substrate 200, it is less likely to form an oxidation structure (or the formation rate is slower) relative to the area far from the surface of the substrate 200, thereby reducing the bird's beak structure formed by the gate oxide layer 208 near the surface of the substrate 200 compared to the prior art.

[0117] In summary, the method for manufacturing a semiconductor device of this embodiment combines the advantages of the first embodiment and the second embodiment, and thus can achieve a better effect of improving the bird's beak problem of the gate oxide layer.

[0118] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate having a patterned hard mask layer formed on the surface thereof, wherein the patterned hard mask layer has a first groove exposing a sacrificial oxide layer to be formed on the substrate; Under the mask of the patterned hard mask layer, thermally oxidizing a portion of the substrate at the first groove to form a sacrificial oxide layer; Under the mask of the patterned hard mask layer, wet-etching to remove the sacrificial oxide layer and form a second groove in the substrate; Under the masking of the patterned hard mask layer, thermally oxidizing a portion of the substrate at the second groove to form a gate oxide layer; Wherein, the manufacturing method further comprises: After forming the first groove and before thermally oxidizing a portion of the substrate at the first groove to form a sacrificial oxide layer, under the mask of the patterned hard mask layer, ions for increasing the substrate oxidation rate are obliquely implanted into a portion of the thickness of the substrate at the first groove; the patterned hard mask layer is etched back to widen the first groove to expose a portion of the substrate area where the bird's beak of the sacrificial oxide layer is easily formed; and / or, After forming the second groove and before thermally oxidizing a portion of the substrate at the second groove to form a gate oxide layer, under the mask of the patterned hard mask layer, ions used to increase the substrate oxidation rate are obliquely implanted into a portion of the thickness of the substrate around the second groove; and the patterned hard mask layer is back-etched to widen the second groove to expose a portion of the substrate area to form the bird's beak of the gate oxide layer.

2. The manufacturing method according to claim 1, characterized in that The substrate also has a device isolation structure for defining a device active area; the step of forming the patterned hard mask layer on the substrate comprises: sequentially covering the substrate and the device isolation structure with a pad oxide layer and a hard mask layer; The hard mask layer is dry-etched, and the pad oxide layer is further wet-etched to form the patterned hard mask layer.

3. The manufacturing method according to claim 2, characterized in that: The patterned hard mask layer is etched back using a wet etching process; and / or, after etching back the patterned hard mask layer, the pad oxide layer is further etched back using a wet etching process to shrink the pad oxide layer relative to the patterned hard mask layer.

4. The manufacturing method according to claim 3, characterized in that: The hard mask layer includes silicon nitride, the pad oxide layer includes silicon oxide, a phosphoric acid solution is used when the patterned hard mask layer is etched back, and an HF acid solution, an SPM solution or an SC1 solution is used when the pad oxide layer is etched back.

5. The manufacturing method according to claim 1, characterized in that: The ions used to increase the substrate oxidation rate include at least one of oxygen ions, amorphization ions and halogen ions.

6. The manufacturing method according to claim 5, characterized in that: The amorphization ions include at least one of silicon ions, germanium ions, and argon ions.

7. The manufacturing method according to claim 5 or 6, characterized in that: The ions for increasing the substrate oxidation rate include amorphization ions, and the amorphization ions are heavier than intrinsic atoms in the substrate.

8. The manufacturing method according to claim 1, characterized in that: After forming the first groove and before etching back the patterned hard mask layer to widen the first groove, the line width of the first groove is 20nm to 150nm smaller than the required line width of the sacrificial oxide layer; or, after forming the second groove and before etching back the patterned hard mask layer to widen the second groove, the line width of the second groove is 20nm to 150nm smaller than the required line width of the gate oxide layer.

9. The manufacturing method according to claim 1, characterized in that: After the ion is obliquely implanted, an ion implantation region is formed in the partial thickness of the substrate at the first groove; wherein the ion implantation region is narrow at the top and wide at the bottom, and the bottom edge of the ion implantation region is located outside the side wall of the first groove; and / or, the ion doping concentration in the ion implantation region located at the bottom of the edge of the patterned hard mask layer increases vertically downward from the surface of the substrate.

10. The manufacturing method according to claim 1, characterized in that: The injection angle of the inclined injection is 20° to 45°.

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