Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps of: after a first opening for exposing a device active region defined by a shallow trench isolation structure is formed by etching a hard mask layer, masking the first opening by utilizing a patterned mask layer; a plurality of first openings are formed in the patterned mask layer, and a plurality of second openings are formed in the area, located on the outer side of the first opening, of the patterned mask layer, so that when the patterned mask layer is used for mask etching of the hard mask layer, the second openings are transferred into the hard mask layer, the line width of the second openings is gradually reduced in the direction away from the shallow trench isolation structure, and the line width of the second openings is gradually reduced in the direction away from the shallow trench isolation structure. When a patterned mask layer is removed and thermal oxidation is carried out on a device active region at the first opening to form a gate oxide layer, the size of an oxide layer (namely a beak) generated on the outer side of a shallow trench isolation structure around the formed first opening can be accurately controlled by utilizing the effect of the second opening, so that the beak is as small as possible and thin.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] With the continuous miniaturization of semiconductor components and the requirements of specific application scenarios, current product designs often need to apply high-voltage devices. High-voltage devices are devices that can withstand higher voltages while ensuring that the gate is not broken down under high-voltage operation. Generally, the thickness of the gate oxide layer of high-voltage devices is much thicker than that of traditional normal-voltage devices and low-voltage devices. For example, the gate oxide layer thickness of a 1.1V low-voltage device is The gate oxide thickness of high voltage devices needs to reach Please refer to Figure 1 At present, the gate oxide layer HOX of the high-voltage device is formed by a thermal oxidation process. In the process of thermal oxidation to form the gate oxide layer HOX of the high-voltage device, in addition to the longitudinal growth of the oxide layer, there will also be lateral diffusion of oxygen. The lateral diffused oxygen will pass through the top of the shallow trench isolation structure STI adjacent to the gate oxide layer HOX to the substrate active area AA on the other side, forming a bird's beak 101a.

[0003] The existence of the bird's beak structure 101a poses a great challenge to the subsequent oxide layer removal process, which may lead to the problem that there is not enough metal silicide at the bottom of the contact plug. In the prior art, the following methods are generally used to improve the bird's beak problem: (1) changing the furnace tube growth method to reduce the lateral diffusion of oxygen and the thickness of the bird's beak structure 101a; (2) improving other processes to enhance the barrier ability of oxygen diffusion; (3) removing the bird's beak structure 101a by additionally increasing the amount of etching solution such as HF acid and the etching time in the subsequent oxide removal process.

[0004] These methods have the following defects: (1) they will challenge the limits of the furnace tube thermal oxidation process and change the thermal oxidation temperature; (2) the increase in the amount of etching solution such as HF acid will have an adverse effect on device performance, etc., and the process is complicated, and the consistency of the final bird's beak reduction is poor; (3) in the subsequent process of removing oxide, the additional amount of etching solution such as HF acid and the etching time are increased, which will cause over-etching of the corresponding oxide layer. The quality of the corresponding oxide after over-etching may affect the reliability of the device, adding many risks. Summary of the invention

[0005] The object of the present invention is to provide a method for manufacturing a semiconductor device, which can make the morphology of the bird's beak structure controllable and reduce the occupied area when forming a gate oxide layer, without changing the thermal oxidation and corresponding oxide wet etching processes, etc., which is more conducive to the uniformity and reliability of device performance.

[0006] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0007] Providing a substrate and forming a shallow trench isolation structure in the substrate to define a device active region where a gate oxide layer is to be formed;

[0008] forming a hard mask layer on the substrate and the shallow trench isolation structure, and etching the hard mask layer to form a first opening exposing the surface of the device active area;

[0009] Forming a patterned mask layer, wherein the patterned mask layer masks the first opening, and forming a plurality of second openings above the substrate region outside the shallow trench isolation structure around the first opening, wherein the line width of the second openings gradually decreases in a direction away from the shallow trench isolation structure;

[0010] Using the patterned mask layer as a mask, etching the hard mask layer at the bottom of each second opening to deepen the bottom surface of each second opening to a corresponding depth of the hard mask layer;

[0011] The patterned mask layer is removed, and the device active area exposed by the first opening and the substrate below the second opening are thermally oxidized, the oxide layer formed at the first opening is used as the gate oxide layer required for the device, and the oxide layers formed at each second opening outside the shallow trench isolation structure are connected to the shallow trench isolation structure.

[0012] Optionally, after forming the first opening exposing the surface of the device active area and before forming the patterned mask layer, it also includes: under the mask of the hard mask layer, thermally oxidizing the device active area exposed by the first opening to form a sacrificial oxide layer; wet etching to remove the sacrificial oxide layer, and at the same time etching open the top of the shallow trench isolation structure around the first opening close to the side of the device active area, so that the top of the device active area becomes lower and rounded; or; after forming the first opening exposing the surface of the device active area and before forming the patterned mask layer, it also includes: under the mask of the hard mask layer, wet etching the device active area exposed by the first opening, and at the same time etching open the top of the shallow trench isolation structure around the first opening close to the side of the device active area, so that the top of the device active area becomes lower and rounded.

[0013] Optionally, the hard mask layer includes a bottom film, an intermediate film and a top film stacked in sequence from bottom to top, and when the hard mask layer at the bottom of each second opening is etched using the patterned mask layer as a mask, the etching stops at the top surface of the intermediate film or at a corresponding depth; the bottom film is silicon oxide, and the intermediate film is silicon oxynitride or silicon nitride.

[0014] Optionally, when the bottom surface of each second opening is deepened to a corresponding depth of the hard mask layer, the thickness of the intermediate layer film remaining at the bottom of the second opening is

[0015] Optionally, at any step node after forming the patterned mask layer and before thermally oxidizing the device active area exposed by the first opening and the substrate below the second opening, ions for suppressing the oxidation rate of the substrate are injected into the substrate below the second opening using the patterned mask layer as a mask; and / or, at any step node before thermally oxidizing the device active area exposed by the first opening and the substrate below the second opening, ions for increasing the oxidation rate of the substrate are injected into the device active area exposed by the first opening.

[0016] Optionally, the ions for suppressing the oxidation rate of the substrate include nitrogen ions, and / or the ions for increasing the oxidation rate of the substrate include at least one of oxygen ions, amorphization ions and halogen ions.

[0017] Optionally, on the outer side of the shallow trench isolation structure, the intervals between the second openings gradually decrease along a direction away from the shallow trench isolation structure.

[0018] Optionally, on the outer side of the shallow trench isolation structure, along a direction close to the shallow trench isolation structure, a line width of any second opening is the same as a spacing between any second opening and its adjacent second opening.

[0019] Optionally, the manufacturing method has at least one of the following parameters:

[0020] (1) On the outer side of the shallow trench isolation structure, along the direction away from the shallow trench isolation structure, the line width of the innermost second opening is between 120 nm and 500 nm;

[0021] (2) On the outer side of the shallow trench isolation structure, along the direction away from the shallow trench isolation structure, the line width of the outermost second opening is between 80 nm and 200 nm;

[0022] (3) On the outer side of the shallow trench isolation structure, along the direction away from the shallow trench isolation structure, the intervals between adjacent second openings and the interval between the innermost second opening and the shallow trench isolation structure are respectively between 80 nm and 200 nm;

[0023] (4) The thickness of the bird's beak formed on the outer side of the shallow trench isolation structure is in the range of

[0024] (5) The width K of the bird's beak formed on the outer side of the shallow trench isolation structure is in the range of 600 nm to 2000 nm.

[0025] Optionally, the manufacturing method, after thermally oxidizing the device active region exposed by the first opening and the substrate below the second opening, further comprises:

[0026] removing the hard mask layer;

[0027] forming a gate on the gate oxide layer;

[0028] forming a sidewall spacer on the sidewall of the gate;

[0029] Using a source-drain ion implantation process to form a source region and a drain region in the substrate at both sides of the gate;

[0030] Forming metal silicide on the top of the gate, the source region and the drain region by using a metal silicide process;

[0031] Contact plugs are formed on the metal silicide on top of the gate, the source region, and the drain region.

[0032] Optionally, after thermally oxidizing the device active area exposed by the first opening and the substrate below the second opening, the method further includes: etching and removing the oxide layer below at least a portion of the second opening including the outermost second opening according to the position of the outermost second opening and the outer boundary position of the shallow trench isolation structure around the first opening, so as to reduce or remove the bird's beak structure on the outer top of the shallow trench isolation structure.

[0033] Compared with the prior art, the technical solution of the present invention, after etching the hard mask layer to form a first opening exposing the device active area defined by the shallow trench isolation structure, uses a patterned mask layer to mask the first opening, and forms a plurality of second openings in the area of ​​the patterned mask layer located outside the first opening, so that when the hard mask layer is etched with the patterned mask layer as a mask, the second opening is transferred to the hard mask layer, and the line width of the second opening gradually decreases along the direction away from the shallow trench isolation structure, and when the patterned mask layer is removed and the device active area at the first opening is thermally oxidized to form a gate oxide layer, the second opening can be used to accurately control the size of the oxide layer (i.e., the bird's beak) generated outside the shallow trench isolation structure around the formed first opening, so that the bird's beak is as small and thin as possible. The principle is as follows: on the one hand, a small portion of oxygen will diffuse downward from the second opening into the substrate to form an oxide layer, and since the line width of the second opening outside the shallow trench isolation structure around the first opening gradually decreases in the direction away from the shallow trench isolation structure, the amount of oxygen passing through the second opening can be reduced in the direction away from the shallow trench isolation structure, and the oxide layer formed under each second opening can serve as a multi-layer barrier layer to prevent the oxygen that penetrates and diffuses laterally from the shallow trench isolation structure from continuing to diffuse outward, thereby accurately controlling the lateral size of the oxide layer formed outside the shallow trench isolation structure, and then accurately controlling the size of the bird's beak on the outside of the top of the shallow trench isolation structure, making the bird's beak as small and thin as possible.

[0034] In addition, after forming the gate oxide layer, the oxide layer below at least a portion of the second opening including the outermost second opening can be etched and removed based on the position of the outermost second opening and the outer boundary position of the shallow trench isolation structure around the first opening, thereby reducing or removing the bird's beak structure outside the shallow trench isolation structure. Obviously, the bird's beak structure removal process will be relatively more controllable and reliable because it has the outer boundary position of the shallow trench isolation structure and the position parameters of the outermost second opening as a reference.

[0035] Moreover, when forming the gate oxide layer, the morphology of the bird's beak structure is controllable and the occupied area is reduced, and there is no need to change the thermal oxidation and corresponding oxide wet etching processes, which is more conducive to the uniformity and reliability of device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0037] Figure 1 It is a cross-sectional schematic diagram of a high-voltage device manufactured by prior art and its bird's beak structure.

[0038] Figure 2It is a flow chart of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention.

[0039] Figures 3 to 10 It is a schematic diagram of the cross-sectional structure of a device in a method for manufacturing a semiconductor device according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0040] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0042] Please refer to Figure 2 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0043] S1, providing a substrate and forming a shallow trench isolation structure in the substrate to define a device active region where a gate oxide layer is to be formed;

[0044] S2, forming a hard mask layer on the substrate and the shallow trench isolation structure, and etching the hard mask layer to form a first opening exposing the surface of the device active area;

[0045] S3, forming a patterned mask layer, wherein the patterned mask layer masks the first opening, and forms a plurality of second openings above the substrate region outside the shallow trench isolation structure around the first opening, wherein the line width of the second openings gradually decreases in a direction away from the shallow trench isolation structure;

[0046] S4, using the patterned mask layer as a mask, etching the hard mask layer at the bottom of each of the second openings to deepen the bottom surface of each of the second openings to a corresponding depth of the hard mask layer;

[0047] S5, removing the patterned mask layer, and thermally oxidizing the device active area exposed by the first opening and the substrate under the second opening, the oxide layer formed at the first opening is used as the gate oxide layer required for the device, and the oxide layers formed at each second opening outside the shallow trench isolation structure are connected to the shallow trench isolation structure.

[0048] Please refer to Figure 3 In step S1, first, the provided substrate 200 can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC) or silicon on insulator (SOI), etc. Then, a shallow trench isolation structure STI is formed by a shallow trench isolation process to define the device active area AA1 where the gate oxide layer is to be formed. In this embodiment, the shallow trench isolation process is a conventional process in the art and is not described in detail here. In the substrate 200, the shallow trench isolation structure STI is used to define the device active area AA1 where the gate oxide layer is to be formed, and active areas AA2 and AA3 outside the shallow trench isolation structure STI located on both sides of the device active area AA1 are also defined.

[0049] Please continue to refer to Figure 3 In step S2, first, any suitable process such as chemical vapor deposition can be used to sequentially cover the bottom film 201, the middle film 202 (optionally with a thickness of 200 mm / s) on the top surface of the device active area AA1, the active areas AA2 and AA3, and the shallow trench isolation structure STI. For example ) and a top film 203, thereby forming a hard mask layer. As an example, the bottom film 201 is a silicon oxide layer, the middle film 202 is a silicon nitride layer, and the top film 203 is a silicon oxide layer. As another example, the bottom film 201 is a silicon oxide layer, the middle film 202 is a silicon oxynitride layer, and the top film 203 is a silicon nitride layer.

[0050] Among them, the bottom film 201 is used to relieve the stress between the composite layer formed by the stacking of the middle film 202 and the top film 203 and the substrate 200. The top film 203 is used as a downward transfer layer of the photoresist pattern in the subsequent process, and on the other hand, it is used as a barrier layer to block the diffusion of oxygen atoms when the gate oxide layer is formed by thermal oxidation in the subsequent process. The middle film 202 is used as an etching stop layer when the top film 203 is etched in the subsequent process, and on the other hand, its blocking ability for oxygen atoms is higher than that of the bottom film 201, and it can relatively controllably allow oxygen to diffuse through it and the bottom film 201 into the substrate 200 below, and the blocking ability of the middle film 202 for oxygen atoms is related to its thickness, and the thicker the thickness, the stronger the blocking ability.

[0051] Please refer to Figure 4 In step S2, a photoresist (not shown) is then coated on the top film 203 of the hard mask layer, and the photoresist is subjected to photolithography (including exposure and development processes) to open the photoresist above the device active area AA1, that is, to define the area where the gate oxide layer is to be formed in the photoresist; then, the top film 203 of the hard mask layer is dry-etched using the photoresist after photolithography as a mask to open the top film 203 and the middle film 202 above the device active area AA1 to be formed; then, the photoresist is removed, and the top film 203 and the middle film 202 are used as masks to etch the bottom film 201 using a wet etching process until the top surface of the substrate of the device active area AA1 is exposed, thereby forming a first opening 204 that penetrates the hard mask layer from top to bottom, and the area defined by the first opening 204 is the area where the gate oxide layer (e.g., the gate oxide of a high-voltage device) is to be formed. The photoresist is removed, and the remaining hard mask layer masks the top surface of the area around the first opening 204 (including the shallow trench isolation structure STI and the top of the active areas AA2 and AA3 ).

[0052] In one example, after step S2 and before step S3, the following steps are further performed:

[0053] First, please continue to refer to Figure 4, under the mask of the hard mask layer, the exposed device active area AA1 is thermally oxidized. The thermal oxidation can be achieved by a furnace tube oxidation process. In the thermal oxidation process, since the surface of the device active area AA1 is exposed, the oxygen molecules directly contact and react with the silicon of the device active area AA1 and consume a certain thickness of the device active area AA1 downward to form a sacrificial oxide layer 205. The sacrificial oxide layer 205 is used to reduce the height difference between the gate oxide layer of the high-voltage transistor and the medium-voltage or low-voltage transistor on the subsequent substrate, and at the same time round the top of the device active area AA1 to facilitate the subsequent formation of a gate oxide layer HOX of a high-voltage device with a better morphology. Optionally, the thermal oxidation time of the formed sacrificial oxide layer 205 is short, and the thickness of the sacrificial oxide layer 205 is less than the thickness of the gate oxide layer HOX that needs to be formed later, thereby ensuring that the performance of the shallow trench isolation structure STI is relatively good, and the oxygen molecules are not easy to pass through the shallow trench isolation structure STI and reach the adjacent active areas AA2 and AA3 to form bird's beaks.

[0054] Then, please refer to Figure 5 Any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, and H2O) or SC1 (a mixture of NH4OH, H2O2, and H2O) can be selected to wet-etch and remove the sacrificial oxide layer 205. In this process, since the etching selectivity between the shallow trench isolation structure STI and the sacrificial oxide layer 205 is not high, the etching solution will also etch the top and sidewall of the inner side of the shallow trench isolation structure STI exposed by the hard mask layer. After removing the sacrificial oxide layer 205, the top of the device active area AA1 is lowered to the required height and rounded. At this time, the top of the shallow trench isolation structure STI is etched open on one side close to the device active area AA1 (i.e., the inner side of the shallow trench isolation structure STI), so that the top of the shallow trench isolation structure STI becomes thinner in the lateral direction, and the top of the area where the shallow trench isolation structure STI is etched open is lowered to be lower than the top of the device active area AA1 re-exposed after removing the sacrificial oxide layer 205. The top of the device active area AA1 thus exposed forms a step relative to the top of the adjacent shallow trench isolation structure STI, which is beneficial to the subsequent self-aligned formation of the gate oxide layer required for the high-voltage device.

[0055] In another example, after step S2 and before step S3, the following steps are further performed: Figure 5, under the mask of the hard mask layer, the exposed device active area AA1 is wet etched or dry etched, so that the top of the device active area AA1 is lowered to the required height and rounded. Optionally, in this process, the top of the shallow trench isolation structure STI close to the side of the device active area AA1 (i.e., the inner side of the shallow trench isolation structure STI) can be etched open together, so that the top of the shallow trench isolation structure STI is thinned in the lateral direction, and the top of the region where the shallow trench isolation structure STI is etched open is lowered, thereby the top of the exposed device active area AA1 forms a step relative to the top of the adjacent shallow trench isolation structure STI, which is conducive to the subsequent self-aligned formation of the gate oxide layer required for the high-voltage device.

[0056] Please refer to Figure 6 In step S3, a photoresist layer is first coated on the top film 203 of the hard mask layer and the first opening 204, and the photoresist layer fills the first opening 204 and has a flat top surface; then the photoresist layer is photolithographically processed (including a series of processes such as exposure and development) to form a patterned mask layer 300. The patterned mask layer 300 masks the area of ​​the first opening 204, and forms a plurality of second openings in the area above the active areas AA2 and AA3 on the outside of the shallow trench isolation structure STI outside the first opening 204 (i.e., the side of the shallow trench isolation structure STI away from the first opening 204), and the line width of these second openings on the outside of the shallow trench isolation structure STI gradually decreases along the direction away from the shallow trench isolation structure STI (i.e., the direction away from the first opening 204), so that when the gate oxide layer is subsequently formed by thermal oxidation, the amount of oxygen passing through the second openings in the direction away from the shallow trench isolation structure STI is reduced, thereby controlling the lateral width (i.e., the width of the oxide layer (i.e., the bird's beak structure) formed on the top of the active areas AA2 and AA3 Fig. 9 The k) in should be as short as possible.

[0057] It should be understood that when the shallow trench isolation structure STI outside the first opening 204 is symmetrically distributed, the distribution of the second openings above the active areas AA2 and AA3 is preferably symmetrically distributed, so that the morphology of the bird's beak formed subsequently is a symmetrical structure. Moreover, the size of each second opening is smaller than the first opening 204, wherein the number, shape, position, line width, spacing and other parameters of the second openings above the active areas AA2 and AA3 (i.e., above the outer side of the shallow trench isolation structure STI outside the first opening 204) are all dependent on the requirements of the device structure to be formed in the active areas AA2 and AA3. And the line width of each second opening and the spacing between adjacent second openings can enable the oxide layer formed in the active area AA2 or AA3 at the adjacent second openings to be connected as a whole when the oxide layer is formed by thermal oxidation in the subsequent step S5. The outermost second opening 206c can limit the terminal position and thickness of the bird's beak formed on the outer top of the shallow trench isolation structure STI later.

[0058] In this embodiment, the active areas AA2 and AA3 are distributed on both sides of the active area AA1 , so the second openings on the active areas AA2 and AA3 are parallel and spaced strip openings, and the second openings are symmetrically arranged on both sides of the first opening 204 .

[0059] Optionally, outside the shallow trench isolation structure STI on each side of the first opening 204 , the intervals between the second openings gradually decrease along a direction away from the shallow trench isolation structure STI (ie, along a direction away from the first opening 204 ).

[0060] Optionally, on the outer side of the shallow trench isolation structure STI on each side of the first opening 204, along the direction close to the shallow trench isolation structure STI (i.e., the direction close to the first opening 204, which is opposite to the direction away from the first opening 204), the line width of any second opening is the same as the interval between the second opening and its adjacent second opening.

[0061] As an example, three second openings 206a, 206b, and 206c are symmetrically formed on the outer side of the shallow trench isolation structure STI on both sides of the first opening 204 along the direction away from the shallow trench isolation structure STI (i.e., along the direction away from the first opening 204), and along the direction away from the shallow trench isolation structure STI (i.e., along the direction away from the first opening 204), the line width W3 of the second opening 206a, the line width W2 of the second opening 206b, and the line width W1 of the second opening 206c decrease successively, and the interval D2 between the second opening 206a and the second opening 206b, and the interval D1 between the second opening 206b and the second opening 206c also decrease successively. Along the direction close to the shallow trench isolation structure STI (i.e., close to the first opening 204), the line width W1 of the second opening 206c is the same as the interval D1 between it and the second opening 206b, the line width W2 of the second opening 206b is the same as the interval D2 between it and the second opening 206a, and the line width W3 of the second opening 206a is the same as the interval D3 between it and the shallow trench isolation structure STI, i.e., W1=D1, W2=D2, and W3=D3.

[0062] Optionally, the line width W3 of the innermost second opening 206a is between 120nm and 500nm, and the line width W1 of the outermost second opening 206c is between 80nm and 200nm. D1, D2 and D3 are respectively between 80nm and 200nm.

[0063] In addition, it should be understood that, in this embodiment, the patterned mask layer 300 is a photoresist layer, but the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, the patterned mask layer 300 may also include an amorphous carbon layer, a bottom anti-reflection layer, a top anti-reflection layer, etc. In addition, in other embodiments of the present invention, the patterned mask layer 300 may be a patterned dielectric layer formed by dielectric material deposition, photoresist coating, photolithography, and stripping processes.

[0064] Please refer to Figure 7In step S4, the patterned mask layer 300 is used as a mask and the intermediate layer film 202 of the hard mask layer is used as an etching stop layer to etch the top layer film 203 and the intermediate layer film 202 of the hard mask layer at each second opening. The etching can stop on the top surface of the intermediate layer film 202 of the hard mask layer, or stop at the corresponding depth of the intermediate layer film 202 of the hard mask layer, thereby deepening each second opening to a desired depth. The deepened second openings penetrate the top layer film 203 of the hard mask layer and the bottom does not expose the substrate surface of the active areas AA2 and AA3. This step is to transfer the second openings in the patterned mask layer 300 to the hard mask layer, and because the bottom of each second opening still exposes the hard mask layer of corresponding thickness (i.e., the remaining intermediate film layer 202 and the bottom film 201), all the second openings on the outside of the shallow trench isolation structure STI on each side of the first opening 204 are equivalent to forming a comb-shaped opening, in which the hard mask layer between adjacent second openings serves as a spacer column (also referred to as "spacer") between adjacent second openings, and the hard mask layer between the innermost second opening 206a and the first opening 204 serves as a spacer column between the innermost second opening 206a and the first opening 204.

[0065] The remaining hard mask layer at the bottom of each second opening (ie, the remaining intermediate film layer 202 and bottom film 201 ) can play a desired role in limiting the longitudinal diffusion of oxygen at the second opening when the gate oxide layer is formed by thermal oxidation in the subsequent step S5 .

[0066] Optionally, the hard mask layer at each second opening is etched using the patterned mask layer 300 as a mask to deepen each second opening to a desired depth. The thickness of the intermediate film layer 202 remaining at the bottom of each second opening after deepening is

[0067] It should be understood that in other embodiments of the present invention, the hard mask layer formed in step S2 can also be a double-layer structure formed by stacking a silicon oxide layer (bottom film) and a silicon nitride layer (top film). In this case, in step S4, the hard mask layer at each second opening is etched using the patterned mask layer 300 as a mask. When each second opening is deepened to a desired depth, the etching stops at the corresponding depth of the silicon nitride layer of the double-layer structure, and the bottom of each deepened second opening does not expose the top surface of the silicon oxide layer of the double-layer structure.

[0068] Optionally, in order to prevent the longitudinal dimension of the oxide layer formed at each second opening from being too large and the length of the oxide layer formed at the outermost second opening 206c extending outward laterally from being too long, before performing the subsequent thermal oxidation of step S5 and after forming the patterned mask layer 300 having the second opening, or before performing the subsequent thermal oxidation of step S5 and after etching the hard mask layer at each second opening with the patterned mask layer 300 as a mask to deepen each second opening to a desired depth, the patterned mask layer 300 is also used as a mask to inject any suitable ions for suppressing the substrate oxidation rate into the substrate 200 of the active areas AA2 and AA3 below each second opening, so as to further reduce the substrate oxidation rate at the second opening in step S5, so as to shrink the bird's beak formed by the substrate at the second opening faster. The ions for suppressing the substrate oxidation rate include, for example, nitrogen ions.

[0069] Please refer to Figure 7 and Figure 8 In step S5, first, any appropriate removal process is selected according to the material properties of the patterned mask layer 300 to remove the patterned mask layer 300 and re-expose the surface of the device active area AA1 at the first opening 204. For example, when the patterned mask layer 300 is a photoresist, any appropriate dry stripping or wet stripping process can be used to remove the patterned mask layer 300. Next, using any suitable thermal oxidation process such as furnace thermal oxidation, the surface layer of the substrate of the device active area AA1 exposed at the first opening 204 directly reacts with oxygen and generates an oxide layer in situ. The oxide layer formed at the first opening 204 is subsequently used as the gate oxide layer HOX of the device (e.g., a high-voltage device). Since oxygen can also diffuse longitudinally from each second opening to the active areas AA2 and AA3 below the bottom of the second opening, a corresponding oxide layer can also be formed in the active areas AA2 and AA3 below the bottom of the second opening. Finally, the oxide layers formed at the bottom of each second opening are connected in sequence and finally connected to the shallow trench isolation structure adjacent to the innermost second opening 206a to form the shallow trench isolation structure. The bird's beak 207 of the structure has a more controllable size than that of the prior art, that is, without changing the size and structure of the shallow trench isolation structure STI and other oxidation conditions (that is, with minimal changes to the existing process), the size of the shallow trench isolation structure STI that is penetrated by oxygen and forms a bird's beak can be effectively controlled. It only needs to combine the bird's beak with controllable size and set a reasonable formation position of the metal silicide to ensure the good morphology of the metal silicide (because the bird's beak morphology here is usually uncontrollable and has a serious impact on the formation of the metal silicide on the substrate surface), and can effectively ensure the yield of the subsequent metal-to-metal silicide connection formed by the contact plug (CT).

[0070] During the thermal oxidation process in this step, firstly, since the size of the second opening is much smaller than that of the first opening and there is an oxygen barrier at the second opening, the substrate oxidation rate at the second opening is much smaller than that at the first opening, so the thickness of the oxide layer formed at the second opening is thinner than that formed at the first opening. Secondly, in the horizontal direction, since the line width and spacing of the second openings on each side of the first opening 204 are gradually reduced in the direction away from the first opening 204, the amount of oxygen passing through the second opening can be reduced in the direction away from the first opening 204, and the oxide layers formed at the bottom of the second openings can be connected in sequence, while the bird's beak shrinks faster, so that the bird's beak 207 formed at the end of the thermal oxidation is smaller in the horizontal direction and thinner in the vertical direction, especially when the size of the openings is gradually reduced and the size of the spacing between the openings is also gradually reduced, it is ensured that the oxide layer formed at the bottom of the second opening can be connected with the smallest volume, and the oxygen passing through the shallow trench isolation structure STI is blocked with the smallest size of the connected whole, that is, with the smallest bird's beak, the best shielding is achieved, and the bird's beak is small and the size is more controllable. Furthermore, the oxide layer formed under each second opening before being connected together is equivalent to forming a multi-layer barrier layer, which can prevent the oxygen that has diffused laterally from the first opening 204 through the shallow trench isolation structure STI from continuing to diffuse laterally outward. Therefore, by precisely controlling the setting of the second opening, the lateral size of the oxide layer formed outside the shallow trench isolation structure STI can be precisely controlled, and then the size of the bird's beak 207 near the shallow trench isolation structure STI can be precisely controlled, so that the bird's beak 207 formed on the active areas AA2 and AA3 at the end of thermal oxidation is as small and thin as possible in the lateral direction.

[0071] As an example, the thickness h of the bird's beak 207 near the shallow trench isolation structure STI is The width k ranges from 600 nm to 2000 nm.

[0072] Optionally, in order to further accelerate the formation of the gate oxide layer HOX at the first opening 204 and avoid the problem that the oxide layer formed at the second opening is still too large and too thick due to the long thermal oxidation time, any suitable ions for increasing the oxidation rate of the substrate 200 may be injected into the substrate 200 of the device active area AA1 exposed by the first opening 204 at any step node before performing thermal oxidation on the substrate 200 of the device active area AA1 exposed by the first opening 204 in step S5. For example, after forming the first opening in step S2 and before performing step S3, the ions for increasing the oxidation rate of the substrate 200 may be injected into the substrate 200 of the device active area AA1 exposed by the first opening 204 using the hard mask layer as a mask; after removing the patterned mask layer in step S5 and before performing thermal oxidation, the ions for increasing the oxidation rate of the substrate 200 may be injected into the substrate 200 of the device active area AA1 exposed by the first opening 204 using the hard mask layer as a mask. As an example, the ions used to increase the oxidation rate of the substrate 200 include at least one of oxygen ions, amorphization ions, and halogen ions. Among them, the implantation of oxygen ions can increase the oxygen content in the substrate 200, thereby increasing the oxidation rate of the substrate when the gate oxide layer HOX is formed; the amorphization ions include, for example, silicon ions, germanium ions, or argon ions, etc. The implantation of amorphization ions can form the single crystal silicon in the substrate 200 of the device active area AA1 into amorphous silicon, thereby increasing the substrate oxidation rate when the gate oxide layer HOX is formed; the halogen ions include, for example, at least one of chloride ions (Cl), fluorine ions (F), and bromide ions (Br). The implantation of halogen ions can act as a catalyst and has the effect of weakening the Si-O bond energy. Therefore, when the gate oxide layer HOX is subsequently formed at the first opening 204 by thermal oxidation, the SO bond energy of SiO2 of the formed gate oxide layer HOX is weaker, making it easier for oxygen to diffuse into, thereby increasing the oxidation rate of the substrate during oxidation when the gate oxide layer HOX is formed.

[0073] It should be understood that after the gate oxide layer HOX is formed, any appropriate subsequent processes may be continued.

[0074] In one embodiment of the present invention, after forming the gate oxide layer HOX, the manufacturing method further includes: removing the hard mask layer by any suitable process such as a wet etching process or a dry etching process. As an example, when the parameters such as the outer boundary position of the shallow trench isolation structure STI and the position of the outermost second opening 206c are reasonably set, while removing the bottom film 201 (i.e., silicon oxide) of the hard mask layer by the wet etching process, the oxide layer under at least part of the second opening including the outermost second opening 206c is removed to reduce or remove the bird's beak 207. In this case, the thickness of the bottom film 201 of the hard mask layer and the setting of the second opening 206c also determine the time of the wet etching. Therefore, the process of removing the bird's beak 207 by the wet etching is equivalent to also taking the outer interface position of the shallow trench isolation structure STI and the position parameters of the outermost second opening 206c as references, so that the process of removing the bird's beak 207 is relatively more controllable and reliable.

[0075] In another embodiment of the present invention, after forming the gate oxide layer HOX, the manufacturing method etches the bird's beak 207 (which may be only the area near the second opening 206c, or the area from the second opening 206c to the position of any second opening 206a on the inner side) according to the outer boundary position of the shallow trench isolation structure STI and the position of the outermost second opening 206c (or the position of each second opening) in some subsequent processes of etching the oxide, so as to remove the oxide layer under at least part of the second opening including the outermost second opening 206c, and reduce or remove the bird's beak 207. Obviously, the bird's beak structure removal process will be relatively more controllable and reliable because the outer boundary position of the shallow trench isolation structure STI and the position parameters of the outermost second opening are used as references.

[0076] In another embodiment of the present invention, after forming the gate oxide layer HOX (ie, after thermally oxidizing the device active region exposed by the first opening and the substrate below the second opening), the manufacturing method further comprises:

[0077] First, please refer to Fig. 9 , using any suitable process such as a wet etching process to remove the top layer film and the middle layer film of the hard mask layer;

[0078] Next, please refer to Fig.10 , forming a gate 208 on the gate oxide layer HOX at the first opening 204 by using a gate process;

[0079] Then, please continue to refer to Fig.10 , forming a sidewall spacer 209 on the sidewall of the gate 208 by using a sidewall spacer process;

[0080] Afterwards, a source region and a drain region are formed in the substrate on both sides of the gate by using a source-drain ion implantation process. In one example, the source region is formed in the surface layer of the active region AA2, and the drain region is formed in the surface layer of the active region AA3;

[0081] Next, a metal silicide 210 is formed on the top of the gate 208, the source region and the drain region by using a metal silicide process;

[0082] Afterwards, an interlayer dielectric layer 211 is deposited, and a contact plug 212 is formed on the metal silicide 210 on the top of the gate 208, the source region, and the drain region by using a contact hole etching and filling process. In this step, the metal silicide 210 and the contact plug 212 thereon can be controlled to be formed near the outer side of the outermost second opening 206c according to the formation position of the outermost second opening 206c, thereby ensuring the reliability of the formed metal silicide and contact plug. In addition, since the bird's beak 207 is small and thin, compared with the prior art, the distance between the contact plug 212 on the source region and the drain region and the gate 208 becomes smaller, the parasitic resistance is reduced, and it is beneficial to improve the device performance.

[0083] To summarize, the manufacturing method of the present invention, after etching the hard mask layer to form a first opening exposing the device active area defined by the shallow trench isolation structure, uses a patterned mask layer to mask the first opening, and forms a plurality of second openings in the area of ​​the patterned mask layer located outside the first opening, so that when the hard mask layer is etched with the patterned mask layer as a mask, the second opening is transferred to the hard mask layer, and the line width of the second opening gradually decreases in the direction away from the shallow trench isolation structure. When the patterned mask layer is removed and the device active area at the first opening is thermally oxidized to form a gate oxide layer, the second opening can be used to accurately control the size of the oxide layer (i.e., the bird's beak) generated outside the shallow trench isolation structure around the formed first opening, so that the bird's beak is as small and thin as possible and the size is more controllable. The principle is as follows: on the one hand, a small portion of oxygen will diffuse downward from the second opening into the substrate to form an oxide layer, and since the line width of the second opening outside the shallow trench isolation structure around the first opening gradually decreases in the direction away from the shallow trench isolation structure, the amount of oxygen passing through the second opening can be reduced in the direction away from the shallow trench isolation structure, and the oxide layer formed under each second opening can serve as a multi-layer barrier layer to prevent the oxygen that penetrates and diffuses laterally from the shallow trench isolation structure from continuing to diffuse outward, thereby accurately controlling the lateral size of the oxide layer formed outside the shallow trench isolation structure, and then accurately controlling the size of the bird's beak on the outside of the top of the shallow trench isolation structure, making the bird's beak as small and thin as possible.

[0084] In addition, after forming the gate oxide layer, the oxide layer below at least a portion of the second opening including the outermost second opening can be etched and removed based on the position of the outermost second opening and the outer boundary position of the shallow trench isolation structure around the first opening, thereby reducing or removing the bird's beak structure outside the shallow trench isolation structure. Obviously, the bird's beak structure removal process will be relatively more controllable and reliable because it has the outer boundary position of the shallow trench isolation structure and the position parameters of the outermost second opening as a reference.

[0085] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate and forming a shallow trench isolation structure in the substrate to define a device active region where a gate oxide layer is to be formed; forming a hard mask layer on the substrate and the shallow trench isolation structure, and etching the hard mask layer to form a first opening exposing the surface of the device active area; Forming a patterned mask layer, wherein the patterned mask layer masks the first opening, and forming a plurality of second openings above the substrate region outside the shallow trench isolation structure around the first opening, wherein the line width of the second openings gradually decreases in a direction away from the shallow trench isolation structure; Using the patterned mask layer as a mask, etching the hard mask layer at the bottom of each second opening to deepen the bottom surface of each second opening to a corresponding depth of the hard mask layer; The patterned mask layer is removed, and the device active area exposed by the first opening and the substrate below the second opening are thermally oxidized, the oxide layer formed at the first opening is used as the gate oxide layer required for the device, and the oxide layers formed at each second opening outside the shallow trench isolation structure are connected to the shallow trench isolation structure.

2. The manufacturing method according to claim 1, characterized in that After forming the first opening exposing the surface of the device active area and before forming the patterned mask layer, it also includes: under the mask of the hard mask layer, thermally oxidizing the device active area exposed by the first opening to form a sacrificial oxide layer; wet etching to remove the sacrificial oxide layer, and at the same time etching open the top of the shallow trench isolation structure around the first opening close to the device active area, so that the top of the device active area becomes lower and rounded; or; after forming the first opening exposing the surface of the device active area and before forming the patterned mask layer, it also includes: under the mask of the hard mask layer, wet etching the device active area exposed by the first opening, and at the same time etching open the top of the shallow trench isolation structure around the first opening close to the device active area, so that the top of the device active area becomes lower and rounded.

3. The manufacturing method according to claim 1, characterized in that: The hard mask layer includes a bottom film, an intermediate film and a top film stacked in sequence from bottom to top. When the hard mask layer at the bottom of each second opening is etched using the patterned mask layer as a mask, the etching stops at the top surface of the intermediate film or at a corresponding depth. The bottom film is silicon oxide, and the intermediate film is silicon oxynitride or silicon nitride.

4. The manufacturing method according to claim 3, characterized in that: When the bottom surface of each second opening is deepened to the corresponding depth of the hard mask layer, the thickness of the intermediate layer film remaining at the bottom of the second opening is 5. The manufacturing method according to claim 1, characterized in that: At any step node after forming the patterned mask layer and before thermally oxidizing the device active region exposed by the first opening and the substrate below the second opening, ions for suppressing the oxidation rate of the substrate are implanted into the substrate below the second opening using the patterned mask layer as a mask; And / or, at any step node before thermally oxidizing the device active region exposed by the first opening and the substrate below the second opening, ions for increasing the oxidation rate of the substrate are further implanted into the device active region exposed by the first opening.

6. The manufacturing method according to claim 5, characterized in that: The ions for suppressing the substrate oxidation rate include nitrogen ions, and / or the ions for increasing the substrate oxidation rate include at least one of oxygen ions, amorphization ions and halogen ions.

7. The manufacturing method according to any one of claims 1 to 6, characterized in that: On the outside of the shallow trench isolation structure, the spacing between the second openings gradually decreases along the direction away from the shallow trench isolation structure; and / or, on the outside of the shallow trench isolation structure, along the direction close to the shallow trench isolation structure, the line width of any second opening is the same as the spacing between any second opening and its adjacent second opening.

8. The manufacturing method according to claim 7, characterized in that: Has at least one of the following parameters: (1) On the outer side of the shallow trench isolation structure, along the direction away from the shallow trench isolation structure, the line width of the innermost second opening is between 120 nm and 500 nm; (2) On the outer side of the shallow trench isolation structure, along the direction away from the shallow trench isolation structure, the line width of the outermost second opening is between 80 nm and 200 nm; (3) On the outer side of the shallow trench isolation structure, along the direction away from the shallow trench isolation structure, the intervals between adjacent second openings and the interval between the innermost second opening and the shallow trench isolation structure are respectively between 80 nm and 200 nm; (4) The thickness of the bird's beak formed on the outer side of the shallow trench isolation structure is in the range of (5) The width of the bird's beak formed on the outer side of the shallow trench isolation structure is in the range of 600nm to 2000nm.

9. The manufacturing method according to claim 1, characterized in that: After thermally oxidizing the device active region exposed by the first opening and the substrate below the second opening, the method further includes: removing the hard mask layer; forming a gate on the gate oxide layer; forming a sidewall spacer on the sidewall of the gate; Using a source-drain ion implantation process to form a source region and a drain region in the substrate at both sides of the gate; Forming metal silicide on the top of the gate, the source region and the drain region by using a metal silicide process; Contact plugs are formed on the metal silicide on top of the gate, the source region, and the drain region.

10. The manufacturing method according to claim 1, characterized in that: After thermally oxidizing the device active area exposed by the first opening and the substrate below the second opening, the method further includes: etching and removing the oxide layer below at least a portion of the second opening including the outermost second opening according to the position of the outermost second opening and the outer boundary position of the shallow trench isolation structure around the first opening, so as to reduce or remove the bird's beak structure on the outer top of the shallow trench isolation structure.

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