Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps of: before a gate oxide layer is formed by thermal oxidation, performing injection of first ions (used for adjusting threshold voltage) and injection of second ions on a substrate in a gate oxide forming region under the masking action of the same patterned mask layer; a part of thickness of the substrate in the gate oxide forming area is etched to form a groove used for reducing the height of the top surface of the substrate, and then the inner surface of the groove is subjected to rapid thermal annealing treatment to repair the interface damage on the inner surface of the groove, so that the additional photomask cost is not increased, the step of forming a sacrificial oxide layer through thermal oxidation is omitted, and the manufacturing cost is reduced. Therefore, heat introduction is reduced, extra diffusion of doped ions in the drift region can be inhibited through the second ions when the gate oxide layer is formed through subsequent thermal oxidation, the beak problem is avoided, and the problem that the performance of the device is reduced due to the loss of the injected ions in the drift region is prevented. And the problem that the electrical parameters of the device are influenced by interface change is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] With the continuous miniaturization of semiconductor components and the requirements of specific application scenarios, current product designs often need to apply high-voltage devices. High-voltage devices are devices that can withstand higher voltages while ensuring that the gate is not broken down under high-voltage operation. Generally, the thickness of the gate oxide layer of high-voltage devices is much thicker than that of traditional medium-voltage devices and low-voltage devices. For example, the gate oxide layer thickness of a 1.1V low-voltage device is The gate oxide thickness of high voltage devices needs to reach above.

[0003] Please refer to Figure 1 At present, in order to achieve the purpose of increasing the height difference (i.e., the longitudinal distance) between the gate and the first metal layer (i.e., the top of the source contact plug) of the high-voltage device to improve the device breakdown voltage (BV), generally before growing the gate oxide layer 108 of the required thickness of the high-voltage device by the furnace tube oxidation method, a second conductive type (e.g., P-type) well 101 and shallow trench isolation structure are formed in the substrate 100 and a first conductive type (e.g., n-type) drift region 103a (a drain region will be formed on its surface later) and 103b (a source region will be formed on its surface later) and a second conductive type drift region 104a and 104b are formed by n-type and p-type ion implantation. After the structure is formed, a sacrificial oxide layer 106 of a certain thickness is grown in the area where the gate oxide layer needs to be grown by furnace tube oxidation under the mask of a hard mask layer 105 such as silicon nitride, so as to consume the silicon in the substrate 100 in the area. The formed sacrificial oxide layer 106 is then removed to reduce the surface height of the substrate in the area (for example, to form a groove 107 with a relatively lowered top surface of the substrate). The purpose is to increase the height difference between the subsequently formed gate and the first metal layer (Metal1) by reducing the surface height of the substrate, thereby increasing the breakdown voltage of the device, and then thermally oxidizing the substrate in the groove 107 to form a gate oxide layer 108 of the required thickness for the high-voltage device.

[0004] The above process has the following disadvantages: (1) From the perspective of physical structure, when the sacrificial oxide layer 106 and the gate oxide layer 108 are formed by furnace oxidation, due to the relatively long process time (e.g., 150 min) and high temperature, oxygen is easily diffused to the surface of the drift region and other regions, resulting in the formation of "bird beaks" 106a, 108a in the surface of these regions. The "bird beak" defect will have many adverse effects. For example, when the sacrificial oxide layer 106 is formed, the "bird beak" 106a will be generated on the surface of the drift region 103b due to the diffusion of oxygen. When the sacrificial oxide layer 106 is removed, the "bird beak" 106a will be formed. 06, the "bird's beak" 106a will be removed together, which will not only cause the loss of the injected ions in the drift region 103b, causing the device performance to deteriorate, but also cause the "bird's beak" 108a of the gate oxide layer 108 to become relatively more serious, affecting the electrical performance and reliability of the device; (2) The process temperature for growing the sacrificial oxide layer 106 and the gate oxide layer 108 is high and the process time is long, which will also aggravate the diffusion of the injected ions in the drift region 103b and other regions, thereby reducing the dose of the injected ions in these regions, thereby causing the device performance to deteriorate.

[0005] Therefore, a new solution is needed to improve or even eliminate the above disadvantages. Summary of the invention

[0006] The object of the present invention is to provide a method for manufacturing a semiconductor device, which can avoid the disadvantages of increasing the breakdown voltage of the device by forming and removing a sacrificial oxide layer.

[0007] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0008] providing a substrate in which a drift region is formed;

[0009] forming a patterned hard mask layer on the substrate, wherein the patterned hard mask layer has an opening exposing a surface of the substrate in a gate oxide formation region;

[0010] Using the patterned hard mask layer as a mask, implanting a first ion and a second ion into the substrate exposed by the opening, wherein the first ion is used to adjust the threshold voltage, and the second ion is used to suppress the diffusion of doped ions in the drift region during the process of thermal oxidation to form a gate oxide layer, so as to form a first ion implantation layer located at an upper portion and implanted with the first ions, and a second ion implantation layer located at a lower portion and implanted with the second ions in the substrate exposed by the opening;

[0011] Using the patterned hard mask layer as a mask, etching and removing a portion of the thickness of the substrate exposed by the opening to form a trench, wherein a portion of the thickness or the entire thickness of the first ion implantation layer is retained below the bottom of the trench;

[0012] Performing a rapid thermal annealing treatment on the inner surface of the groove to repair interface damage on the inner surface of the groove;

[0013] A gate oxide layer is formed in the trench by thermal oxidation.

[0014] Optionally, using the patterned hard mask layer as a mask, the first ions are first implanted into the substrate exposed by the opening, and then the second ions are implanted to form the ion implantation layer; or, alternatively, using the patterned hard mask layer as a mask, multiple ion implantations with different implantation depths are used to complete the implantation of the first ions and / or the second ions, and when the first ions are implanted to the maximum depth into the substrate exposed by the opening, a common implantation method is used to implant the second ions with the shallowest required implantation depth into the substrate exposed by the opening.

[0015] Optionally, the second ions include carbon; and / or the implantation depth of the second ions is

[0016]

[0017] Optionally, etching removes the exposed thickness to form the trench; and / or, after forming the gate oxide layer, a partial thickness or the entire thickness of the first ion implantation layer is retained below the bottom of the gate oxide layer.

[0018] Optionally, a rapid thermal annealing treatment is performed on the inner surface of the trench in an atmosphere containing oxygen and / or nitrogen to form a film having a thickness of Interface repair layer.

[0019] Optionally, the step of forming a drift region in the substrate includes:

[0020] Performing ion implantation of a first conductivity type in the substrate to form a well region;

[0021] forming a shallow trench isolation structure in the substrate to define a corresponding device area;

[0022] Performing ion implantation of the first conductivity type and ion implantation of the second conductivity type on the well regions on both sides of the gate oxide forming region, respectively, to form a drift region of the first conductivity type and a drift region of the second conductivity type in the surface layer of the well region;

[0023] Wherein, the first ions are of the first conductivity type.

[0024] Optionally, when forming the corresponding drift region, the corresponding ion implantation dose is 4E12-11E12, and the energy is 10KeV-1000KeV.

[0025] Optionally, after forming the gate oxide layer, the method further comprises:

[0026] Forming a gate on the gate oxide layer; performing source-drain ion implantation on the drift region of the second conductivity type on both sides of the gate oxide layer using ions of the second conductivity type to form a source region and a drain region;

[0027] A contact plug and a first metal layer located on top of the contact plug are formed on the substrate having the source region and the drain region formed thereon.

[0028] Optionally, the first conductivity type is p-type and the second conductivity type is n-type, or the first conductivity type is n-type and the second conductivity type is p-type; the p-type ions used in the manufacturing method include at least one of boron, indium and gallium, and the n-type ions used include at least one of phosphorus, arsenic and antimony.

[0029] Optionally, the step of forming a patterned hard mask layer on the substrate includes:

[0030] Covering the substrate with a hard mask layer and coating photoresist on the hard mask layer;

[0031] Performing photolithography on the photoresist, and using the photoresist after photolithography as a mask, etching and opening the hard mask layer to form the patterned hard mask layer;

[0032] The photoresist after photolithography is removed at any appropriate step node after etching to open the hard mask layer and before etching to remove a portion of the thickness of the substrate in the gate oxide region to form a trench.

[0033] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0034] 1. Before forming a gate oxide layer by thermal oxidation under the masking effect of a patterned mask layer, a shallow first ion (for adjusting a threshold voltage) and a larger second ion are implanted into the substrate in the gate oxide formation region under the masking effect of the same patterned mask layer. This will not increase the additional mask cost on the one hand, and can also suppress the additional diffusion of the ions doped in the drift region by implanting the larger second ions when the gate oxide layer is subsequently formed by thermal oxidation. This prevents the loss of the implanted ions in the drift region when the gate oxide layer is formed by thermal oxidation, thereby avoiding degradation of device performance.

[0035] 2. Under the masking effect of the same graphic mask layer, after the first ion implantation and the second ion implantation, and before the gate oxide layer is formed by thermal oxidation, the substrate in the gate oxide formation area is first etched (for example, wet etching) to remove a portion of the thickness to form a groove for lowering the top surface of the substrate in the gate oxide formation area, and the inner surface of the groove is further subjected to rapid thermal annealing to repair the interface damage on the inner surface of the groove. On the one hand, no additional mask cost is added, and on the other hand, the step of thermally oxidizing to form a sacrificial oxide layer can be omitted. In this way, the height difference between the subsequently formed gate and the first metal layer can meet the requirements through the groove, thereby improving the breakdown voltage of the device, and reducing heat introduction, thereby avoiding the problem of bird's beak when forming the sacrificial oxide layer in the prior art, and preventing the loss of the injected ions in the drift region when forming the sacrificial oxide layer by thermal oxidation. In addition, the problem of aggravating the formation of the bird's beak of the gate oxide layer due to first thermally oxidizing to form the sacrificial oxide layer and then etching to remove the sacrificial oxide layer can be avoided, and the problem of affecting the electrical parameters of the device due to interface changes can be avoided, thereby further improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0037] Figure 1 It is a schematic diagram of the cross-sectional structure of a bird's beak problem in an existing high-voltage device.

[0038] Figure 2 The flowchart of the method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0039] Figure 3 to Figure 4 It is a schematic diagram of a device cross-sectional structure in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0040] Figure 5 It is a schematic diagram of a device cross-sectional structure in a method for manufacturing a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0041] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0043] Please refer to Figure 2 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0044] S1, providing a substrate, and forming a drift region in the substrate;

[0045] S2, forming a patterned hard mask layer on the substrate, wherein the patterned hard mask layer has an opening exposing the surface of the substrate in a gate oxide formation region;

[0046] S3, using the patterned hard mask layer as a mask, performing first ion implantation and second ion implantation on the substrate exposed by the opening, wherein the first ion is used to adjust the threshold voltage, and the second ion is used to suppress diffusion of doped ions in the drift region during thermal oxidation to form a gate oxide layer, so as to form a first ion implantation layer located at an upper portion and implanted with the first ions, and a second ion implantation layer located at a lower portion and implanted with the second ions, in the substrate exposed by the opening;

[0047] S4, using the patterned hard mask layer as a mask, etching away a portion of the thickness of the substrate exposed by the opening to form a trench, wherein a portion of the thickness or the entire thickness of the first ion implantation layer is retained below the bottom of the trench;

[0048] S5, performing a rapid thermal annealing treatment on the inner surface of the groove to repair interface damage on the inner surface of the groove;

[0049] S6, forming a gate oxide layer by thermal oxidation in the trench.

[0050] In step S1, refer to Figure 3 In (A), first, the provided substrate 100 may be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC) or silicon on insulator (SOI), etc.; then, through corresponding photolithography and ion implantation processes, ions of a first conductivity type (e.g., p-type) and ions of a second conductivity type (e.g., n-type) are used to implant ions into different regions of the substrate 100, respectively, so as to form mutually spaced n-type well regions and p-type well regions in the substrate 100, wherein the n-type well region serves as an active region of a pMOS device, and the p-type well region serves as an active region of an nMOS device. The p-type ions used for the p-type well region may include at least one of boron (B), indium (In) and gallium (Ga), and the n-type ions used for forming the n-type well region may include at least one of phosphorus (P), arsenic (As) and antimony (Sb).

[0051] In step S1, refer to Figure 3 (A) in the figure, then, a number of shallow trench isolation structures 102 are formed in the substrate 100, a portion of the shallow trench isolation structures 102 are located at the junction of different device regions, thereby isolating the high-voltage device region (i.e., the active region of the high-voltage device) and the non-high-voltage device region (i.e., the active region of the non-high-voltage device, such as the active region of the medium-voltage device region and the low-voltage device region), and another portion of the shallow trench isolation structures 102 can be formed in the corresponding well region (e.g., the well region of the high-voltage device region) 101, which is used to define the region in the well region (or active region) where the source region, drain region, channel region, body contact region and other structures are to be formed. Figure 3 (A) shows only one well region 101, and the line width of the shallow trench isolation structure 102 used to isolate different device regions is larger than the shallow trench isolation structure 102 located inside the corresponding device region, thereby ensuring the isolation performance between different device regions and at the same time ensuring the process window during the manufacture of the internal structure of the corresponding device region (such as the source region, the drain region, etc.).

[0052] Please refer to Figure 3 In (A), as an example, the specific steps of forming the shallow trench isolation structure 102 in the substrate 100 include:

[0053] (1) A pad oxide layer (PAD OX, not shown) is formed on the substrate 100 by any suitable process such as thermal oxidation, atomic layer deposition or plasma enhanced chemical vapor deposition, and a hard mask layer such as silicon nitride (not shown) is further deposited on the pad oxide layer by chemical vapor deposition, and the hard mask layer is etched by photolithography and etching processes to form a patterned hard mask layer (not shown) for defining a shallow trench formation area. The pad oxide layer can serve as a stress buffer layer when depositing the hard mask layer and the subsequent barrier layer, and can also serve as a barrier layer for well ion implantation and a stop layer in the process of removing the hard mask layer and the barrier layer.

[0054] (2) Using the patterned hard mask layer as a mask, the pad oxide layer and the substrate 100 are etched to form a shallow trench (not shown) in the substrate 100 .

[0055] (3) A linear oxide layer (not shown) is formed on the inner surface of the shallow trench by thermal oxidation, atomic layer deposition or plasma enhanced chemical vapor deposition, and an insulating dielectric material (not shown) is further deposited by a chemical vapor deposition process to fill the shallow trench.

[0056] (4) The top of the insulating dielectric material is planarized to the top surface of the patterned hard mask layer by a chemical mechanical polishing process, thereby removing excess insulating dielectric material to form a shallow trench isolation structure filled in the shallow trench.

[0057] (5) Removing the patterned hard mask layer by a wet etching process.

[0058] In step S1, then, refer to Figure 3In (B), a photoresist is coated on the top of the shallow trench isolation structure 102 and the well region 101, and a photolithography process such as exposure and development is performed to form a patterned photoresist layer (not shown) for defining the formation area of ​​the n-type drift region; using the patterned photoresist layer as a mask, n-type ions are implanted into the well region 101, and the implantation depth is deeper than the bottom of the shallow trench isolation structure 102, thereby forming n-type drift regions 103a and 103b, for example, the implantation dose of the n-type ions is 4E12-11E12, and the energy is 10KeV-10 00KeV; after removing the patterned photoresist layer, re-coating the photoresist and performing photolithography processes such as exposure and development, a patterned photoresist layer (not shown) for defining the formation area of ​​the p-type drift region is formed, and the patterned photoresist layer is used as a mask to perform p-type ion implantation on the well region 101, and the implantation depth is deeper than the bottom of the shallow trench isolation structure 102, thereby forming p-type drift regions 104a and 104b, for example, the implantation dose of the p-type ions is 4E12 to 11E12, and the energy is 10KeV to 1000KeV. Then the patterned photoresist layer is removed. In other embodiments of the present invention, the p-type drift regions 104a and 104b can be formed first by corresponding photolithography processes and ion implantation processes, and then the n-type drift regions 103a and 103b are formed. The n-type drift regions 103a and 103b are formed together, and the p-type drift regions 104a and 104b are formed together, and any one of the n-type drift region 103a and the p-type drift region 104a can be implanted by a single time or by a combination of different implant energies, implant doses, and elements.

[0059] Wherein, when the semiconductor device to be manufactured is a high-voltage transistor, the formed well region 101 is a p-type deep well, the formed n-type drift regions 103a and 103b are separated on both sides of the region where the gate oxide is to be formed (i.e., the gate oxide formation region), and the surface layer thereof is used to form the source region and the drain region later, the p-type drift region 104a is located outside the n-type drift region 103a, and the p-type drift region is located outside the n-type drift region 104b. Optionally, the p-type drift regions 104a and 104b are respectively part of the same annular p-type drift region. As an example, the p-type ions used for the p-type drift regions 104a and 104b may include at least one of the boron (B) element, the indium (In) element, and the gallium (Ga) element, and the n-type ions used to form the n-type drift regions 103a and 103b may include at least one of the phosphorus (P) element, the arsenic (As) element, and the antimony (Sb) element.

[0060] In this embodiment, the device to be formed (for example, a high voltage device) is an asymmetric structure with asymmetric source and drain. Figure 3 and Figure 4, its n-type drift regions 103a and 103b are asymmetrically separated on both sides of the region where the gate oxide is to be formed (i.e., the gate oxide formation region), the n-type drift region 103b is used to form the source region 112s, and the n-type drift region 103a is used to form the drain region 112d, and the distance between the region where the n-type drift region 103a is used to form the drain region 112d and the region where the gate oxide is to be formed (i.e., the gate oxide formation region) is larger than the distance between the region where the n-type drift region 103b is used to form the source region 112s and the region where the gate oxide is to be formed (i.e., the gate oxide formation region), and there is no corresponding shallow trench isolation structure separating the n-type drift region 103b and the p-type drift region 104b.

[0061] In step S2, please refer to Figure 3 In (C), first, silicon nitride or silicon oxynitride or other materials are deposited on the surfaces of the drift regions 103a, 103b, 104a, 104b and the shallow trench isolation structure 102 to form a hard mask layer, and a photoresist 200 is coated on the hard mask layer; then, the photoresist 200 is photolithographically processed with the aid of a mask for threshold voltage ion implantation (which is also a mask for defining a gate oxide formation region), and the hard mask layer is etched open using the photoresist 200 after photolithography as a mask, A patterned hard mask layer 105 is formed, which masks the shallow trench isolation structure 102 and the various drift regions 103a, 103b, 104a, 104b, and has an opening 105a that exposes the substrate surface of the gate oxide formation area (i.e., the surface of the well region 101 between the drift regions 103a, 103b), thereby defining the gate oxide formation area (which is also the area where threshold voltage ion implantation is required) through the opening 105a.

[0062] In step S3, please continue to refer to Figure 3 In (C), the patterned hard mask layer 105 is used as a mask, and the first ions (for example, the first conductive type) of the same conductivity type as the well region 101 can be used to perform shallow depth implantation on the well region 101 exposed at the opening 105a, thereby forming a first ion implantation layer 109a, and then the second ions are used to perform greater depth implantation on the well region 101 exposed at the opening 105a, thereby forming a second ion implantation layer 109b located below the bottom of the first ion implantation layer 109a. The first ions are used to adjust the threshold voltage, and the second ions are used to suppress the diffusion of the doped ions in the drift regions 103a, 103b, etc. during the subsequent thermal oxidation process to form the gate oxide layer. Among them, the bottom of the first ion implantation layer 109a can be connected to the top of the second ion implantation layer 109b, or they can be separated. However, since the implantation of the first ions and the implantation of the second ions are both performed using the patterned hard mask layer 105 as a mask, the first ion implantation layer 109a and the second ion implantation layer 109b are aligned in the longitudinal direction.

[0063] The first ion implantation may be a single ion implantation or multiple ion implantations with different implantation depths, and the second ion implantation may be a single ion implantation or multiple ion implantations with different implantation depths.

[0064] In one embodiment of the present invention, the first ion is implanted by multiple ion implantations with different implantation depths, and the second ion is implanted by multiple ion implantations with different implantation depths, and the first ion implantation and the second ion implantation are performed in an unrestricted order. Optionally, when the first ion is implanted to the maximum depth in the well region 101 exposed by the opening 105a using the patterned hard mask layer 105 as a mask, the second ion with the shallowest required implantation depth is implanted into the well region 101 exposed by the opening 105a by a co-implantation method, thereby making the top of the second ion implantation layer 109b connected to the bottom of the first ion implantation layer 109a, so that the second ion implantation layer 109b has a better inhibitory effect on the ion diffusion in the first ion implantation layer 109a.

[0065] In addition, it should be understood that the first ion implantation is to adjust the threshold voltage of the device, and the surface silicon of the substrate in this area needs to be consumed to form a gate oxide layer later. Therefore, by designing the first ion implantation process, the first ion implantation layer 109a formed can be an ion implantation layer with a sufficient thickness extending downward from the substrate surface, such as Figure 3 As shown in (C), when the groove 107 is formed, the surface portion of the first ion implantation layer 109a is removed, and after the gate oxide layer is subsequently formed, a portion of the thickness of the first ion implantation layer 109a below the bottom of the gate oxide layer can be retained without being oxidized to adjust the threshold voltage of the device; the first ion implantation process can also be designed to make the formed first ion implantation layer 109a an ion implantation layer extending downward from a corresponding height below the substrate surface to a sufficient thickness, and when the groove 107 is formed, the first ion implantation layer 109a is not etched or only a portion of the thickness of the first ion implantation layer 109a is etched and removed, and after the gate oxide layer is subsequently formed, a portion of the thickness or the entire thickness of the first ion implantation layer 109a below the bottom of the gate oxide layer can be retained without being oxidized to adjust the threshold voltage of the device.

[0066] As an example, the second ions may include carbon (C) element, and the implantation depth of the second ions may be

[0067] Among them, when the first ion is n-type, it can include at least one of phosphorus (P) element, arsenic (As) element, and antimony (Sb) element; when the first ion is p-type, it can include at least one of boron (B) element, indium (In) element, and gallium (Ga) element.

[0068] It should be understood that the threshold voltage ion implantation of the nMOS device region and the pMOS device region needs to be performed separately, the first ion implanted in the nMOS device region is p-type, and the first ion implanted in the pMOS device region is n-type. Usually, the depth and dose of the threshold voltage ion implantation need to be set according to the threshold voltage requirements of the device.

[0069] In this embodiment, after the first ion and the second ion are implanted, the photoresist 200 is removed by any suitable process such as a wet stripping process or a dry stripping process. However, in other examples of the present invention, the photoresist 200 may be removed by any suitable process such as a wet stripping process or a dry stripping process at any suitable step node after performing step S3 (i.e., etching to open the hard mask layer to form a patterned hard mask layer 105) and before performing step S6 (i.e., thermally oxidizing to form a gate oxide layer).

[0070] In step S4, please refer to Figure 3 In (D), under the masking effect of the patterned hard mask layer 105, a plasma dry etching or any other suitable etching process is used to etch away a portion of the thickness of the first ion implantation layer 109a at the opening to form a groove 107 of a desired depth. The main function of the groove 107 is to reduce the height of the top surface of the substrate to increase the height difference between the gate and the first metal layer to be formed in the device region later, thereby increasing the breakdown voltage of the device. In this step, after the groove 107 is formed, a portion of the thickness of the first ion implantation layer 109a is retained below the bottom of the groove 107. On the one hand, the first ions of the remaining first ion implantation layer 109a can be used to adjust the threshold voltage of the device. On the other hand, the second ion implantation layer 109b is retained to the greatest extent, which can maximally suppress the diffusion of the doped ions in the drift regions 103a, 103b, etc. during the process of thermal oxidation to form the gate oxide layer.

[0071] As an example, under the masking effect of the patterned hard mask layer 105, when etching the first ion implantation layer 109a at the opening 105a, multi-step etching (for example, dry etching followed by wet etching) or direct downward etching using HNA acid (a mixed solution of hydrofluoric acid, nitric acid, acetic acid and water) can be used to etch away a portion of the thickness of the first ion implantation layer 109a at the opening 105a. While forming a groove 107 of the required depth, the top corner of the active area can also be exposed and rounded (not shown), which is conducive to the subsequent formation of a gate oxide layer with a better morphology.

[0072] As an example, the exposed portion at the opening 105a is removed by etching. In this example, the exposed portion of the opening 105a is removed. The first ion implantation layer 109a is thick, that is, the depth of the trench 107 relative to the top surface of the surrounding substrate (or the height difference between the bottom surface of the trench 107 and the surface of the active area, or the etching depth of the trench 107) is

[0073] In addition, it should be understood that it is usually necessary to manufacture devices with different operating voltages on the same substrate, wherein the thickness of the gate oxide layer of a high-voltage device is generally much thicker than that of a medium-voltage device and a low-voltage device. Therefore, when devices requiring different operating voltages coexist on the same substrate, the etching depth of the groove 107 can also be reasonably set according to the thickness difference between the gate oxide layer thickness required by the device region where it is located and the gate oxide layer thickness required by other device regions, and is not limited to the above-mentioned example of etching depth. Thus, the height difference of the gate oxide layer between the device region and other device regions is balanced by the effect of lowering the height of the substrate surface by the groove 107, thereby avoiding excessive height difference of the gate oxide layer in different device regions, which affects the uniformity of subsequent film layers deposited after the gate oxide layer is formed, and further improving the performance and yield of the final product.

[0074] In step S5, please refer to Figure 3 In (E), in an atmosphere containing oxygen, the inner surface of the groove 107 is subjected to a rapid thermal annealing process. The rapid thermal annealing process can, on the one hand, repair the interface damage on the inner surface of the groove 107 caused by the previous etching process, etc., to avoid the possible interface damage affecting the electrical parameters of the device, and on the other hand, a layer with a thickness of The interface repair layer 108b can block or reduce the lateral diffusion of oxygen in the subsequent thermal oxidation process to form the gate oxide layer 108, and is beneficial to the morphology control of the gate oxide layer 108 and reduces the formation of bird's beak. As an example, the interface repair layer 108b is a silicon oxide layer with a thickness of Because the surface height of the substrate in this area is lowered by etching in step S4, instead of the method of in-situ generation of a sacrificial oxide layer by a furnace tube process in the prior art to consume substrate silicon to lower the substrate surface height, in these processes before thermal oxidation to form a gate oxide layer, compared with the prior art, the introduction of a lot of thermal budget is reduced, thereby greatly reducing the undesirable ion diffusion phenomenon, and at the same time avoiding the bird's beak effect caused by the in-situ growth stage of the sacrificial oxide layer.

[0075] In step S6, please refer to Figure 3In (F), a corresponding thermal oxidation process recipe (gate oxide recipe) is set according to the thickness requirement of the gate oxide layer of the device (e.g., a high-voltage device). According to the process recipe, a high-temperature furnace tube oxidation process is used to thermally oxidize a portion of the thickness of the substrate 100 at the opening 107 (in this example, a portion of the thickness of the first ion implantation layer 109a is thermally oxidized) under the masking effect of the patterned hard mask layer 105, and then a gate oxide layer 108 of a desired thickness is grown in the trench 107. As an example, the process temperature for thermally oxidizing the gate oxide layer 108 is 920° C. to 1000° C. In this step, after the gate oxide layer 108 is formed, a portion of the thickness of the first ion implantation layer 109a is retained below the bottom of the gate oxide layer 108 and is not oxidized. The retained first ion implantation layer 109a is used to adjust the threshold voltage of the device.

[0076] It should be understood that during the thermal oxidation process, on the one hand, the second ions (e.g., carbon ions) doped in the second ion implantation layer 109b can prevent the problem of ion loss caused by the additional diffusion of the ions already doped in the drift regions 103a and 103b around the trench 107; on the other hand, the interface repair layer 108b can block or reduce the lateral diffusion of oxygen and is beneficial to the morphology control of the gate oxide layer 108, thereby preventing the surface layer of the drift region 103b from being oxidized to form a "bird's beak". In addition, when the interface repair layer 108b is a silicon oxide layer, it will eventually merge with the oxide layer grown during the thermal oxidation process and become a part of the gate oxide layer 108.

[0077] After forming the required gate oxide layer 108 in step S6, please refer to Figure 4 , the patterned hard mask layer 105 can also be removed by any suitable process such as wet etching, and an etching protection layer (which can be silicon oxide) 110 is formed, and polysilicon is deposited and gate photolithography and etching are performed, so as to form a gate 111 on the gate oxide layer 108. Next, a sidewall (not shown) is formed on the sidewall of the gate 111, and source and drain ion implantation is performed to form a source region 112s and a drain region 112d, and further a body contact region 112p whose conductivity type is inverse to that of the source region 112s and the drain region 112d is formed by ion implantation. Then, a metal silicide (not shown) is formed on the top surface of the source region 112s, the drain region 112d, the body contact region 112p and the gate 111 by a metal silicide process, and a contact plug (not shown) is formed on the metal silicide on the source region 112s, the drain region 112d, the body contact region 112p and the gate 111 by a contact hole etching and filling process. Then, a first metal layer (Metal 1, not shown) electrically connected to the contact plug is formed by a copper interconnection process, so as to lead the source region 112 s , the drain region 112 d , the body contact region 112 p and the gate 111 outward.

[0078] It is worth noting that Figure 3 to Figure 4 The device (eg, a high voltage device) formed in the embodiment shown is an asymmetric structure with asymmetric source and drain. Figure 4 The gate 111 formed thereby continuously extends from the top surface of the gate oxide layer 108 through the top surface of the drift region 103a close to the gate 111 to the top surface of the shallow trench isolation structure 102 in the drift region 103a close to the gate 111 along the direction close to the drain region 112d, and the source region 112s and the drain region 112d are on both sides of the gate 111 and at different distances from the gate 111. However, the technical solution of the present invention is not only applicable to the above-mentioned device structure with asymmetric source and drain, but also to the device structure with symmetric source and drain, please refer to Figure 5 In the device structure with symmetric source and drain, one side of the formed gate 111 extends continuously from the top surface of the gate oxide layer 108 through the top surface of the drift region 103a close to the gate 111 to the top surface of the shallow trench isolation structure 102 in the drift region 103a close to the gate 111 along the direction approaching the drain region 112d, and the other side of the gate 111 extends continuously from the top surface of the gate oxide layer 108 through the top surface of the drift region 103b close to the gate 111 to the top surface of the shallow trench isolation structure 102 in the drift region 103b close to the gate 111 along the direction approaching the source region 112s. The distances from the source region 112s and the drain region 112d to the gate 111 are the same and are symmetrical about the midline of the gate 111. The gate 111 itself is also symmetrical about the midline of the gate 111. Among them, the linearly symmetrical n-type drift regions 103a and 103b are symmetrically separated on both sides of the region where gate oxide is to be formed (i.e., the gate oxide formation region), and corresponding shallow trench isolation structures are formed in the n-type drift regions 103a and 103b, and the shallow trench isolation structures in the n-type drift regions 103a and 103b are also symmetrically separated on both sides of the region where gate oxide is to be formed (i.e., the gate oxide formation region); the p-type drift region 104a and the n-type drift region 103a are separated by a corresponding shallow trench isolation structure, and the p-type drift region 104b and the n-type drift region 103b are separated by a corresponding shallow trench isolation structure, and the two shallow trench isolation structures and the p-type drift regions 104a and 104b are also correspondingly symmetrically separated on both sides of the region where gate oxide is to be formed (i.e., the gate oxide formation region).

[0079] In summary, the manufacturing method of the semiconductor device of the present invention, under the masking effect of the same patterned mask layer, performs the first ion implantation (for adjusting the threshold voltage) and the second ion implantation into the substrate in the gate oxide formation area. This does not increase the additional mask cost on the one hand, and can also suppress the additional diffusion of the ions already doped in the drift region by the second ions when the gate oxide layer is subsequently formed by thermal oxidation. This prevents the loss of the ions already implanted in the drift region when the gate oxide layer is formed by thermal oxidation, thereby avoiding the degradation of device performance. Furthermore, under the masking effect of the same graphic mask layer, a portion of the thickness of the substrate in the gate oxide formation area is etched away to form a groove for lowering the top surface of the substrate in the gate oxide formation area, and the interface damage on the inner surface of the groove is repaired by a rapid thermal annealing process. On the one hand, no additional mask cost is added, and on the other hand, the step of thermally oxidizing to form a sacrificial oxide layer can be omitted. In this way, the height difference between the subsequently formed gate and the first metal layer can be increased through the groove, thereby improving the breakdown voltage of the device, and heat introduction can be reduced, avoiding the problem of bird's beak when forming the sacrificial oxide layer in the prior art, and preventing the loss of injected ions in the drift region when thermally oxidizing to form the sacrificial oxide layer. In addition, the problem of aggravating the formation of the bird's beak of the gate oxide layer due to first thermally oxidizing to form the sacrificial oxide layer and then etching to remove the sacrificial oxide layer can be avoided, and the problem of affecting the electrical parameters of the device due to interface changes can be avoided, thereby further improving the device performance.

[0080] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate in which a drift region is formed; forming a patterned hard mask layer on the substrate, wherein the patterned hard mask layer has an opening exposing a surface of the substrate in a gate oxide formation region; Using the patterned hard mask layer as a mask, implanting a first ion and a second ion into the substrate exposed by the opening, wherein the first ion is used to adjust the threshold voltage, and the second ion is used to suppress the diffusion of doped ions in the drift region during the process of thermal oxidation to form a gate oxide layer, so as to form a first ion implantation layer located at an upper portion and implanted with the first ions, and a second ion implantation layer located at a lower portion and implanted with the second ions in the substrate exposed by the opening; Using the patterned hard mask layer as a mask, etching and removing a portion of the thickness of the substrate exposed by the opening to form a trench, wherein a portion of the thickness or the entire thickness of the first ion implantation layer is retained below the bottom of the trench; Performing a rapid thermal annealing treatment on the inner surface of the groove to repair interface damage on the inner surface of the groove; A gate oxide layer is formed in the trench by thermal oxidation.

2. The manufacturing method according to claim 1, characterized in that Using the patterned hard mask layer as a mask, the first ions are first implanted into the substrate exposed by the opening, and then the second ions are implanted; or, using the patterned hard mask layer as a mask, multiple ion implantations with different implantation depths are used to complete the first ion implantation and / or the second ion implantation, and when the first ions are implanted at the maximum depth into the substrate exposed by the opening, the second ions with the shallowest required implantation depth are implanted into the substrate exposed by the opening by a common implantation method.

3. The manufacturing method according to claim 1, characterized in that: The second ions include carbon; and / or the implantation depth of the second ions is 4. The manufacturing method according to claim 1, characterized in that: The exposed portion of the opening is removed by etching. thickness to form the trench; and / or, after forming the gate oxide layer, a partial thickness or the entire thickness of the first ion implantation layer is retained below the bottom of the gate oxide layer.

5. The manufacturing method according to claim 1, characterized in that: The inner surface of the trench is subjected to a rapid thermal annealing process in an atmosphere containing oxygen to form a thin film having a thickness of Interface repair layer.

6. The manufacturing method according to any one of claims 1 to 5, characterized in that: The step of forming a drift region in the substrate comprises: Performing ion implantation of a first conductivity type in the substrate to form a well region; forming a shallow trench isolation structure in the substrate to define a corresponding device area; Performing ion implantation of the first conductivity type and ion implantation of the second conductivity type on the well regions on both sides of the gate oxide forming region, respectively, to form a drift region of the first conductivity type and a drift region of the second conductivity type in the surface layer of the well region; Wherein, the first ions are of the first conductivity type.

7. The manufacturing method according to claim 6, characterized in that: When forming the corresponding drift region, the corresponding ion implantation dose is 4E12-11E12, and the energy is 10KeV-1000KeV.

8. The manufacturing method according to claim 6, characterized in that: After forming the gate oxide layer, the method further comprises: forming a gate on the gate oxide layer; Using ions of the second conductivity type to perform source and drain ion implantation on the drift region of the second conductivity type on both sides of the gate oxide layer to form a source region and a drain region; A contact plug and a first metal layer located on top of the contact plug are formed on the substrate having the source region and the drain region formed thereon.

9. The manufacturing method according to claim 8, characterized in that: The first conductivity type is p-type and the second conductivity type is n-type, or the first conductivity type is n-type and the second conductivity type is p-type; the p-type ions used in the manufacturing method include at least one of boron, indium and gallium, and the n-type ions used include at least one of phosphorus, arsenic and antimony.

10. The manufacturing method according to claim 1, characterized in that: The step of forming a patterned hard mask layer on the substrate comprises: Covering the substrate with a hard mask layer and coating photoresist on the hard mask layer; Performing photolithography on the photoresist, and using the photoresist after photolithography as a mask, etching and opening the hard mask layer to form the patterned hard mask layer; The photoresist after photolithography is removed at any appropriate step node after etching to open the hard mask layer and before etching to remove a portion of the thickness of the substrate in the gate oxide region to form a trench.

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