Gain adjusting circuit of voltage-controlled oscillator of charge pump phase-locked loop and charge pump phase-locked loop
By designing a gain adjustment circuit in the voltage-controlled oscillator of the charge pump phase-locked loop, the problem of KVCO cannot be adjusted is solved, and effective control of noise and optimization of phase noise is achieved.
Patent Information
- Application Number
- CN202311415486.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-28
- Publication Date
- 2025-05-06
AI Technical Summary
The KVCO of the voltage-controlled oscillator of the existing charge pump phase-locked loop cannot be adjusted, resulting in enhanced noise amplification capability and affecting the optimization of phase noise.
A gain adjustment circuit for a voltage-controlled oscillator with a charge pump phase-locked loop is designed, and the adjustability of KVCO is achieved through the combination of calibration output module, gear adjustment module and calibration control module.
By reducing the value of KVCO, the amplification capability of noise is reduced, and the phase noise performance of the charge pump phase lock loop is optimized.
Smart Images
Figure CN119945423A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of charge pump phase-locked loops, and in particular relates to a gain adjustment circuit of a voltage-controlled oscillator of a charge pump phase-locked loop and a charge pump phase-locked loop. Background Art
[0002] An ordinary charge pump phase-locked loop can adjust the control voltage of the voltage-controlled oscillator by charging and discharging the LPF through a loop using a charge pump to obtain an ideal output frequency clock. However, the KVCO (gain of the voltage-controlled oscillator, frequency change / voltage change) of the voltage-controlled oscillator of the charge pump phase-locked loop cannot be adjusted. The present invention achieves adjustable KVCO of the voltage-controlled oscillator through a gain adjustment circuit of the voltage-controlled oscillator of the charge pump phase-locked loop. Summary of the invention
[0003] In view of the deficiencies in the prior art, the present invention provides a gain adjustment circuit of a voltage-controlled oscillator of a charge pump phase-locked loop and a charge pump phase-locked loop.
[0004] The technical solution of the present invention is as follows:
[0005] A gain adjustment circuit for a voltage-controlled oscillator of a charge pump phase-locked loop, comprising:
[0006] A calibrated output module comprising:
[0007] A first D flip-flop, whose data input terminal and reset terminal are both input with a first enable signal, whose clock input terminal is input with a first clock signal, and whose Q terminal outputs a first reset signal;
[0008] A second D flip-flop, whose clock input terminal is input with the first clock signal, and whose reset terminal is electrically connected to the Q terminal of the first D flip-flop;
[0009] A first inverter, an input terminal of which is electrically connected to the Q terminal of the second D flip-flop, and an output terminal of which is electrically connected to the data input terminal of the second D flip-flop;
[0010] a third D flip-flop, whose clock input terminal is electrically connected to the Q terminal of the second D flip-flop, and whose reset terminal is electrically connected to the Q terminal of the first D flip-flop;
[0011] a second inverter, an input end of which is electrically connected to the Q end of the third D flip-flop, and an output end of which is electrically connected to the data input end of the third D flip-flop;
[0012] a third inverter, an input terminal of which is electrically connected to a Q terminal of a third D flip-flop;
[0013] a fourth D flip-flop, whose clock input terminal is electrically connected to the output terminal of the third inverter, whose reset terminal is electrically connected to the Q terminal of the first D flip-flop, and whose Q terminal outputs the first frequency-divided signal;
[0014] a fourth inverter, an input end of which is electrically connected to the Q end of the fourth D flip-flop, and an output end of which is electrically connected to the data input end of the fourth D flip-flop;
[0015] a fifth D flip-flop, whose clock input terminal is electrically connected to the Q terminal of the fourth D flip-flop, whose reset terminal is electrically connected to the Q terminal of the first D flip-flop, and whose Q terminal outputs a second enable signal;
[0016] a sixth D flip-flop, whose clock input terminal is electrically connected to the Q terminal of the fourth D flip-flop, whose reset terminal is electrically connected to the Q terminal of the first D flip-flop, and whose Q terminal outputs an adjustment completion signal;
[0017] a fifth inverter, an input terminal of which is electrically connected to the Q terminal of the sixth D flip-flop;
[0018] a sixth inverter, an input terminal of which is electrically connected to the Q terminal of the fifth D flip-flop;
[0019] a first AND gate, wherein a first input terminal thereof is electrically connected to the output terminal of the fifth inverter, a second input terminal thereof is electrically connected to the output terminal of the sixth inverter, and an output terminal thereof is electrically connected to the data input terminal of the fifth D flip-flop;
[0020] a first OR gate, wherein a first input terminal thereof is electrically connected to the Q terminal of the fifth D flip-flop, a second input terminal thereof is electrically connected to the Q terminal of the sixth D flip-flop, and an output terminal thereof is electrically connected to the data input terminal of the sixth D flip-flop;
[0021] The gear adjustment module comprises:
[0022] a seventh inverter, an input terminal of which inputs the second enable signal, and an output terminal of which outputs the third enable signal;
[0023] a seventh D flip-flop, whose data input terminal and reset terminal are both input with the second enable signal, and whose clock input terminal is input with the first clock signal;
[0024] an eighth D flip-flop, whose data input terminal is electrically connected to the Q terminal of the seventh D flip-flop, whose clock input terminal is input with the first clock signal, and whose reset terminal is input with the second enable signal;
[0025] a ninth D flip-flop, wherein the data input terminal and the reset terminal thereof are both input with the second enable signal, and the clock input terminal thereof is input with the first clock signal;
[0026] an XOR gate, a first input terminal of which is electrically connected to the Q terminal of the eighth D flip-flop, and a second input terminal of which is electrically connected to the Q terminal of the ninth D flip-flop;
[0027] The gear adjustment configuration word generating unit includes five-level bit generating subunits; wherein the five-level bit generating subunits have the same structure and all include:
[0028] An eighth inverter, an input terminal of which is input with the first clock signal;
[0029] a tenth D flip-flop, whose data input terminal serves as the input terminal of the bit generating sub-unit, whose clock input terminal is electrically connected to the output terminal of the eighth inverter, whose reset terminal inputs the second enable signal, and whose Q terminal serves as the output terminal of the bit generating sub-unit;
[0030] a first NOR gate, a first input terminal of which is electrically connected to the Q terminal of the tenth D flip-flop;
[0031] A ninth inverter, an input terminal of which is input with a highest carry signal;
[0032] a second AND gate, a first input terminal of which is electrically connected to the Q terminal of the tenth D flip-flop, and a second input terminal of which is electrically connected to the output terminal of the ninth inverter;
[0033] a second NOR gate, whose first input terminal is electrically connected to the output terminal of the first NOR gate, whose second input terminal is electrically connected to the output terminal of the seventh inverter, whose third input terminal is electrically connected to the output terminal of the second AND gate, and whose output terminal is electrically connected to the second input terminal of the first NOR gate;
[0034] a tenth inverter, whose input end is electrically connected to the output end of the first NOR gate, and whose output end outputs a bit signal of the gear adjustment configuration word;
[0035] The input end of the first-level bit generating subunit is electrically connected to the output end of the XOR gate, and the first-level bit generating subunit, the second-level bit generating subunit, the third-level bit generating subunit, the fourth-level bit generating subunit, and the fifth-level bit generating subunit are connected in series in sequence;
[0036] The calibration control module is used to adjust the jump of the completion signal by sampling the jump of the completion signal through a D trigger for two beats using the reference clock of the charge pump phase-locked loop and then outputting a first enable signal.
[0037] Also includes:
[0038] The clock signal generating module is used to generate a counting clock signal, a first clock signal and a reset signal based on a reference clock of a charge pump phase-locked loop and a first enable signal.
[0039] The clock signal generating module comprises:
[0040] an eleventh D flip-flop, wherein the data input terminal and the reset terminal are both input with the first enable signal, the clock input terminal is input with the reference clock of the charge pump phase-locked loop, and the Q terminal outputs the second reset signal;
[0041] A two-frequency divider, whose input terminal is input with a reference clock of a charge pump phase-locked loop, whose reset terminal is electrically connected with a Q terminal of an eleventh D flip-flop, and whose output terminal outputs a second frequency-divided signal;
[0042] a twelfth D flip-flop, whose clock input terminal is electrically connected to the output terminal of the two-frequency divider, whose reset terminal is electrically connected to the Q terminal of the eleventh D flip-flop, and whose Q terminal outputs a logic control word; wherein the logic control word includes a first logic control bit signal, a second logic control bit signal, and a third logic control bit signal;
[0043] A second adder, a first input end of which is electrically connected to the Q end of the twelfth D flip-flop, a second input end of which includes a first input terminal, a second input terminal and a third input terminal, and an output end of which is electrically connected to the data input end of the twelfth D flip-flop; wherein the third input terminal, the second input terminal and the first input terminal respectively input a low level signal, a low level signal and a high level signal in a one-to-one correspondence, the low level signal corresponds to the first logic control bit signal, the low level signal input to the second input terminal corresponds to the second logic control bit signal, and the low level signal input to the third input terminal corresponds to the third logic control bit signal;
[0044] an eleventh inverter, an input terminal of which is input with a first logic control bit signal;
[0045] A twelfth inverter, an input terminal of which is input with a third logic control bit signal;
[0046] A NAND gate, a first input terminal of which is electrically connected to the output terminal of the eleventh inverter, a second input terminal of which is input with a second logic control bit signal, and a third input terminal of which is electrically connected to the output terminal of the twelfth inverter;
[0047] a thirteenth inverter, an input end of which is electrically connected to the output end of the two-frequency divider;
[0048] a thirteenth D flip-flop, whose data input terminal is electrically connected to the output terminal of the NAND gate, whose clock input terminal is electrically connected to the output terminal of the thirteenth inverter, whose reset terminal is electrically connected to the Q terminal of the eleventh D flip-flop, and whose Q terminal outputs the first clock signal;
[0049] a fourteenth D flip-flop, whose data input terminal is electrically connected to the Q terminal of the thirteenth D flip-flop, whose clock input terminal is electrically connected to the output terminal of the thirteenth inverter, whose reset terminal is electrically connected to the Q terminal of the eleventh D flip-flop, and whose Q terminal outputs a reset signal;
[0050] A fourteenth inverter, an input terminal of which is input with a third logic control bit signal;
[0051] The data input terminal of the fifteenth D flip-flop is electrically connected to the output terminal of the divider, the clock input terminal is electrically connected to the output terminal of the fourteenth inverter, the reset terminal is electrically connected to the Q terminal of the eleventh D flip-flop, and the Q terminal outputs a counting clock signal.
[0052] Also includes:
[0053] The counter starts counting the second clock signal output by the voltage controlled oscillator of the charge pump phase-locked loop in response to the counting clock signal, and outputs a loop frequency division configuration word.
[0054] After a round of counting is completed, the counter is reset by a reset signal.
[0055] Also includes:
[0056] The first adder is used for accumulating the loop frequency division configuration word and the loop frequency division default configuration word of the charge pump phase-locked loop to obtain a highest carry signal.
[0057] When the loop frequency division configuration word is greater than the loop frequency division default configuration word, the highest carry signal is 1; when the loop frequency division configuration word is less than or equal to the loop frequency division default configuration word, the highest carry signal is 0.
[0058] The calibration control module comprises:
[0059] An eighteenth D flip-flop, whose data input terminal and reset terminal are both input with an external overall enable signal, and whose clock input terminal is input with a reference clock of a charge pump phase-locked loop;
[0060] A second OR gate, a first input terminal of which inputs an adjustment completion signal;
[0061] a sixteenth D flip-flop, whose data input terminal is electrically connected to the output terminal of the second OR gate, whose clock input terminal is input with the reference clock of the charge pump phase-locked loop, whose reset terminal is electrically connected to the Q terminal of the eighteenth D flip-flop, and whose Q terminal is electrically connected to the second input terminal of the second OR gate;
[0062] a fifteenth inverter, an input terminal of which is electrically connected to the Q terminal of the sixteenth D flip-flop;
[0063] The seventeenth D flip-flop has its data input terminal electrically connected to the output terminal of the fifteenth inverter, its clock input terminal inputs the reference clock of the charge pump phase-locked loop, its reset terminal is electrically connected to the Q terminal of the eighteenth D flip-flop, and its Q terminal outputs the first enable signal.
[0064] A charge pump phase-locked loop, comprising:
[0065] A gain adjustment circuit for a voltage controlled oscillator of the charge pump phase-locked loop;
[0066] A phase and frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a frequency divider which are electrically connected in sequence and form a loop;
[0067] A voltage output module, whose input terminal inputs the current output by the bandgap reference, and whose output terminal is electrically connected to the output terminal of the charge pump;
[0068] Among them, the adjustment completion signal controls the phase detector, charge pump, frequency divider, and voltage output module to work or not work; when the phase detector, charge pump, and frequency divider are working, the voltage output module is not working; when the phase detector, charge pump, and frequency divider are not working, the voltage output module is working; the gear adjustment configuration word is input into the voltage-controlled oscillator.
[0069] The voltage output module comprises:
[0070] The PMOS tube has a source electrode serving as an input terminal of the voltage output module, a gate electrode serving as an adjustment completion signal, and a drain electrode serving as an output terminal of the voltage output module;
[0071] The resistor has one end electrically connected to the drain of the PMOS tube and the other end grounded.
[0072] The beneficial effects of the present invention are as follows:
[0073] The present invention can realize the adjustable voltage-controlled oscillator KVCO. Since KVCO will amplify the noise introduced by the charge pump and the loop filter, when KVCO is too large, the noise amplification capability will be stronger. The present invention reduces KVCO through the gain adjustment circuit of the voltage-controlled oscillator of the charge pump phase-locked loop, thereby reducing its noise amplification capability and optimizing the phase noise of the charge pump phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS
[0074] Figure 1 It is a schematic diagram of the structure of the charge pump phase-locked loop of the present invention;
[0075] Figure 2 is a circuit diagram of a voltage output module of the present invention;
[0076] Figure 3 It is a structural schematic diagram of a gain adjustment circuit of a voltage-controlled oscillator of a charge pump phase-locked loop of the present invention;
[0077] Figure 4 A circuit diagram of a clock signal generating module of the present invention;
[0078] Figure 5 It is a basic waveform diagram of the clock signal generating module of the present invention;
[0079] Figure 6 It is a structural schematic diagram of the calibration output module of the present invention;
[0080] Figure 7 It is a structural schematic diagram of the gear adjustment module of the present invention;
[0081] Figure 8 A waveform diagram of the gear adjustment configuration word output by the calibration output module that changes with the highest carry signal;
[0082] Fig. 9It is a structural schematic diagram of the calibration control module of the present invention. DETAILED DESCRIPTION
[0083] The present invention is further described below by means of specific examples, but is not limited thereto.
[0084] See also Figure 1 A charge pump phase-locked loop in many embodiments of the present invention includes a gain adjustment circuit of a voltage-controlled oscillator of the charge pump phase-locked loop, a phase detector and a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider and a voltage output module.
[0085] The gain adjustment circuit of the voltage controlled oscillator of the charge pump phase-locked loop is used to generate the adjustment completion signal Trim_done and the gear adjustment configuration word Vco_set<4:0> based on the reference clock Ckref of the charge pump phase-locked loop, the loop frequency division default configuration word N<10:0> and the second clock signal Ck_hs output by the voltage controlled oscillator of the charge pump phase-locked loop. The gain adjustment circuit of the voltage controlled oscillator of the charge pump phase-locked loop will be described in detail later.
[0086] The phase and frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator and the frequency divider are electrically connected in sequence to form a loop.
[0087] The phase and frequency detector outputs a second signal Up and a third signal Down to the charge pump. The second signal Up and the third signal Down are used to control whether the charge pump is in a charging state or a discharging state, thereby affecting the size of the VCO control voltage Vctl. The size of the VCO control voltage Vctl directly affects the output frequency of the voltage-controlled oscillator and its KVCO size.
[0088] The input end of the voltage output module inputs the current I output by the bandgap reference, the output end of the voltage output module is electrically connected to the output end of the charge pump, and the output end of the voltage output module outputs the VCO control voltage Vctl to control the output frequency of the voltage controlled oscillator and its KVCO. For details, see Figure 2 The voltage output module includes a PMOS tube PM and a resistor R.
[0089] The source of the PMOS tube PM serves as the input end of the voltage output module, the gate of the PMOS tube PM inputs the adjustment completion signal Trim_done, the drain of the PMOS tube PM serves as the output end of the voltage output module, and the output end of the voltage output module outputs the VCO control voltage Vctl, that is, the drain of the PMOS tube PM outputs the VCO control voltage Vctl.
[0090] One end of the resistor R is electrically connected to the drain of the PMOS tube, and the other end of the resistor R is grounded GND.
[0091] The trim completion signal Trim_done controls the phase detector, charge pump, frequency divider, and voltage output module to work or not work. When the phase detector, charge pump, and frequency divider work, the voltage output module does not work; when the phase detector, charge pump, and frequency divider do not work, the voltage output module works. For example, when the trim completion signal Trim_done is at a low level, the phase detector, charge pump, and frequency divider do not work, and the voltage output module works; when the trim completion signal Trim_done is at a high level, the phase detector, charge pump, and frequency divider work, and the voltage output module works. In contrast, the loop filter and the voltage-controlled oscillator are not controlled by the trim completion signal Trim_done and always work. The loop frequency division default configuration word N<10:0> is input to the frequency divider, and the loop frequency division default configuration word N<10:0> controls the frequency division size of the frequency divider and its output clock frequency. The reference clock Ckref is input into the phase and frequency detector. The reference clock Ckref is an external clock input and is used to compare with the feedback clock generated by the charge pump phase-locked loop, that is, the third frequency-divided signal Ck_fb. The voltage-controlled oscillator outputs the second clock signal Ck_hs. The frequency divider outputs the third frequency-divided signal Ck_fb.
[0092] The gear adjustment configuration word Vco_set<4:0> is input into the voltage controlled oscillator. By changing the gear adjustment configuration word Vco_set<4:0>, the output frequency of the voltage controlled oscillator is changed, that is, the frequency of the second clock signal Ck_hs is changed.
[0093] See also Figure 3 A gain adjustment circuit of a voltage controlled oscillator of a charge pump phase-locked loop in many embodiments of the present invention includes a clock signal generation module, a counter, a first adder, a calibration output module and a calibration control module. The clock signal generation module, the counter, the first adder, the calibration output module and the calibration control module are electrically connected in sequence to form a calibration loop.
[0094] The clock signal generating module is used to generate a counting clock signal Ck_pwl, a first clock signal Ck_load and a reset signal Ck_rst based on a reference clock Ckref of a charge pump phase-locked loop and a first enable signal En_trim.
[0095] For details, see Figure 4 The clock signal generating module includes an eleventh D flip-flop D11, a divider div2, a twelfth D flip-flop D12, a second adder add2, an eleventh inverter inv11, a twelfth inverter inv12, a NAND gate nand, a thirteenth inverter inv13, a thirteenth D flip-flop D13, a fourteenth D flip-flop D14, a fourteenth inverter inv14, and a fifteenth D flip-flop D15.
[0096] The data input terminal of the eleventh D flip-flop D11 and the reset terminal of the eleventh D flip-flop D11 both input the first enable signal En_trim, the clock input terminal of the eleventh D flip-flop D11 inputs the reference clock Ckref of the charge pump phase-locked loop, and the Q terminal of the eleventh D flip-flop D11 outputs the second reset signal Rst.
[0097] The reference clock Ckref is input to the input terminal of the frequency divider div2, the reset terminal of the frequency divider div2 is electrically connected to the Q terminal of the eleventh D flip-flop D11, and the output terminal of the frequency divider div2 outputs the second frequency division signal Ckref_div2.
[0098] The clock input terminal of the twelfth D flip-flop D12 is electrically connected to the output terminal of the divider div2, the reset terminal of the twelfth D flip-flop D12 is electrically connected to the Q terminal of the eleventh D flip-flop D11, and the Q terminal of the twelfth D flip-flop D12 outputs the logic control word Dbuf<2:0>. The logic control word Dbuf<2:0> includes the first logic control bit signal Dbuf <0> , the second logic control bit signal Dbuf <1> , the third logic control bit signal Dbuf <2> .
[0099] The first input end of the second adder add2 is electrically connected to the Q end of the twelfth D flip-flop D12, and the second input end of the second adder add2 includes a first input terminal, a second input terminal and a third input terminal, and the third input terminal, the second input terminal and the first input terminal respectively correspond to input a low level signal vlo, a low level signal vlo and a high level signal vhi, wherein the low level signal vhi is in correspondence with the first logic control bit signal Dbuf <0> Correspondingly, the low level signal vlo input to the second input terminal and the second logic control bit signal Dbuf <1> Correspondingly, the low level signal vlo input to the third input terminal and the third logic control bit signal Dbuf <2> In other words, the low-level signal vlo represents a binary "0", and the high-level signal vhi represents a binary "1", that is, the second input terminal of the second adder add2 inputs 001, and when the second adder add2 performs an addition operation, its output result is: 001+logic control word Dbuf<2:0>. The output terminal of the second adder add2 is electrically connected to the data input terminal of the twelfth D flip-flop D12.
[0100] The input terminal of the eleventh inverter inv11 inputs the first logic control bit signal Dbuf <0> .
[0101] The input terminal of the twelfth inverter inv12 inputs the third logic control bit signal Dbuf <2> .
[0102] The first input terminal of the NAND gate nand is electrically connected to the output terminal of the eleventh inverter inv11, and the second input terminal of the NAND gate nand inputs the second logic control bit signal Dbuf <1> , the third input terminal of the NAND gate nand is electrically connected to the output terminal of the twelfth inverter inv12.
[0103] An input terminal of the thirteenth inverter inv13 is electrically connected to an output terminal of the frequency divider div2.
[0104] The data input terminal of the thirteenth D flip-flop D13 is electrically connected to the output terminal of the NAND gate nand, the clock input terminal of the thirteenth D flip-flop D13 is electrically connected to the output terminal of the thirteenth inverter inv13, the reset terminal of the thirteenth D flip-flop D13 is electrically connected to the Q terminal of the eleventh D flip-flop D11, and the Q terminal of the thirteenth D flip-flop D13 outputs the first clock signal Ck_load.
[0105] The data input terminal of the fourteenth D flip-flop D14 is electrically connected to the Q terminal of the thirteenth D flip-flop D13, the clock input terminal of the fourteenth D flip-flop D14 is electrically connected to the output terminal of the thirteenth inverter inv13, the reset terminal of the fourteenth D flip-flop D14 is electrically connected to the Q terminal of the eleventh D flip-flop D11, and the Q terminal of the fourteenth D flip-flop D14 outputs a reset signal Ck_rst.
[0106] The input terminal of the fourteenth inverter inv14 inputs the third logic control bit signal Dbuf <2> .
[0107] The data input terminal of the fifteenth D flip-flop D15 is electrically connected to the output terminal of the divider div2, the clock input terminal of the fifteenth D flip-flop D15 is electrically connected to the output terminal of the fourteenth inverter inv14, the reset terminal of the fifteenth D flip-flop D15 is electrically connected to the Q terminal of the eleventh D flip-flop D11, and the Q terminal of the fifteenth D flip-flop D15 outputs the counting clock signal Ck_pwl.
[0108] It can be seen that the clock signal generating module first uses the reference clock Ckref to sample the first enable signal En_trim signal to confirm the timing, and uses the second frequency division signal Ckref_div2 to sample the output result of the second adder add2 to obtain the logic control word Dbuf<2:0>, and then uses the logic control word Dbuf<2:0> to perform logic to obtain the counting clock signal Ck_pwl, the first clock signal Ck_load, and the reset signal Ck_rst.
[0109] like Figure 5 , Figure 5 It is a basic waveform diagram of the clock signal generation module, where Tckref represents the size of one cycle of the reference clock Ckref. Figure 5In the figure, 8*Tckref is 8 times Tckref, which means 8 times one cycle of the reference clock Ckref; 2*Tckref is 2 times Tckref, which means 2 times one cycle of the reference clock Ckref.
[0110] The counter starts counting the second clock signal Ck_hs output by the voltage-controlled oscillator of the charge pump phase-locked loop in response to the counting clock signal Ck_pwl, and outputs the loop frequency division configuration word Nc<10:0>. After a round of counting, the counter is reset by the reset signal Ck_rst. For example, when the counting clock signal Ck_pwl is at a high level, the counter starts counting the second clock signal Ck_hs, and is reset by the reset signal Ck_rst after a round of counting.
[0111] The first adder is used to accumulate the loop frequency division configuration word Nc<10:0> and the loop frequency division default configuration word N<10:0> of the charge pump phase-locked loop to obtain the highest carry signal Cmp_result. Specifically, when the loop frequency division configuration word Nc<10:0> is greater than the loop frequency division default configuration word N<10:0>, the highest carry signal Cmp_result is 1; when the loop frequency division configuration word Nc<10:0> is less than or equal to the loop frequency division default configuration word N<10:0>, the highest carry signal Cmp_result is 0.
[0112] See also Figure 6 The calibration output module includes a first D flip-flop D1, a second D flip-flop D2, a first inverter inv1, a third D flip-flop D3, a second inverter inv2, a third inverter inv3, a fourth D flip-flop D4, a fourth inverter inv4, a fifth D flip-flop D5, a sixth D flip-flop D6, a fifth inverter inv5, a sixth inverter inv6, a first AND gate and1, a first OR gate or1, and a gear adjustment module.
[0113] The data input terminal of the first D flip-flop D1 and the reset terminal of the first D flip-flop D1 both input the first enable signal En_trim, the clock input terminal of the first D flip-flop D1 inputs the first clock signal Ck_load, and the Q terminal of the first D flip-flop D1 outputs the first reset signal pd.
[0114] The first clock signal Ck_load is input to a clock input terminal of the second D flip-flop D2 , and a reset terminal of the second D flip-flop D2 is electrically connected to a Q terminal of the first D flip-flop D1 .
[0115] An input terminal of the first inverter inv1 is electrically connected to a Q terminal of the second D flip-flop D2 , and an output terminal of the first inverter inv1 is electrically connected to a data input terminal of the second D flip-flop D2 .
[0116] A clock input terminal of the third D flip-flop D3 is electrically connected to the Q terminal of the second D flip-flop D2 , and a reset terminal of the third D flip-flop D3 is electrically connected to the Q terminal of the first D flip-flop D1 .
[0117] An input terminal of the second inverter inv2 is electrically connected to a Q terminal of the third D flip-flop D3 , and an output terminal of the second inverter inv2 is electrically connected to a data input terminal of the third D flip-flop D3 .
[0118] An input terminal of the third inverter inv3 is electrically connected to a Q terminal of the third D flip-flop D3.
[0119] The clock input terminal of the fourth D flip-flop D4 is electrically connected to the output terminal of the third inverter inv3, the reset terminal of the fourth D flip-flop D4 is electrically connected to the Q terminal of the first D flip-flop D1, and the Q terminal of the fourth D flip-flop D4 outputs the first frequency division signal Ck_div8.
[0120] An input terminal of the fourth inverter inv4 is electrically connected to the Q terminal of the fourth D flip-flop D4 , and an output terminal of the fourth inverter inv4 is electrically connected to the data input terminal of the fourth D flip-flop D4 .
[0121] The clock input terminal of the fifth D flip-flop D5 is electrically connected to the Q terminal of the fourth D flip-flop D4, the reset terminal of the fifth D flip-flop D5 is electrically connected to the Q terminal of the first D flip-flop, and the Q terminal of the fifth D flip-flop D5 outputs the second enable signal En.
[0122] The clock input terminal of the sixth D flip-flop D6 is electrically connected to the Q terminal of the fourth D flip-flop D4 , the reset terminal of the sixth D flip-flop D6 is electrically connected to the Q terminal of the first D flip-flop D1 , and the Q terminal of the sixth D flip-flop D6 outputs the trimming completion signal Trim_done.
[0123] An input terminal of the fifth inverter inv5 is electrically connected to a Q terminal of the sixth D flip-flop D6 .
[0124] An input terminal of the sixth inverter inv6 is electrically connected to the Q terminal of the fifth D flip-flop D5.
[0125] The first input terminal of the first AND gate and1 is electrically connected to the output terminal of the fifth inverter inv5, the second input terminal of the first AND gate and1 is electrically connected to the output terminal of the sixth inverter inv6, and the output terminal of the first AND gate and1 is electrically connected to the data input terminal of the fifth D flip-flop D5.
[0126] The first input terminal of the first OR gate or1 is electrically connected to the Q terminal of the fifth D flip-flop D5, the second input terminal of the first OR gate or1 is electrically connected to the Q terminal of the sixth D flip-flop D6, and the output terminal of the first OR gate or1 is electrically connected to the data input terminal of the sixth D flip-flop D6.
[0127] See also Figure 7 The gear adjustment module includes a seventh inverter inv7, a seventh D flip-flop D7, an eighth D flip-flop D8, a ninth D flip-flop D9, an XOR gate xor, and a gear adjustment configuration word generating unit.
[0128] The input terminal of the seventh inverter inv7 inputs the second enable signal En, and the output terminal of the seventh inverter inv7 outputs the third enable signal Enb.
[0129] The data input terminal of the seventh D flip-flop D7 and the reset terminal of the seventh D flip-flop D7 are both input with the second enable signal En, and the clock input terminal of the seventh D flip-flop D7 is input with the first clock signal Ck_load.
[0130] The data input terminal of the eighth D flip-flop D8 is electrically connected to the Q terminal of the seventh D flip-flop D7 , the clock input terminal of the eighth D flip-flop D8 inputs the first clock signal Ck_load, and the reset terminal of the eighth D flip-flop D8 inputs the second enable signal En.
[0131] The data input terminal of the ninth D flip-flop D9 and the reset terminal of the ninth D flip-flop D9 are both input with the second enable signal En, and the clock input terminal of the ninth D flip-flop D9 is input with the first clock signal Ck_load.
[0132] A first input terminal of the XOR gate xor is electrically connected to the Q terminal of the eighth D flip-flop D8 , and a second input terminal of the XOR gate xor is electrically connected to the Q terminal of the ninth D flip-flop.
[0133] The gear adjustment configuration word generating unit includes five-level bit generating subunits. The five-level bit generating subunits have the same structure and all include an eighth inverter inv8, a tenth D flip-flop D10, a first NOR gate nor1, a ninth inverter inv9, a second AND gate and2, a second NOR gate nor2, and a tenth inverter inv10.
[0134] The input terminal of the eighth inverter inv8 is input with the first clock signal Ck_load.
[0135] The data input terminal of the tenth D flip-flop D10 serves as the input terminal of the bit generating sub-unit, the clock input terminal of the tenth D flip-flop D10 is electrically connected to the output terminal of the eighth inverter inv8, the reset terminal of the tenth D flip-flop D10 inputs the second enable signal En, and the Q terminal of the tenth D flip-flop D10 serves as the output terminal of the bit generating sub-unit.
[0136] A first input terminal of the first NOR gate nor1 is electrically connected to a Q terminal of the tenth D flip-flop D10.
[0137] The input terminal of the ninth inverter inv9 is input with the highest carry signal Cmp_result.
[0138] A first input terminal of the second AND gate and2 is electrically connected to the Q terminal of the tenth D flip-flop D10 , and a second input terminal of the second AND gate and2 is electrically connected to the output terminal of the ninth inverter inv9 .
[0139] A first input terminal of the second NOR gate nor2 is electrically connected to the output terminal of the first NOR gate nor1, a second input terminal of the second NOR gate nor2 is electrically connected to the output terminal of the seventh inverter inv7, a third input terminal of the second NOR gate nor2 is electrically connected to the output terminal of the second AND gate and2, and the output terminal of the second NOR gate nor2 is electrically connected to the second input terminal of the first NOR gate nor1.
[0140] An input terminal of the tenth inverter inv10 is electrically connected to an output terminal of the first NOR gate nor1 , and an output terminal of the tenth inverter inv10 outputs a bit signal of the gear adjustment configuration word Vco_set<4:0>.
[0141] The input end of the first-level bit generating subunit is electrically connected to the output end of the XOR gate xor, and the first-level bit generating subunit, the second-level bit generating subunit, the third-level bit generating subunit, the fourth-level bit generating subunit, and the fifth-level bit generating subunit are connected in series in sequence, that is, the output end of the first-level bit generating subunit is electrically connected to the input end of the second-level bit generating subunit, the output end of the second-level bit generating subunit is electrically connected to the input end of the third-level bit generating subunit, the output end of the third-level bit generating subunit is electrically connected to the input end of the fourth-level bit generating subunit, and the output end of the fourth-level bit generating subunit is electrically connected to the input end of the fifth-level bit generating subunit.
[0142] The tenth inverter inv10 of the first-stage bit generation subunit outputs the fifth bit signal Vco_set of the gear adjustment configuration word Vco_set<4:0> <4> , the tenth inverter inv10 of the second-stage bit generation subunit outputs the fourth bit signal Vco_set of the gear adjustment configuration word Vco_set<4:0> <3> , the tenth inverter inv10 of the third-level bit generation subunit outputs the third bit signal Vco_set of the gear adjustment configuration word Vco_set<4:0> <2> , the tenth inverter inv10 of the fourth-stage bit generation subunit outputs the second bit signal Vco_set of the gear adjustment configuration word Vco_set<4:0> <1> The tenth inverter inv10 of the fifth-stage bit generation subunit outputs the first bit signal Vco_set of the gear adjustment configuration word Vco_set<4:0> <0> .
[0143] See also Figure 7 , Figure 8When the second enable signal En signal jumps, the entire gear adjustment module starts to work. The key point of the gear adjustment module is that the output state of the three-input NOR gate, that is, the second NOR gate nor2, is controlled by the highest carry signal Cmp_result and each bit output will be locked and no longer change after the clock completes two cycle jumps, unless the second enable signal En signal is reset, thereby achieving the purpose of outputting different waveforms of the gear adjustment configuration word Vco_set<4:0> as the highest carry signal Cmp_result changes. The specific waveform changes and approximate logical functions of the gear adjustment configuration word Vco_set<4:0> are listed in the following Table 1.
[0144] Table 1 Basic logic function table of calibration output module
[0145]
[0146]
[0147] Table 1 does not reflect the phenomenon that the gear adjustment configuration word Vco_set<4:0> changes with the change of the highest carry signal Cmp_result. Figure 8 To supplement.
[0148] See also Figure 6 , Figure 7 , Figure 8 As shown in Table 1, the calibration output module controls the relationship between the adjustment completion signal Trim_done and the gear adjustment configuration word Vco_set<4:0> through the first clock signal Ck_load. The first frequency division signal Ck_div8 is an 8-frequency division clock of the first clock signal Ck_load. Note that there is a third inverter inv3 between the second and third frequency divisions of the first clock signal Ck_load, so that the VCO control voltage Vctl is stable when the rising edge of the first frequency division signal Ck_div8 arrives. When the first rising edge of the first frequency division signal Ck_div8 arrives, the second enable signal En will jump, and the gear adjustment module starts to work. The gear adjustment module is as follows: Figure 7 When the second rising edge of the first frequency division signal Ck_div8 arrives, the adjustment completion signal Trim_done will jump from 0 to 1 and the adjustment completion signal Trim_done output by the calibration output module will be locked to 1, and at this time the second enable signal En will jump again, and the gear adjustment module will be turned off, which means that the work of the gear adjustment module needs to be completed within one clock cycle of the first frequency division signal Ck_div8.
[0149] See also Fig. 9The calibration control module includes a second OR gate or2, a sixteenth D flip-flop D16, a seventeenth D flip-flop D17, an eighteenth D flip-flop D18, and a fifteenth inverter inv15.
[0150] The data input terminal and the reset terminal of the eighteenth D flip-flop D18 are both input with the external overall enable signal Pll_en, and the clock input terminal of the eighteenth D flip-flop D18 is input with the reference clock Ckref.
[0151] The first input terminal of the second OR gate or2 inputs the trimming completion signal Trim_done.
[0152] The data input terminal of the sixteenth D flip-flop D16 is electrically connected to the output terminal of the second OR gate or2, the clock input terminal of the sixteenth D flip-flop D16 inputs the reference clock Ckref, the reset terminal of the sixteenth D flip-flop D16 is electrically connected to the Q terminal of the eighteenth D flip-flop D18, and the Q terminal of the sixteenth D flip-flop D16 is electrically connected to the second input terminal of the second OR gate or2.
[0153] An input terminal of the fifteenth inverter inv15 is electrically connected to a Q terminal of the sixteenth D flip-flop D16.
[0154] The data input terminal of the seventeenth D flip-flop D17 is electrically connected to the output terminal of the fifteenth inverter inv15, the clock input terminal of the seventeenth D flip-flop D17 inputs the reference clock Ckref, the reset terminal of the seventeenth D flip-flop D17 is electrically connected to the Q terminal of the eighteenth D flip-flop D18, and the Q terminal of the seventeenth D flip-flop D17 outputs the first enable signal En_trim.
[0155] See also Fig. 9 When the external overall enable signal Pll_en jumps, the entire calibration control module starts to work. When the adjustment completion signal Trim_done jumps, the calibration control module uses the reference clock Ckref of the charge pump phase-locked loop to sample the jump of the adjustment completion signal Trim_done for two beats through the D trigger and then outputs the first enable signal En_trim, where Pll_en is the external overall enable signal, which is also used as the enable signal of the calibration control module.
[0156] Working principle:
[0157] The KVCO of the voltage controlled oscillator (VCO) of the charge pump phase-locked loop is equal to the output frequency change divided by the VCO control voltage change. When the VCO control voltage is large enough, the VCO output frequency change will decrease, that is, the VCO control voltage will affect the KVCO. The main structure of the gain adjustment circuit of the voltage controlled oscillator of the charge pump phase-locked loop is as follows: Figure 1 and Figure 3First, the output of the voltage output module is used as the VCO control voltage ( Figure 1 The voltage output module in the voltage controlled oscillator) and the original charge pump phase-locked loop is not working when the gain adjustment circuit of the voltage controlled oscillator is working ( Figure 1 The role of the signal Trim_done in Figure 1 The output voltage of the voltage output module in the VCO can make the VCO output frequency reach the ideal frequency. The configuration word Vco_set<4:0> has the following structure: Figure 3 The principle is to count with the second clock signal Ck_hs at a fixed Tckref (Tckref represents one cycle of the reference clock Ckref). The size of the loop frequency division configuration word Nc<10:0> is obtained by counting with the second clock signal Ck_hs at a fixed Tckref. The loop frequency division configuration word Nc<10:0> is compared with the loop frequency division default configuration word N<10:0> to obtain the highest carry signal Cmp_result. The level of the highest carry signal Cmp_result is adjusted to output the gear adjustment configuration word Vco_set<4:0>, and then the gear adjustment configuration word Vco_set<4:0> is input to the voltage controlled oscillator to adjust the output frequency of the voltage controlled oscillator, thereby forming a gain adjustment circuit of the voltage controlled oscillator of the charge pump phase-locked loop.
[0158] Figure 5 The high level of the counting clock signal ck_pwl in is 8*Tckref, that is, 8 times Tckref. 8 times Tckref is for the accuracy of the loop frequency division configuration word Nc<10:0>. Here, 8*Tckref corresponds to the default loop frequency division ratio, which must also be multiplied by 8. The calibration output module is a binary logic implementation as shown in Table 1. The gear adjustment configuration word Vco_set<4:0> is locked after 5 jumps. At this time, the second clock signal Ck_hs basically reaches the ideal frequency and the VCO control voltage Vctl is the ideal voltage at this time, thereby reducing KVCO. After locking, the calibration output module outputs the adjustment completion signal Trim_done, the first enable signal En_trim will jump, the voltage output module stops working, the phase detector, the charge pump, and the divider work normally, the charge pump phase-locked loop works normally, and the calibration output module stops working.
Claims
1. A gain adjustment circuit for a voltage controlled oscillator of a charge pump phase-locked loop, characterized in that: include: A calibrated output module comprising: A first D flip-flop (D1), whose data input terminal and reset terminal are both input with a first enable signal (En_trim), whose clock input terminal is input with a first clock signal (Ck_load), and whose Q terminal outputs a first reset signal (pd); A second D flip-flop (D2), whose clock input terminal is input with the first clock signal (Ck_load), and whose reset terminal is electrically connected to the Q terminal of the first D flip-flop (D1); A first inverter (inv1), an input end of which is electrically connected to the Q end of the second D flip-flop (D2), and an output end of which is electrically connected to the data input end of the second D flip-flop; a third D flip-flop (D3), whose clock input terminal is electrically connected to the Q terminal of the second D flip-flop (D2), and whose reset terminal is electrically connected to the Q terminal of the first D flip-flop (D1); A second inverter (inv2), an input end of which is electrically connected to the Q end of the third D flip-flop (D3), and an output end of which is electrically connected to the data input end of the third D flip-flop (D3); A third inverter (inv3), an input end of which is electrically connected to a Q end of a third D flip-flop (D3); a fourth D flip-flop (D4), whose clock input terminal is electrically connected to the output terminal of the third inverter (inv3), whose reset terminal is electrically connected to the Q terminal of the first D flip-flop (D1), and whose Q terminal outputs the first frequency division signal (Ck_div8); a fourth inverter (inv4), whose input end is electrically connected to the Q end of the fourth D flip-flop (D4), and whose output end is electrically connected to the data input end of the fourth D flip-flop (D4); a fifth D flip-flop (D5), whose clock input terminal is electrically connected to the Q terminal of the fourth D flip-flop (D4), whose reset terminal is electrically connected to the Q terminal of the first D flip-flop (D1), and whose Q terminal outputs a second enable signal (En); a sixth D flip-flop (D6), whose clock input terminal is electrically connected to the Q terminal of the fourth D flip-flop (D4), whose reset terminal is electrically connected to the Q terminal of the first D flip-flop (D1), and whose Q terminal outputs a trimming completion signal (Trim_done); a fifth inverter (inv5), an input terminal of which is electrically connected to a Q terminal of a sixth D flip-flop (D6); a sixth inverter (inv6), an input terminal of which is electrically connected to a Q terminal of a fifth D flip-flop (D5); a first AND gate, wherein a first input terminal is electrically connected to the output terminal of the fifth inverter (inv5), a second input terminal is electrically connected to the output terminal of the sixth inverter (inv6), and an output terminal is electrically connected to the data input terminal of the fifth D flip-flop (D5); a first OR gate (or1), wherein a first input terminal thereof is electrically connected to a Q terminal of a fifth D flip-flop (D5), a second input terminal thereof is electrically connected to a Q terminal of a sixth D flip-flop (D6), and an output terminal thereof is electrically connected to a data input terminal of the sixth D flip-flop (D6); The gear adjustment module comprises: a seventh inverter (inv7), an input terminal of which inputs the second enable signal (En), and an output terminal of which outputs a third enable signal (Enb); A seventh D flip-flop (D7), a data input terminal and a reset terminal of which are both input with the second enable signal (En), and a clock input terminal of which is input with the first clock signal (Ck_load); an eighth D flip-flop (D8), whose data input terminal is electrically connected to the Q terminal of the seventh D flip-flop (D7), whose clock input terminal is input with the first clock signal (Ck_load), and whose reset terminal is input with the second enable signal (En); A ninth D flip-flop (D9), a data input terminal and a reset terminal of which both input the second enable signal (En), and a clock input terminal of which input the first clock signal (Ck_load); an exclusive-OR gate (xor), a first input terminal of which is electrically connected to the Q terminal of the eighth D flip-flop (D8), and a second input terminal of which is electrically connected to the Q terminal of the ninth D flip-flop (D9); The gear adjustment configuration word generating unit includes five-level bit generating subunits; wherein the five-level bit generating subunits have the same structure and all include: An eighth inverter (inv8), an input terminal of which is input with the first clock signal (Ck_load); a tenth D flip-flop (D10), whose data input terminal serves as the input terminal of the bit generating subunit, whose clock input terminal is electrically connected to the output terminal of the eighth inverter (inv8), whose reset terminal inputs the second enable signal (En), and whose Q terminal serves as the output terminal of the bit generating subunit; A first NOR gate (nor1), a first input terminal of which is electrically connected to a Q terminal of a tenth D flip-flop (D10); A ninth inverter (inv9) has an input terminal inputting a highest carry signal (Cmp_result); A second AND gate (and2), a first input terminal of which is electrically connected to the Q terminal of the tenth D flip-flop (D10), and a second input terminal of which is electrically connected to the output terminal of the ninth inverter (inv9); a second NOR gate (nor2), a first input terminal of which is electrically connected to the output terminal of the first NOR gate (nor1), a second input terminal of which is electrically connected to the output terminal of the seventh inverter (inv7), a third input terminal of which is electrically connected to the output terminal of the second AND gate and2, and an output terminal of which is electrically connected to the second input terminal of the first NOR gate (nor1); a tenth inverter (inv10), whose input end is electrically connected to the output end of the first NOR gate (nor1), and whose output end outputs a bit signal of the gear adjustment configuration word (Vco_set<4:0>); The input end of the first-level bit generating subunit is electrically connected to the output end of the XOR gate (XOR), and the first-level bit generating subunit, the second-level bit generating subunit, the third-level bit generating subunit, the fourth-level bit generating subunit, and the fifth-level bit generating subunit are connected in series in sequence; The calibration control module is used to output the first enable signal (En_trim) after sampling the jump of the adjustment completion signal (Trim_done) twice through the D trigger using the reference clock (Ckref) of the charge pump phase-locked loop when the adjustment completion signal (Trim_done) jumps.
2. The gain adjustment circuit of the voltage controlled oscillator of the charge pump phase-locked loop according to claim 1, characterized in that: Also includes: The clock signal generating module is used to generate a counting clock signal (Ck_pwl), a first clock signal (Ck_load) and a reset signal (Ck_rst) based on a reference clock (Ckref) of a charge pump phase-locked loop and a first enable signal (En_trim).
3. The gain adjustment circuit of the voltage controlled oscillator of the charge pump phase-locked loop according to claim 2, characterized in that: The clock signal generating module comprises: an eleventh D flip-flop (D11), wherein the data input terminal and the reset terminal are both input with the first enable signal (En_trim), the clock input terminal is input with the reference clock (Ckref) of the charge pump phase-locked loop, and the Q terminal outputs the second reset signal (Rst); A frequency divider (div2), whose input terminal is input with a reference clock (Ckref) of a charge pump phase-locked loop, whose reset terminal is electrically connected to a Q terminal of an eleventh D flip-flop (D11), and whose output terminal outputs a second frequency-divided signal (Ckref_div2); The twelfth D flip-flop (D12) has a clock input terminal electrically connected to the output terminal of the divider (div2), a reset terminal electrically connected to the Q terminal of the eleventh D flip-flop (D11), and a Q terminal outputs a logic control word (Dbuf<2:0>); wherein the logic control word (Dbuf<2:0>) includes a first logic control bit signal (Dbuf <0> )、The second logic control bit signal (Dbuf <1> )、The third logic control bit signal (Dbuf <2> ); A second adder (add2), whose first input end is electrically connected to the Q end of the twelfth D flip-flop (D12), whose second input end includes a first input terminal, a second input terminal and a third input terminal, and whose output end is electrically connected to the data input end of the twelfth D flip-flop (D12); wherein the third input terminal, the second input terminal and the first input terminal respectively correspond to inputting a low level signal (vlo), a low level signal (vlo) and a high level signal (vhi), and the low level signal (vhi) corresponds to the first logic control bit signal (Dbuf <0> ), the low level signal (vlo) input to the second input terminal corresponds to the second logic control bit signal (Dbuf <1> ), the low level signal (vlo) input to the third input terminal corresponds to the third logic control bit signal (Dbuf <2> ) corresponding to; The eleventh inverter (inv11) has its input terminal inputted with the first logic control bit signal (Dbuf <0> ); The twelfth inverter (inv12) inputs the third logic control bit signal (Dbuf <2> ); A NAND gate (nand) has a first input terminal electrically connected to the output terminal of the eleventh inverter (inv11), and a second input terminal inputting a second logic control bit signal (Dbuf <1> ), a third input terminal of which is electrically connected to the output terminal of the twelfth inverter (inv12); a thirteenth inverter (inv13), an input end of which is electrically connected to the output end of the divider (div2); a thirteenth D flip-flop (D13), whose data input terminal is electrically connected to the output terminal of the NAND gate (nand), whose clock input terminal is electrically connected to the output terminal of the thirteenth inverter (inv13), whose reset terminal is electrically connected to the Q terminal of the eleventh D flip-flop (D11), and whose Q terminal outputs a first clock signal (Ck_load); a fourteenth D flip-flop (D14), whose data input terminal is electrically connected to the Q terminal of the thirteenth D flip-flop (D13), whose clock input terminal is electrically connected to the output terminal of the thirteenth inverter (inv13), whose reset terminal is electrically connected to the Q terminal of the eleventh D flip-flop (D11), and whose Q terminal outputs a reset signal (Ck_rst); The fourteenth inverter (inv14) inputs the third logic control bit signal (Dbuf <2> ); The fifteenth D flip-flop (D5) has a data input terminal electrically connected to the output terminal of the divider (div2), a clock input terminal electrically connected to the output terminal of the fourteenth inverter (inv14), a reset terminal electrically connected to the Q terminal of the eleventh D flip-flop (D11), and a Q terminal outputting a counting clock signal (Ck_pwl).
4. The gain adjustment circuit of the voltage controlled oscillator of the charge pump phase-locked loop according to claim 2 or 3, characterized in that: Also includes: The counter starts counting the second clock signal (Ck_hs) output by the voltage controlled oscillator of the charge pump phase-locked loop in response to the counting clock signal (Ck_pwl), and outputs the loop frequency division configuration word (Nc<10:0>).
5. The gain adjustment circuit of the voltage controlled oscillator of the charge pump phase-locked loop according to claim 4, characterized in that: After a round of counting is completed, the counter is reset by a reset signal (Ck_rst).
6. The gain adjustment circuit of the voltage controlled oscillator of the charge pump phase-locked loop according to claim 4, characterized in that: Also includes: The first adder is used for accumulating the loop frequency division configuration word (Nc<10:0>) and the loop frequency division default configuration word (N<10:0>) of the charge pump phase-locked loop to obtain a highest carry signal (Cmp_result).
7. The gain adjustment circuit of the voltage controlled oscillator of the charge pump phase-locked loop according to claim 6, characterized in that: When the loop frequency division configuration word (Nc<10:0>) is greater than the loop frequency division default configuration word (N<10:0>), the highest carry signal (Cmp_result) is 1; when the loop frequency division configuration word (Nc<10:0>) is less than or equal to the loop frequency division default configuration word (N<10:0>), the highest carry signal (Cmp_result) is 0.
8. The gain adjustment circuit of the voltage controlled oscillator of the charge pump phase-locked loop according to claim 1, characterized in that: The calibration control module comprises: An eighteenth D flip-flop (D18), whose data input terminal and reset terminal are both input with an external overall enable signal (Pll_en), and whose clock input terminal is input with a reference clock (Ckref) of a charge pump phase-locked loop; A second OR gate (or2), a trim completion signal (Trim_done) being input to a first input terminal thereof; a sixteenth D flip-flop (D16), whose data input terminal is electrically connected to the output terminal of the second OR gate (or2), whose clock input terminal is input with the reference clock (Ckref) of the charge pump phase-locked loop, whose reset terminal is electrically connected to the Q terminal of the eighteenth D flip-flop (D18), whose Q terminal is electrically connected to the second input terminal of the second OR gate (or2); a fifteenth inverter (inv15), an input terminal of which is electrically connected to a Q terminal of a sixteenth D flip-flop (D16); The seventeenth D flip-flop (D17) has a data input terminal electrically connected to the output terminal of the fifteenth inverter (inv15), a clock input terminal inputting a reference clock (Ckref) of a charge pump phase-locked loop, a reset terminal electrically connected to the Q terminal of the eighteenth D flip-flop (D18), and a Q terminal outputting a first enable signal (En_trim).
9. A charge pump phase-locked loop, characterized in that: include: A gain adjustment circuit for a voltage controlled oscillator of a charge pump phase-locked loop according to any one of claims 1 to 8; A phase and frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a frequency divider which are electrically connected in sequence and form a loop; A voltage output module, whose input terminal inputs the current output by the bandgap reference, and whose output terminal is electrically connected to the output terminal of the charge pump; Among them, the adjustment completion signal (Trim_done) controls the phase-frequency detector, charge pump, frequency divider, and voltage output module to work or not work; when the phase-frequency detector, charge pump, and frequency divider are working, the voltage output module is not working; when the phase-frequency detector, charge pump, and frequency divider are not working, the voltage output module is working; the gear adjustment configuration word (Vco_set<4:0>) is input to the voltage-controlled oscillator.
10. The charge pump phase-locked loop according to claim 9, characterized in that: The voltage output module comprises: The PMOS tube (PM) has its source as the input end of the voltage output module, its gate inputs the adjustment completion signal (Trim_done), and its drain serves as the output end of the voltage output module; The resistor (R) has one end electrically connected to the drain of the PMOS tube (PM) and the other end grounded.